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-rw-r--r--drivers/net/tg3.c97
1 files changed, 68 insertions, 29 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 73e271e59c6a..49ad60b72657 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -69,8 +69,8 @@
69 69
70#define DRV_MODULE_NAME "tg3" 70#define DRV_MODULE_NAME "tg3"
71#define PFX DRV_MODULE_NAME ": " 71#define PFX DRV_MODULE_NAME ": "
72#define DRV_MODULE_VERSION "3.56" 72#define DRV_MODULE_VERSION "3.58"
73#define DRV_MODULE_RELDATE "Apr 1, 2006" 73#define DRV_MODULE_RELDATE "May 22, 2006"
74 74
75#define TG3_DEF_MAC_MODE 0 75#define TG3_DEF_MAC_MODE 0
76#define TG3_DEF_RX_MODE 0 76#define TG3_DEF_RX_MODE 0
@@ -974,6 +974,8 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
974 return err; 974 return err;
975} 975}
976 976
977static void tg3_link_report(struct tg3 *);
978
977/* This will reset the tigon3 PHY if there is no valid 979/* This will reset the tigon3 PHY if there is no valid
978 * link unless the FORCE argument is non-zero. 980 * link unless the FORCE argument is non-zero.
979 */ 981 */
@@ -987,6 +989,11 @@ static int tg3_phy_reset(struct tg3 *tp)
987 if (err != 0) 989 if (err != 0)
988 return -EBUSY; 990 return -EBUSY;
989 991
992 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
993 netif_carrier_off(tp->dev);
994 tg3_link_report(tp);
995 }
996
990 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || 997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || 998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { 999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
@@ -1023,6 +1030,12 @@ out:
1023 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); 1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1024 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1031 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1025 } 1032 }
1033 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1034 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1035 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1036 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1037 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1038 }
1026 /* Set Extended packet length bit (bit 14) on all chips that */ 1039 /* Set Extended packet length bit (bit 14) on all chips that */
1027 /* support jumbo frames */ 1040 /* support jumbo frames */
1028 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 1041 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
@@ -3531,7 +3544,7 @@ static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3531 return IRQ_RETVAL(0); 3544 return IRQ_RETVAL(0);
3532} 3545}
3533 3546
3534static int tg3_init_hw(struct tg3 *); 3547static int tg3_init_hw(struct tg3 *, int);
3535static int tg3_halt(struct tg3 *, int, int); 3548static int tg3_halt(struct tg3 *, int, int);
3536 3549
3537#ifdef CONFIG_NET_POLL_CONTROLLER 3550#ifdef CONFIG_NET_POLL_CONTROLLER
@@ -3567,7 +3580,7 @@ static void tg3_reset_task(void *_data)
3567 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; 3580 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3568 3581
3569 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); 3582 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3570 tg3_init_hw(tp); 3583 tg3_init_hw(tp, 1);
3571 3584
3572 tg3_netif_start(tp); 3585 tg3_netif_start(tp);
3573 3586
@@ -4042,7 +4055,7 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4042 4055
4043 tg3_set_mtu(dev, tp, new_mtu); 4056 tg3_set_mtu(dev, tp, new_mtu);
4044 4057
4045 tg3_init_hw(tp); 4058 tg3_init_hw(tp, 0);
4046 4059
4047 tg3_netif_start(tp); 4060 tg3_netif_start(tp);
4048 4061
@@ -5719,9 +5732,23 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
5719 if (!netif_running(dev)) 5732 if (!netif_running(dev))
5720 return 0; 5733 return 0;
5721 5734
5722 spin_lock_bh(&tp->lock); 5735 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5723 __tg3_set_mac_addr(tp); 5736 /* Reset chip so that ASF can re-init any MAC addresses it
5724 spin_unlock_bh(&tp->lock); 5737 * needs.
5738 */
5739 tg3_netif_stop(tp);
5740 tg3_full_lock(tp, 1);
5741
5742 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5743 tg3_init_hw(tp, 0);
5744
5745 tg3_netif_start(tp);
5746 tg3_full_unlock(tp);
5747 } else {
5748 spin_lock_bh(&tp->lock);
5749 __tg3_set_mac_addr(tp);
5750 spin_unlock_bh(&tp->lock);
5751 }
5725 5752
5726 return 0; 5753 return 0;
5727} 5754}
@@ -5771,7 +5798,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5771} 5798}
5772 5799
5773/* tp->lock is held. */ 5800/* tp->lock is held. */
5774static int tg3_reset_hw(struct tg3 *tp) 5801static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5775{ 5802{
5776 u32 val, rdmac_mode; 5803 u32 val, rdmac_mode;
5777 int i, err, limit; 5804 int i, err, limit;
@@ -5786,7 +5813,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5786 tg3_abort_hw(tp, 1); 5813 tg3_abort_hw(tp, 1);
5787 } 5814 }
5788 5815
5789 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) 5816 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && reset_phy)
5790 tg3_phy_reset(tp); 5817 tg3_phy_reset(tp);
5791 5818
5792 err = tg3_chip_reset(tp); 5819 err = tg3_chip_reset(tp);
@@ -6327,7 +6354,7 @@ static int tg3_reset_hw(struct tg3 *tp)
6327 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 6354 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6328 } 6355 }
6329 6356
6330 err = tg3_setup_phy(tp, 1); 6357 err = tg3_setup_phy(tp, reset_phy);
6331 if (err) 6358 if (err)
6332 return err; 6359 return err;
6333 6360
@@ -6400,7 +6427,7 @@ static int tg3_reset_hw(struct tg3 *tp)
6400/* Called at device open time to get the chip ready for 6427/* Called at device open time to get the chip ready for
6401 * packet processing. Invoked with tp->lock held. 6428 * packet processing. Invoked with tp->lock held.
6402 */ 6429 */
6403static int tg3_init_hw(struct tg3 *tp) 6430static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6404{ 6431{
6405 int err; 6432 int err;
6406 6433
@@ -6413,7 +6440,7 @@ static int tg3_init_hw(struct tg3 *tp)
6413 6440
6414 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); 6441 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6415 6442
6416 err = tg3_reset_hw(tp); 6443 err = tg3_reset_hw(tp, reset_phy);
6417 6444
6418out: 6445out:
6419 return err; 6446 return err;
@@ -6461,6 +6488,10 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp)
6461 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); 6488 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6462 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); 6489 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6463 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); 6490 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6491
6492 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6493 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6494 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6464} 6495}
6465 6496
6466static void tg3_timer(unsigned long __opaque) 6497static void tg3_timer(unsigned long __opaque)
@@ -6683,7 +6714,7 @@ static int tg3_test_msi(struct tg3 *tp)
6683 tg3_full_lock(tp, 1); 6714 tg3_full_lock(tp, 1);
6684 6715
6685 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 6716 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6686 err = tg3_init_hw(tp); 6717 err = tg3_init_hw(tp, 1);
6687 6718
6688 tg3_full_unlock(tp); 6719 tg3_full_unlock(tp);
6689 6720
@@ -6748,7 +6779,7 @@ static int tg3_open(struct net_device *dev)
6748 6779
6749 tg3_full_lock(tp, 0); 6780 tg3_full_lock(tp, 0);
6750 6781
6751 err = tg3_init_hw(tp); 6782 err = tg3_init_hw(tp, 1);
6752 if (err) { 6783 if (err) {
6753 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 6784 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6754 tg3_free_rings(tp); 6785 tg3_free_rings(tp);
@@ -7626,21 +7657,23 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7626 cmd->supported |= (SUPPORTED_1000baseT_Half | 7657 cmd->supported |= (SUPPORTED_1000baseT_Half |
7627 SUPPORTED_1000baseT_Full); 7658 SUPPORTED_1000baseT_Full);
7628 7659
7629 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) 7660 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7630 cmd->supported |= (SUPPORTED_100baseT_Half | 7661 cmd->supported |= (SUPPORTED_100baseT_Half |
7631 SUPPORTED_100baseT_Full | 7662 SUPPORTED_100baseT_Full |
7632 SUPPORTED_10baseT_Half | 7663 SUPPORTED_10baseT_Half |
7633 SUPPORTED_10baseT_Full | 7664 SUPPORTED_10baseT_Full |
7634 SUPPORTED_MII); 7665 SUPPORTED_MII);
7635 else 7666 cmd->port = PORT_TP;
7667 } else {
7636 cmd->supported |= SUPPORTED_FIBRE; 7668 cmd->supported |= SUPPORTED_FIBRE;
7669 cmd->port = PORT_FIBRE;
7670 }
7637 7671
7638 cmd->advertising = tp->link_config.advertising; 7672 cmd->advertising = tp->link_config.advertising;
7639 if (netif_running(dev)) { 7673 if (netif_running(dev)) {
7640 cmd->speed = tp->link_config.active_speed; 7674 cmd->speed = tp->link_config.active_speed;
7641 cmd->duplex = tp->link_config.active_duplex; 7675 cmd->duplex = tp->link_config.active_duplex;
7642 } 7676 }
7643 cmd->port = 0;
7644 cmd->phy_address = PHY_ADDR; 7677 cmd->phy_address = PHY_ADDR;
7645 cmd->transceiver = 0; 7678 cmd->transceiver = 0;
7646 cmd->autoneg = tp->link_config.autoneg; 7679 cmd->autoneg = tp->link_config.autoneg;
@@ -7839,7 +7872,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
7839 7872
7840 if (netif_running(dev)) { 7873 if (netif_running(dev)) {
7841 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 7874 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7842 tg3_init_hw(tp); 7875 tg3_init_hw(tp, 1);
7843 tg3_netif_start(tp); 7876 tg3_netif_start(tp);
7844 } 7877 }
7845 7878
@@ -7884,7 +7917,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
7884 7917
7885 if (netif_running(dev)) { 7918 if (netif_running(dev)) {
7886 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 7919 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7887 tg3_init_hw(tp); 7920 tg3_init_hw(tp, 1);
7888 tg3_netif_start(tp); 7921 tg3_netif_start(tp);
7889 } 7922 }
7890 7923
@@ -8427,6 +8460,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8427 8460
8428 tx_len = 1514; 8461 tx_len = 1514;
8429 skb = dev_alloc_skb(tx_len); 8462 skb = dev_alloc_skb(tx_len);
8463 if (!skb)
8464 return -ENOMEM;
8465
8430 tx_data = skb_put(skb, tx_len); 8466 tx_data = skb_put(skb, tx_len);
8431 memcpy(tx_data, tp->dev->dev_addr, 6); 8467 memcpy(tx_data, tp->dev->dev_addr, 6);
8432 memset(tx_data + 6, 0x0, 8); 8468 memset(tx_data + 6, 0x0, 8);
@@ -8522,7 +8558,7 @@ static int tg3_test_loopback(struct tg3 *tp)
8522 if (!netif_running(tp->dev)) 8558 if (!netif_running(tp->dev))
8523 return TG3_LOOPBACK_FAILED; 8559 return TG3_LOOPBACK_FAILED;
8524 8560
8525 tg3_reset_hw(tp); 8561 tg3_reset_hw(tp, 1);
8526 8562
8527 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) 8563 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8528 err |= TG3_MAC_LOOPBACK_FAILED; 8564 err |= TG3_MAC_LOOPBACK_FAILED;
@@ -8596,7 +8632,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8596 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); 8632 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8597 if (netif_running(dev)) { 8633 if (netif_running(dev)) {
8598 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 8634 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8599 tg3_init_hw(tp); 8635 tg3_init_hw(tp, 1);
8600 tg3_netif_start(tp); 8636 tg3_netif_start(tp);
8601 } 8637 }
8602 8638
@@ -9377,7 +9413,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9377 9413
9378 if ((page_off == 0) || (i == 0)) 9414 if ((page_off == 0) || (i == 0))
9379 nvram_cmd |= NVRAM_CMD_FIRST; 9415 nvram_cmd |= NVRAM_CMD_FIRST;
9380 else if (page_off == (tp->nvram_pagesize - 4)) 9416 if (page_off == (tp->nvram_pagesize - 4))
9381 nvram_cmd |= NVRAM_CMD_LAST; 9417 nvram_cmd |= NVRAM_CMD_LAST;
9382 9418
9383 if (i == (len - 4)) 9419 if (i == (len - 4))
@@ -10353,10 +10389,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10353 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) 10389 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10354 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; 10390 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10355 10391
10356 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 10392 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10357 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) && 10393 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10358 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)) 10394 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10359 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 10395 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10396 else
10397 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10398 }
10360 10399
10361 tp->coalesce_mode = 0; 10400 tp->coalesce_mode = 0;
10362 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && 10401 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
@@ -11569,7 +11608,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11569 tg3_full_lock(tp, 0); 11608 tg3_full_lock(tp, 0);
11570 11609
11571 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 11610 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11572 tg3_init_hw(tp); 11611 tg3_init_hw(tp, 1);
11573 11612
11574 tp->timer.expires = jiffies + tp->timer_offset; 11613 tp->timer.expires = jiffies + tp->timer_offset;
11575 add_timer(&tp->timer); 11614 add_timer(&tp->timer);
@@ -11603,7 +11642,7 @@ static int tg3_resume(struct pci_dev *pdev)
11603 tg3_full_lock(tp, 0); 11642 tg3_full_lock(tp, 0);
11604 11643
11605 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 11644 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11606 tg3_init_hw(tp); 11645 tg3_init_hw(tp, 1);
11607 11646
11608 tp->timer.expires = jiffies + tp->timer_offset; 11647 tp->timer.expires = jiffies + tp->timer_offset;
11609 add_timer(&tp->timer); 11648 add_timer(&tp->timer);