1 files changed, 34 insertions, 7 deletions

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index a5e182dd9819..084eff21b67a 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -548,6 +548,14 @@ enum {
         CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
         CHIP_ID_YUKON_OPT  = 0xbc, /* YUKON-2 Optima */
 };
+
+enum yukon_xl_rev {
+        CHIP_REV_YU_XL_A0  = 0,
+        CHIP_REV_YU_XL_A1  = 1,
+        CHIP_REV_YU_XL_A2  = 2,
+        CHIP_REV_YU_XL_A3  = 3,
+};
+
 enum yukon_ec_rev {
         CHIP_REV_YU_EC_A1    = 0,  /* Chip Rev. for Yukon-EC A1/A0 */
         CHIP_REV_YU_EC_A2    = 1,  /* Chip Rev. for Yukon-EC A2 */
@@ -557,6 +565,7 @@ enum yukon_ec_u_rev {
         CHIP_REV_YU_EC_U_A0  = 1,
         CHIP_REV_YU_EC_U_A1  = 2,
         CHIP_REV_YU_EC_U_B0  = 3,
+        CHIP_REV_YU_EC_U_B1  = 5,
 };
 enum yukon_fe_rev {
         CHIP_REV_YU_FE_A1    = 1,
@@ -685,8 +694,21 @@ enum {
         TXA_CTRL        = 0x0210,/*  8 bit      Tx Arbiter Control Register */
         TXA_TEST        = 0x0211,/*  8 bit      Tx Arbiter Test Register */
         TXA_STAT        = 0x0212,/*  8 bit      Tx Arbiter Status Register */
+
+        RSS_KEY         = 0x0220, /* RSS Key setup */
+        RSS_CFG         = 0x0248, /* RSS Configuration */
 };
 
+enum {
+        HASH_TCP_IPV6_EX_CTRL   = 1<<5,
+        HASH_IPV6_EX_CTRL       = 1<<4,
+        HASH_TCP_IPV6_CTRL      = 1<<3,
+        HASH_IPV6_CTRL          = 1<<2,
+        HASH_TCP_IPV4_CTRL      = 1<<1,
+        HASH_IPV4_CTRL          = 1<<0,
+
+        HASH_ALL                = 0x3f,
+};
 
 enum {
         B6_EXT_REG      = 0x0300,/* External registers (GENESIS only) */
@@ -1775,10 +1797,13 @@ enum {
 /*      GM_SERIAL_MODE                  16 bit r/w      Serial Mode Register */
 enum {
         GM_SMOD_DATABL_MSK      = 0x1f<<11, /* Bit 15..11:      Data Blinder (r/o) */
-        GM_SMOD_LIMIT_4         = 1<<10, /* Bit 10:     4 consecutive Tx trials */
-        GM_SMOD_VLAN_ENA        = 1<<9, /* Bit  9:      Enable VLAN  (Max. Frame Len) */
-        GM_SMOD_JUMBO_ENA       = 1<<8, /* Bit  8:      Enable Jumbo (Max. Frame Len) */
-         GM_SMOD_IPG_MSK        = 0x1f  /* Bit 4..0:    Inter-Packet Gap (IPG) */
+        GM_SMOD_LIMIT_4         = 1<<10, /* 4 consecutive Tx trials */
+        GM_SMOD_VLAN_ENA        = 1<<9,  /* Enable VLAN  (Max. Frame Len) */
+        GM_SMOD_JUMBO_ENA       = 1<<8,  /* Enable Jumbo (Max. Frame Len) */
+
+        GM_NEW_FLOW_CTRL        = 1<<6,  /* Enable New Flow-Control */
+
+        GM_SMOD_IPG_MSK         = 0x1f   /* Bit 4..0:   Inter-Packet Gap (IPG) */
 };
 
 #define DATA_BLIND_VAL(x)       (((x)<<11) & GM_SMOD_DATABL_MSK)
@@ -2157,14 +2182,14 @@ struct tx_ring_info {
         unsigned long flags;
 #define TX_MAP_SINGLE   0x0001
 #define TX_MAP_PAGE     0x0002
-        DECLARE_PCI_UNMAP_ADDR(mapaddr);
-        DECLARE_PCI_UNMAP_LEN(maplen);
+        DEFINE_DMA_UNMAP_ADDR(mapaddr);
+        DEFINE_DMA_UNMAP_LEN(maplen);
 };
 
 struct rx_ring_info {
         struct sk_buff  *skb;
         dma_addr_t      data_addr;
-        DECLARE_PCI_UNMAP_LEN(data_size);
+        DEFINE_DMA_UNMAP_LEN(data_size);
         dma_addr_t      frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
 };
 
@@ -2249,6 +2274,7 @@ struct sky2_hw {
 #define SKY2_HW_NEW_LE          0x00000020      /* new LSOv2 format */
 #define SKY2_HW_AUTO_TX_SUM     0x00000040      /* new IP decode for Tx */
 #define SKY2_HW_ADV_POWER_CTL   0x00000080      /* additional PHY power regs */
+#define SKY2_HW_RSS_BROKEN      0x00000100
 
         u8                   chip_id;
         u8                   chip_rev;
@@ -2256,6 +2282,7 @@ struct sky2_hw {
         u8                   ports;
 
         struct sky2_status_le *st_le;
+        u32                  st_size;
         u32                  st_idx;
         dma_addr_t           st_dma;