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path: root/drivers/net/sky2.c
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-rw-r--r--drivers/net/sky2.c278
1 files changed, 141 insertions, 137 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 459c845d6648..16616f5440d0 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -10,8 +10,7 @@
10 * 10 *
11 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License.
14 * (at your option) any later version.
15 * 14 *
16 * This program is distributed in the hope that it will be useful, 15 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -50,7 +49,7 @@
50#include "sky2.h" 49#include "sky2.h"
51 50
52#define DRV_NAME "sky2" 51#define DRV_NAME "sky2"
53#define DRV_VERSION "1.9" 52#define DRV_VERSION "1.10"
54#define PFX DRV_NAME " " 53#define PFX DRV_NAME " "
55 54
56/* 55/*
@@ -96,9 +95,9 @@ static int disable_msi = 0;
96module_param(disable_msi, int, 0); 95module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98 97
99static int idle_timeout = 100; 98static int idle_timeout = 0;
100module_param(idle_timeout, int, 0); 99module_param(idle_timeout, int, 0);
101MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)"); 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
102 101
103static const struct pci_device_id sky2_id_table[] = { 102static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
@@ -284,6 +283,31 @@ static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
284 gma_write16(hw, port, GM_RX_CTRL, reg); 283 gma_write16(hw, port, GM_RX_CTRL, reg);
285} 284}
286 285
286/* flow control to advertise bits */
287static const u16 copper_fc_adv[] = {
288 [FC_NONE] = 0,
289 [FC_TX] = PHY_M_AN_ASP,
290 [FC_RX] = PHY_M_AN_PC,
291 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
292};
293
294/* flow control to advertise bits when using 1000BaseX */
295static const u16 fiber_fc_adv[] = {
296 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
297 [FC_TX] = PHY_M_P_ASYM_MD_X,
298 [FC_RX] = PHY_M_P_SYM_MD_X,
299 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
300};
301
302/* flow control to GMA disable bits */
303static const u16 gm_fc_disable[] = {
304 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
305 [FC_TX] = GM_GPCR_FC_RX_DIS,
306 [FC_RX] = GM_GPCR_FC_TX_DIS,
307 [FC_BOTH] = 0,
308};
309
310
287static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 311static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
288{ 312{
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 313 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
@@ -356,16 +380,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
357 } 381 }
358 382
359 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 383 ctrl = PHY_CT_RESET;
360 if (sky2->autoneg == AUTONEG_DISABLE)
361 ctrl &= ~PHY_CT_ANE;
362 else
363 ctrl |= PHY_CT_ANE;
364
365 ctrl |= PHY_CT_RESET;
366 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
367
368 ctrl = 0;
369 ct1000 = 0; 384 ct1000 = 0;
370 adv = PHY_AN_CSMA; 385 adv = PHY_AN_CSMA;
371 reg = 0; 386 reg = 0;
@@ -384,20 +399,16 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
384 adv |= PHY_M_AN_10_FD; 399 adv |= PHY_M_AN_10_FD;
385 if (sky2->advertising & ADVERTISED_10baseT_Half) 400 if (sky2->advertising & ADVERTISED_10baseT_Half)
386 adv |= PHY_M_AN_10_HD; 401 adv |= PHY_M_AN_10_HD;
402
403 adv |= copper_fc_adv[sky2->flow_mode];
387 } else { /* special defines for FIBER (88E1040S only) */ 404 } else { /* special defines for FIBER (88E1040S only) */
388 if (sky2->advertising & ADVERTISED_1000baseT_Full) 405 if (sky2->advertising & ADVERTISED_1000baseT_Full)
389 adv |= PHY_M_AN_1000X_AFD; 406 adv |= PHY_M_AN_1000X_AFD;
390 if (sky2->advertising & ADVERTISED_1000baseT_Half) 407 if (sky2->advertising & ADVERTISED_1000baseT_Half)
391 adv |= PHY_M_AN_1000X_AHD; 408 adv |= PHY_M_AN_1000X_AHD;
392 }
393 409
394 /* Set Flow-control capabilities */ 410 adv |= fiber_fc_adv[sky2->flow_mode];
395 if (sky2->tx_pause && sky2->rx_pause) 411 }
396 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
397 else if (sky2->rx_pause && !sky2->tx_pause)
398 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
399 else if (!sky2->rx_pause && sky2->tx_pause)
400 adv |= PHY_AN_PAUSE_ASYM; /* local */
401 412
402 /* Restart Auto-negotiation */ 413 /* Restart Auto-negotiation */
403 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 414 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
@@ -422,25 +433,17 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
422 if (sky2->duplex == DUPLEX_FULL) { 433 if (sky2->duplex == DUPLEX_FULL) {
423 reg |= GM_GPCR_DUP_FULL; 434 reg |= GM_GPCR_DUP_FULL;
424 ctrl |= PHY_CT_DUP_MD; 435 ctrl |= PHY_CT_DUP_MD;
425 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) { 436 } else if (sky2->speed < SPEED_1000)
426 /* Turn off flow control for 10/100mbps */ 437 sky2->flow_mode = FC_NONE;
427 sky2->rx_pause = 0;
428 sky2->tx_pause = 0;
429 }
430 438
431 if (!sky2->rx_pause)
432 reg |= GM_GPCR_FC_RX_DIS;
433 439
434 if (!sky2->tx_pause) 440 reg |= gm_fc_disable[sky2->flow_mode];
435 reg |= GM_GPCR_FC_TX_DIS;
436 441
437 /* Forward pause packets to GMAC? */ 442 /* Forward pause packets to GMAC? */
438 if (sky2->tx_pause || sky2->rx_pause) 443 if (sky2->flow_mode & FC_RX)
439 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 444 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
440 else 445 else
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
442
443 ctrl |= PHY_CT_RESET;
444 } 447 }
445 448
446 gma_write16(hw, port, GM_GP_CTRL, reg); 449 gma_write16(hw, port, GM_GP_CTRL, reg);
@@ -683,7 +686,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
683 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 686 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
684 687
685 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 688 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
686 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); 689 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
687 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); 690 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
688 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 691 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
689 /* set Tx GMAC FIFO Almost Empty Threshold */ 692 /* set Tx GMAC FIFO Almost Empty Threshold */
@@ -695,16 +698,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
695 698
696} 699}
697 700
698/* Assign Ram Buffer allocation. 701/* Assign Ram Buffer allocation in units of 64bit (8 bytes) */
699 * start and end are in units of 4k bytes 702static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
700 * ram registers are in units of 64bit words
701 */
702static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
703{ 703{
704 u32 start, end; 704 pr_debug(PFX "q %d %#x %#x\n", q, start, end);
705
706 start = startk * 4096/8;
707 end = (endk * 4096/8) - 1;
708 705
709 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 706 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
710 sky2_write32(hw, RB_ADDR(q, RB_START), start); 707 sky2_write32(hw, RB_ADDR(q, RB_START), start);
@@ -713,7 +710,7 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
713 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 710 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
714 711
715 if (q == Q_R1 || q == Q_R2) { 712 if (q == Q_R1 || q == Q_R2) {
716 u32 space = (endk - startk) * 4096/8; 713 u32 space = end - start + 1;
717 u32 tp = space - space/4; 714 u32 tp = space - space/4;
718 715
719 /* On receive queue's set the thresholds 716 /* On receive queue's set the thresholds
@@ -1195,19 +1192,16 @@ static int sky2_up(struct net_device *dev)
1195 1192
1196 sky2_mac_init(hw, port); 1193 sky2_mac_init(hw, port);
1197 1194
1198 /* Determine available ram buffer space (in 4K blocks). 1195 /* Determine available ram buffer space in qwords. */
1199 * Note: not sure about the FE setting below yet 1196 ramsize = sky2_read8(hw, B2_E_0) * 4096/8;
1200 */
1201 if (hw->chip_id == CHIP_ID_YUKON_FE)
1202 ramsize = 4;
1203 else
1204 ramsize = sky2_read8(hw, B2_E_0);
1205 1197
1206 /* Give transmitter one third (rounded up) */ 1198 if (ramsize > 6*1024/8)
1207 rxspace = ramsize - (ramsize + 2) / 3; 1199 rxspace = ramsize - (ramsize + 2) / 3;
1200 else
1201 rxspace = ramsize / 2;
1208 1202
1209 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1203 sky2_ramset(hw, rxqaddr[port], 0, rxspace-1);
1210 sky2_ramset(hw, txqaddr[port], rxspace, ramsize); 1204 sky2_ramset(hw, txqaddr[port], rxspace, ramsize-1);
1211 1205
1212 /* Make sure SyncQ is disabled */ 1206 /* Make sure SyncQ is disabled */
1213 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1207 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
@@ -1499,6 +1493,11 @@ static int sky2_down(struct net_device *dev)
1499 /* Stop more packets from being queued */ 1493 /* Stop more packets from being queued */
1500 netif_stop_queue(dev); 1494 netif_stop_queue(dev);
1501 1495
1496 /* Disable port IRQ */
1497 imask = sky2_read32(hw, B0_IMSK);
1498 imask &= ~portirq_msk[port];
1499 sky2_write32(hw, B0_IMSK, imask);
1500
1502 sky2_gmac_reset(hw, port); 1501 sky2_gmac_reset(hw, port);
1503 1502
1504 /* Stop transmitter */ 1503 /* Stop transmitter */
@@ -1549,11 +1548,6 @@ static int sky2_down(struct net_device *dev)
1549 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 1548 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1550 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 1549 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1551 1550
1552 /* Disable port IRQ */
1553 imask = sky2_read32(hw, B0_IMSK);
1554 imask &= ~portirq_msk[port];
1555 sky2_write32(hw, B0_IMSK, imask);
1556
1557 sky2_phy_power(hw, port, 0); 1551 sky2_phy_power(hw, port, 0);
1558 1552
1559 /* turn off LED's */ 1553 /* turn off LED's */
@@ -1605,6 +1599,12 @@ static void sky2_link_up(struct sky2_port *sky2)
1605 struct sky2_hw *hw = sky2->hw; 1599 struct sky2_hw *hw = sky2->hw;
1606 unsigned port = sky2->port; 1600 unsigned port = sky2->port;
1607 u16 reg; 1601 u16 reg;
1602 static const char *fc_name[] = {
1603 [FC_NONE] = "none",
1604 [FC_TX] = "tx",
1605 [FC_RX] = "rx",
1606 [FC_BOTH] = "both",
1607 };
1608 1608
1609 /* enable Rx/Tx */ 1609 /* enable Rx/Tx */
1610 reg = gma_read16(hw, port, GM_GP_CTRL); 1610 reg = gma_read16(hw, port, GM_GP_CTRL);
@@ -1648,8 +1648,7 @@ static void sky2_link_up(struct sky2_port *sky2)
1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", 1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1649 sky2->netdev->name, sky2->speed, 1649 sky2->netdev->name, sky2->speed,
1650 sky2->duplex == DUPLEX_FULL ? "full" : "half", 1650 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1651 (sky2->tx_pause && sky2->rx_pause) ? "both" : 1651 fc_name[sky2->flow_status]);
1652 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1653} 1652}
1654 1653
1655static void sky2_link_down(struct sky2_port *sky2) 1654static void sky2_link_down(struct sky2_port *sky2)
@@ -1664,7 +1663,7 @@ static void sky2_link_down(struct sky2_port *sky2)
1664 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 1663 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1665 gma_write16(hw, port, GM_GP_CTRL, reg); 1664 gma_write16(hw, port, GM_GP_CTRL, reg);
1666 1665
1667 if (sky2->rx_pause && !sky2->tx_pause) { 1666 if (sky2->flow_status == FC_RX) {
1668 /* restore Asymmetric Pause bit */ 1667 /* restore Asymmetric Pause bit */
1669 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, 1668 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1670 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) 1669 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
@@ -1683,6 +1682,14 @@ static void sky2_link_down(struct sky2_port *sky2)
1683 sky2_phy_init(hw, port); 1682 sky2_phy_init(hw, port);
1684} 1683}
1685 1684
1685static enum flow_control sky2_flow(int rx, int tx)
1686{
1687 if (rx)
1688 return tx ? FC_BOTH : FC_RX;
1689 else
1690 return tx ? FC_TX : FC_NONE;
1691}
1692
1686static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 1693static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1687{ 1694{
1688 struct sky2_hw *hw = sky2->hw; 1695 struct sky2_hw *hw = sky2->hw;
@@ -1703,39 +1710,20 @@ static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1703 } 1710 }
1704 1711
1705 sky2->speed = sky2_phy_speed(hw, aux); 1712 sky2->speed = sky2_phy_speed(hw, aux);
1706 if (sky2->speed == SPEED_1000) { 1713 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1707 u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
1708 u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
1709 if (lpa2 & PHY_B_1000S_MSF) {
1710 printk(KERN_ERR PFX "%s: master/slave fault",
1711 sky2->netdev->name);
1712 return -1;
1713 }
1714
1715 if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
1716 sky2->duplex = DUPLEX_FULL;
1717 else
1718 sky2->duplex = DUPLEX_HALF;
1719 } else {
1720 u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1721 if ((aux & adv) & PHY_AN_FULL)
1722 sky2->duplex = DUPLEX_FULL;
1723 else
1724 sky2->duplex = DUPLEX_HALF;
1725 }
1726 1714
1727 /* Pause bits are offset (9..8) */ 1715 /* Pause bits are offset (9..8) */
1728 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) 1716 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1729 aux >>= 6; 1717 aux >>= 6;
1730 1718
1731 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; 1719 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1732 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; 1720 aux & PHY_M_PS_TX_P_EN);
1733 1721
1734 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000 1722 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1735 && hw->chip_id != CHIP_ID_YUKON_EC_U) 1723 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1736 sky2->rx_pause = sky2->tx_pause = 0; 1724 sky2->flow_status = FC_NONE;
1737 1725
1738 if (sky2->rx_pause || sky2->tx_pause) 1726 if (aux & PHY_M_PS_RX_P_EN)
1739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 1727 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1740 else 1728 else
1741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 1729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
@@ -1750,13 +1738,13 @@ static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1750 struct sky2_port *sky2 = netdev_priv(dev); 1738 struct sky2_port *sky2 = netdev_priv(dev);
1751 u16 istatus, phystat; 1739 u16 istatus, phystat;
1752 1740
1741 if (!netif_running(dev))
1742 return;
1743
1753 spin_lock(&sky2->phy_lock); 1744 spin_lock(&sky2->phy_lock);
1754 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 1745 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1755 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 1746 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1756 1747
1757 if (!netif_running(dev))
1758 goto out;
1759
1760 if (netif_msg_intr(sky2)) 1748 if (netif_msg_intr(sky2))
1761 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", 1749 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1762 sky2->netdev->name, istatus, phystat); 1750 sky2->netdev->name, istatus, phystat);
@@ -1907,7 +1895,7 @@ static struct sk_buff *receive_copy(struct sky2_port *sky2,
1907 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 1895 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1908 length, PCI_DMA_FROMDEVICE); 1896 length, PCI_DMA_FROMDEVICE);
1909 re->skb->ip_summed = CHECKSUM_NONE; 1897 re->skb->ip_summed = CHECKSUM_NONE;
1910 __skb_put(skb, length); 1898 skb_put(skb, length);
1911 } 1899 }
1912 return skb; 1900 return skb;
1913} 1901}
@@ -1970,7 +1958,7 @@ static struct sk_buff *receive_new(struct sky2_port *sky2,
1970 if (skb_shinfo(skb)->nr_frags) 1958 if (skb_shinfo(skb)->nr_frags)
1971 skb_put_frags(skb, hdr_space, length); 1959 skb_put_frags(skb, hdr_space, length);
1972 else 1960 else
1973 skb_put(skb, hdr_space); 1961 skb_put(skb, length);
1974 return skb; 1962 return skb;
1975} 1963}
1976 1964
@@ -2016,6 +2004,10 @@ oversize:
2016 2004
2017error: 2005error:
2018 ++sky2->net_stats.rx_errors; 2006 ++sky2->net_stats.rx_errors;
2007 if (status & GMR_FS_RX_FF_OV) {
2008 sky2->net_stats.rx_fifo_errors++;
2009 goto resubmit;
2010 }
2019 2011
2020 if (netif_msg_rx_err(sky2) && net_ratelimit()) 2012 if (netif_msg_rx_err(sky2) && net_ratelimit())
2021 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", 2013 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
@@ -2027,8 +2019,6 @@ error:
2027 sky2->net_stats.rx_frame_errors++; 2019 sky2->net_stats.rx_frame_errors++;
2028 if (status & GMR_FS_CRC_ERR) 2020 if (status & GMR_FS_CRC_ERR)
2029 sky2->net_stats.rx_crc_errors++; 2021 sky2->net_stats.rx_crc_errors++;
2030 if (status & GMR_FS_RX_FF_OV)
2031 sky2->net_stats.rx_fifo_errors++;
2032 2022
2033 goto resubmit; 2023 goto resubmit;
2034} 2024}
@@ -2220,8 +2210,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2220 /* PCI-Express uncorrectable Error occurred */ 2210 /* PCI-Express uncorrectable Error occurred */
2221 u32 pex_err; 2211 u32 pex_err;
2222 2212
2223 pex_err = sky2_pci_read32(hw, 2213 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2224 hw->err_cap + PCI_ERR_UNCOR_STATUS);
2225 2214
2226 if (net_ratelimit()) 2215 if (net_ratelimit())
2227 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", 2216 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
@@ -2229,20 +2218,15 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2229 2218
2230 /* clear the interrupt */ 2219 /* clear the interrupt */
2231 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2220 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2232 sky2_pci_write32(hw, 2221 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2233 hw->err_cap + PCI_ERR_UNCOR_STATUS, 2222 0xffffffffUL);
2234 0xffffffffUL);
2235 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2223 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2236 2224
2237 2225 if (pex_err & PEX_FATAL_ERRORS) {
2238 /* In case of fatal error mask off to keep from getting stuck */
2239 if (pex_err & (PCI_ERR_UNC_POISON_TLP | PCI_ERR_UNC_FCP
2240 | PCI_ERR_UNC_DLP)) {
2241 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2226 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2242 hwmsk &= ~Y2_IS_PCI_EXP; 2227 hwmsk &= ~Y2_IS_PCI_EXP;
2243 sky2_write32(hw, B0_HWE_IMSK, hwmsk); 2228 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2244 } 2229 }
2245
2246 } 2230 }
2247 2231
2248 if (status & Y2_HWE_L1_MASK) 2232 if (status & Y2_HWE_L1_MASK)
@@ -2423,7 +2407,6 @@ static int sky2_reset(struct sky2_hw *hw)
2423 u16 status; 2407 u16 status;
2424 u8 t8; 2408 u8 t8;
2425 int i; 2409 int i;
2426 u32 msk;
2427 2410
2428 sky2_write8(hw, B0_CTST, CS_RST_CLR); 2411 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2429 2412
@@ -2464,13 +2447,9 @@ static int sky2_reset(struct sky2_hw *hw)
2464 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 2447 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2465 2448
2466 /* clear any PEX errors */ 2449 /* clear any PEX errors */
2467 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) { 2450 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2468 hw->err_cap = pci_find_ext_capability(hw->pdev, PCI_EXT_CAP_ID_ERR); 2451 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2469 if (hw->err_cap) 2452
2470 sky2_pci_write32(hw,
2471 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2472 0xffffffffUL);
2473 }
2474 2453
2475 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 2454 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2476 hw->ports = 1; 2455 hw->ports = 1;
@@ -2527,10 +2506,7 @@ static int sky2_reset(struct sky2_hw *hw)
2527 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2528 } 2507 }
2529 2508
2530 msk = Y2_HWE_ALL_MASK; 2509 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2531 if (!hw->err_cap)
2532 msk &= ~Y2_IS_PCI_EXP;
2533 sky2_write32(hw, B0_HWE_IMSK, msk);
2534 2510
2535 for (i = 0; i < hw->ports; i++) 2511 for (i = 0; i < hw->ports; i++)
2536 sky2_gmac_reset(hw, i); 2512 sky2_gmac_reset(hw, i);
@@ -2762,7 +2738,7 @@ static int sky2_nway_reset(struct net_device *dev)
2762{ 2738{
2763 struct sky2_port *sky2 = netdev_priv(dev); 2739 struct sky2_port *sky2 = netdev_priv(dev);
2764 2740
2765 if (sky2->autoneg != AUTONEG_ENABLE) 2741 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2766 return -EINVAL; 2742 return -EINVAL;
2767 2743
2768 sky2_phy_reinit(sky2); 2744 sky2_phy_reinit(sky2);
@@ -2864,6 +2840,14 @@ static int sky2_set_mac_address(struct net_device *dev, void *p)
2864 return 0; 2840 return 0;
2865} 2841}
2866 2842
2843static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2844{
2845 u32 bit;
2846
2847 bit = ether_crc(ETH_ALEN, addr) & 63;
2848 filter[bit >> 3] |= 1 << (bit & 7);
2849}
2850
2867static void sky2_set_multicast(struct net_device *dev) 2851static void sky2_set_multicast(struct net_device *dev)
2868{ 2852{
2869 struct sky2_port *sky2 = netdev_priv(dev); 2853 struct sky2_port *sky2 = netdev_priv(dev);
@@ -2872,7 +2856,10 @@ static void sky2_set_multicast(struct net_device *dev)
2872 struct dev_mc_list *list = dev->mc_list; 2856 struct dev_mc_list *list = dev->mc_list;
2873 u16 reg; 2857 u16 reg;
2874 u8 filter[8]; 2858 u8 filter[8];
2859 int rx_pause;
2860 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2875 2861
2862 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
2876 memset(filter, 0, sizeof(filter)); 2863 memset(filter, 0, sizeof(filter));
2877 2864
2878 reg = gma_read16(hw, port, GM_RX_CTRL); 2865 reg = gma_read16(hw, port, GM_RX_CTRL);
@@ -2880,18 +2867,19 @@ static void sky2_set_multicast(struct net_device *dev)
2880 2867
2881 if (dev->flags & IFF_PROMISC) /* promiscuous */ 2868 if (dev->flags & IFF_PROMISC) /* promiscuous */
2882 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2869 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2883 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ 2870 else if (dev->flags & IFF_ALLMULTI)
2884 memset(filter, 0xff, sizeof(filter)); 2871 memset(filter, 0xff, sizeof(filter));
2885 else if (dev->mc_count == 0) /* no multicast */ 2872 else if (dev->mc_count == 0 && !rx_pause)
2886 reg &= ~GM_RXCR_MCF_ENA; 2873 reg &= ~GM_RXCR_MCF_ENA;
2887 else { 2874 else {
2888 int i; 2875 int i;
2889 reg |= GM_RXCR_MCF_ENA; 2876 reg |= GM_RXCR_MCF_ENA;
2890 2877
2891 for (i = 0; list && i < dev->mc_count; i++, list = list->next) { 2878 if (rx_pause)
2892 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; 2879 sky2_add_filter(filter, pause_mc_addr);
2893 filter[bit / 8] |= 1 << (bit % 8); 2880
2894 } 2881 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2882 sky2_add_filter(filter, list->dmi_addr);
2895 } 2883 }
2896 2884
2897 gma_write16(hw, port, GM_MC_ADDR_H1, 2885 gma_write16(hw, port, GM_MC_ADDR_H1,
@@ -3004,8 +2992,20 @@ static void sky2_get_pauseparam(struct net_device *dev,
3004{ 2992{
3005 struct sky2_port *sky2 = netdev_priv(dev); 2993 struct sky2_port *sky2 = netdev_priv(dev);
3006 2994
3007 ecmd->tx_pause = sky2->tx_pause; 2995 switch (sky2->flow_mode) {
3008 ecmd->rx_pause = sky2->rx_pause; 2996 case FC_NONE:
2997 ecmd->tx_pause = ecmd->rx_pause = 0;
2998 break;
2999 case FC_TX:
3000 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3001 break;
3002 case FC_RX:
3003 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3004 break;
3005 case FC_BOTH:
3006 ecmd->tx_pause = ecmd->rx_pause = 1;
3007 }
3008
3009 ecmd->autoneg = sky2->autoneg; 3009 ecmd->autoneg = sky2->autoneg;
3010} 3010}
3011 3011
@@ -3015,10 +3015,10 @@ static int sky2_set_pauseparam(struct net_device *dev,
3015 struct sky2_port *sky2 = netdev_priv(dev); 3015 struct sky2_port *sky2 = netdev_priv(dev);
3016 3016
3017 sky2->autoneg = ecmd->autoneg; 3017 sky2->autoneg = ecmd->autoneg;
3018 sky2->tx_pause = ecmd->tx_pause != 0; 3018 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3019 sky2->rx_pause = ecmd->rx_pause != 0;
3020 3019
3021 sky2_phy_reinit(sky2); 3020 if (netif_running(dev))
3021 sky2_phy_reinit(sky2);
3022 3022
3023 return 0; 3023 return 0;
3024} 3024}
@@ -3238,7 +3238,11 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3238 dev->poll = sky2_poll; 3238 dev->poll = sky2_poll;
3239 dev->weight = NAPI_WEIGHT; 3239 dev->weight = NAPI_WEIGHT;
3240#ifdef CONFIG_NET_POLL_CONTROLLER 3240#ifdef CONFIG_NET_POLL_CONTROLLER
3241 dev->poll_controller = sky2_netpoll; 3241 /* Network console (only works on port 0)
3242 * because netpoll makes assumptions about NAPI
3243 */
3244 if (port == 0)
3245 dev->poll_controller = sky2_netpoll;
3242#endif 3246#endif
3243 3247
3244 sky2 = netdev_priv(dev); 3248 sky2 = netdev_priv(dev);
@@ -3248,8 +3252,8 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3248 3252
3249 /* Auto speed and flow control */ 3253 /* Auto speed and flow control */
3250 sky2->autoneg = AUTONEG_ENABLE; 3254 sky2->autoneg = AUTONEG_ENABLE;
3251 sky2->tx_pause = 1; 3255 sky2->flow_mode = FC_BOTH;
3252 sky2->rx_pause = 1; 3256
3253 sky2->duplex = -1; 3257 sky2->duplex = -1;
3254 sky2->speed = -1; 3258 sky2->speed = -1;
3255 sky2->advertising = sky2_supported_modes(hw); 3259 sky2->advertising = sky2_supported_modes(hw);
@@ -3340,9 +3344,8 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3340 3344
3341 if (!hw->msi_detected) { 3345 if (!hw->msi_detected) {
3342 /* MSI test failed, go back to INTx mode */ 3346 /* MSI test failed, go back to INTx mode */
3343 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " 3347 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3344 "switching to INTx mode. Please report this failure to " 3348 "switching to INTx mode.\n",
3345 "the PCI maintainer and include system chipset information.\n",
3346 pci_name(pdev)); 3349 pci_name(pdev));
3347 3350
3348 err = -EOPNOTSUPP; 3351 err = -EOPNOTSUPP;
@@ -3350,6 +3353,7 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw)
3350 } 3353 }
3351 3354
3352 sky2_write32(hw, B0_IMSK, 0); 3355 sky2_write32(hw, B0_IMSK, 0);
3356 sky2_read32(hw, B0_IMSK);
3353 3357
3354 free_irq(pdev->irq, hw); 3358 free_irq(pdev->irq, hw);
3355 3359