diff options
Diffstat (limited to 'drivers/net/sfc/nic.c')
-rw-r--r-- | drivers/net/sfc/nic.c | 114 |
1 files changed, 62 insertions, 52 deletions
diff --git a/drivers/net/sfc/nic.c b/drivers/net/sfc/nic.c index b06f8e348307..5d3aaec58556 100644 --- a/drivers/net/sfc/nic.c +++ b/drivers/net/sfc/nic.c | |||
@@ -418,7 +418,7 @@ void efx_nic_init_tx(struct efx_tx_queue *tx_queue) | |||
418 | FRF_BZ_TX_NON_IP_DROP_DIS, 1); | 418 | FRF_BZ_TX_NON_IP_DROP_DIS, 1); |
419 | 419 | ||
420 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | 420 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
421 | int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM; | 421 | int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; |
422 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum); | 422 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum); |
423 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS, | 423 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS, |
424 | !csum); | 424 | !csum); |
@@ -431,10 +431,10 @@ void efx_nic_init_tx(struct efx_tx_queue *tx_queue) | |||
431 | efx_oword_t reg; | 431 | efx_oword_t reg; |
432 | 432 | ||
433 | /* Only 128 bits in this register */ | 433 | /* Only 128 bits in this register */ |
434 | BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); | 434 | BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128); |
435 | 435 | ||
436 | efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); | 436 | efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); |
437 | if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) | 437 | if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) |
438 | clear_bit_le(tx_queue->queue, (void *)®); | 438 | clear_bit_le(tx_queue->queue, (void *)®); |
439 | else | 439 | else |
440 | set_bit_le(tx_queue->queue, (void *)®); | 440 | set_bit_le(tx_queue->queue, (void *)®); |
@@ -654,22 +654,23 @@ void efx_generate_event(struct efx_channel *channel, efx_qword_t *event) | |||
654 | * The NIC batches TX completion events; the message we receive is of | 654 | * The NIC batches TX completion events; the message we receive is of |
655 | * the form "complete all TX events up to this index". | 655 | * the form "complete all TX events up to this index". |
656 | */ | 656 | */ |
657 | static void | 657 | static int |
658 | efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) | 658 | efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) |
659 | { | 659 | { |
660 | unsigned int tx_ev_desc_ptr; | 660 | unsigned int tx_ev_desc_ptr; |
661 | unsigned int tx_ev_q_label; | 661 | unsigned int tx_ev_q_label; |
662 | struct efx_tx_queue *tx_queue; | 662 | struct efx_tx_queue *tx_queue; |
663 | struct efx_nic *efx = channel->efx; | 663 | struct efx_nic *efx = channel->efx; |
664 | int tx_packets = 0; | ||
664 | 665 | ||
665 | if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { | 666 | if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { |
666 | /* Transmit completion */ | 667 | /* Transmit completion */ |
667 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); | 668 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); |
668 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); | 669 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); |
669 | tx_queue = &efx->tx_queue[tx_ev_q_label]; | 670 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
670 | channel->irq_mod_score += | 671 | tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) & |
671 | (tx_ev_desc_ptr - tx_queue->read_count) & | 672 | EFX_TXQ_MASK); |
672 | EFX_TXQ_MASK; | 673 | channel->irq_mod_score += tx_packets; |
673 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); | 674 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); |
674 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { | 675 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { |
675 | /* Rewrite the FIFO write pointer */ | 676 | /* Rewrite the FIFO write pointer */ |
@@ -689,6 +690,8 @@ efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) | |||
689 | EFX_QWORD_FMT"\n", channel->channel, | 690 | EFX_QWORD_FMT"\n", channel->channel, |
690 | EFX_QWORD_VAL(*event)); | 691 | EFX_QWORD_VAL(*event)); |
691 | } | 692 | } |
693 | |||
694 | return tx_packets; | ||
692 | } | 695 | } |
693 | 696 | ||
694 | /* Detect errors included in the rx_evt_pkt_ok bit. */ | 697 | /* Detect errors included in the rx_evt_pkt_ok bit. */ |
@@ -947,16 +950,17 @@ efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) | |||
947 | } | 950 | } |
948 | } | 951 | } |
949 | 952 | ||
950 | int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota) | 953 | int efx_nic_process_eventq(struct efx_channel *channel, int budget) |
951 | { | 954 | { |
952 | unsigned int read_ptr; | 955 | unsigned int read_ptr; |
953 | efx_qword_t event, *p_event; | 956 | efx_qword_t event, *p_event; |
954 | int ev_code; | 957 | int ev_code; |
955 | int rx_packets = 0; | 958 | int tx_packets = 0; |
959 | int spent = 0; | ||
956 | 960 | ||
957 | read_ptr = channel->eventq_read_ptr; | 961 | read_ptr = channel->eventq_read_ptr; |
958 | 962 | ||
959 | do { | 963 | for (;;) { |
960 | p_event = efx_event(channel, read_ptr); | 964 | p_event = efx_event(channel, read_ptr); |
961 | event = *p_event; | 965 | event = *p_event; |
962 | 966 | ||
@@ -970,15 +974,23 @@ int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota) | |||
970 | /* Clear this event by marking it all ones */ | 974 | /* Clear this event by marking it all ones */ |
971 | EFX_SET_QWORD(*p_event); | 975 | EFX_SET_QWORD(*p_event); |
972 | 976 | ||
977 | /* Increment read pointer */ | ||
978 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; | ||
979 | |||
973 | ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); | 980 | ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); |
974 | 981 | ||
975 | switch (ev_code) { | 982 | switch (ev_code) { |
976 | case FSE_AZ_EV_CODE_RX_EV: | 983 | case FSE_AZ_EV_CODE_RX_EV: |
977 | efx_handle_rx_event(channel, &event); | 984 | efx_handle_rx_event(channel, &event); |
978 | ++rx_packets; | 985 | if (++spent == budget) |
986 | goto out; | ||
979 | break; | 987 | break; |
980 | case FSE_AZ_EV_CODE_TX_EV: | 988 | case FSE_AZ_EV_CODE_TX_EV: |
981 | efx_handle_tx_event(channel, &event); | 989 | tx_packets += efx_handle_tx_event(channel, &event); |
990 | if (tx_packets >= EFX_TXQ_SIZE) { | ||
991 | spent = budget; | ||
992 | goto out; | ||
993 | } | ||
982 | break; | 994 | break; |
983 | case FSE_AZ_EV_CODE_DRV_GEN_EV: | 995 | case FSE_AZ_EV_CODE_DRV_GEN_EV: |
984 | channel->eventq_magic = EFX_QWORD_FIELD( | 996 | channel->eventq_magic = EFX_QWORD_FIELD( |
@@ -1001,14 +1013,11 @@ int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota) | |||
1001 | " (data " EFX_QWORD_FMT ")\n", channel->channel, | 1013 | " (data " EFX_QWORD_FMT ")\n", channel->channel, |
1002 | ev_code, EFX_QWORD_VAL(event)); | 1014 | ev_code, EFX_QWORD_VAL(event)); |
1003 | } | 1015 | } |
1016 | } | ||
1004 | 1017 | ||
1005 | /* Increment read pointer */ | 1018 | out: |
1006 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; | ||
1007 | |||
1008 | } while (rx_packets < rx_quota); | ||
1009 | |||
1010 | channel->eventq_read_ptr = read_ptr; | 1019 | channel->eventq_read_ptr = read_ptr; |
1011 | return rx_packets; | 1020 | return spent; |
1012 | } | 1021 | } |
1013 | 1022 | ||
1014 | 1023 | ||
@@ -1123,7 +1132,7 @@ static void efx_poll_flush_events(struct efx_nic *efx) | |||
1123 | ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) { | 1132 | ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) { |
1124 | ev_queue = EFX_QWORD_FIELD(*event, | 1133 | ev_queue = EFX_QWORD_FIELD(*event, |
1125 | FSF_AZ_DRIVER_EV_SUBDATA); | 1134 | FSF_AZ_DRIVER_EV_SUBDATA); |
1126 | if (ev_queue < EFX_TX_QUEUE_COUNT) { | 1135 | if (ev_queue < EFX_TXQ_TYPES * efx->n_tx_channels) { |
1127 | tx_queue = efx->tx_queue + ev_queue; | 1136 | tx_queue = efx->tx_queue + ev_queue; |
1128 | tx_queue->flushed = FLUSH_DONE; | 1137 | tx_queue->flushed = FLUSH_DONE; |
1129 | } | 1138 | } |
@@ -1133,7 +1142,7 @@ static void efx_poll_flush_events(struct efx_nic *efx) | |||
1133 | *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); | 1142 | *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); |
1134 | ev_failed = EFX_QWORD_FIELD( | 1143 | ev_failed = EFX_QWORD_FIELD( |
1135 | *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); | 1144 | *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); |
1136 | if (ev_queue < efx->n_rx_queues) { | 1145 | if (ev_queue < efx->n_rx_channels) { |
1137 | rx_queue = efx->rx_queue + ev_queue; | 1146 | rx_queue = efx->rx_queue + ev_queue; |
1138 | rx_queue->flushed = | 1147 | rx_queue->flushed = |
1139 | ev_failed ? FLUSH_FAILED : FLUSH_DONE; | 1148 | ev_failed ? FLUSH_FAILED : FLUSH_DONE; |
@@ -1229,15 +1238,9 @@ static inline void efx_nic_interrupts(struct efx_nic *efx, | |||
1229 | bool enabled, bool force) | 1238 | bool enabled, bool force) |
1230 | { | 1239 | { |
1231 | efx_oword_t int_en_reg_ker; | 1240 | efx_oword_t int_en_reg_ker; |
1232 | unsigned int level = 0; | ||
1233 | |||
1234 | if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx)) | ||
1235 | /* Set the level always even if we're generating a test | ||
1236 | * interrupt, because our legacy interrupt handler is safe */ | ||
1237 | level = 0x1f; | ||
1238 | 1241 | ||
1239 | EFX_POPULATE_OWORD_3(int_en_reg_ker, | 1242 | EFX_POPULATE_OWORD_3(int_en_reg_ker, |
1240 | FRF_AZ_KER_INT_LEVE_SEL, level, | 1243 | FRF_AZ_KER_INT_LEVE_SEL, efx->fatal_irq_level, |
1241 | FRF_AZ_KER_INT_KER, force, | 1244 | FRF_AZ_KER_INT_KER, force, |
1242 | FRF_AZ_DRV_INT_EN_KER, enabled); | 1245 | FRF_AZ_DRV_INT_EN_KER, enabled); |
1243 | efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); | 1246 | efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); |
@@ -1291,11 +1294,10 @@ irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx) | |||
1291 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), | 1294 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), |
1292 | EFX_OWORD_VAL(fatal_intr), | 1295 | EFX_OWORD_VAL(fatal_intr), |
1293 | error ? "disabling bus mastering" : "no recognised error"); | 1296 | error ? "disabling bus mastering" : "no recognised error"); |
1294 | if (error == 0) | ||
1295 | goto out; | ||
1296 | 1297 | ||
1297 | /* If this is a memory parity error dump which blocks are offending */ | 1298 | /* If this is a memory parity error dump which blocks are offending */ |
1298 | mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER); | 1299 | mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) || |
1300 | EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER)); | ||
1299 | if (mem_perr) { | 1301 | if (mem_perr) { |
1300 | efx_oword_t reg; | 1302 | efx_oword_t reg; |
1301 | efx_reado(efx, ®, FR_AZ_MEM_STAT); | 1303 | efx_reado(efx, ®, FR_AZ_MEM_STAT); |
@@ -1324,7 +1326,7 @@ irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx) | |||
1324 | "NIC will be disabled\n"); | 1326 | "NIC will be disabled\n"); |
1325 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | 1327 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); |
1326 | } | 1328 | } |
1327 | out: | 1329 | |
1328 | return IRQ_HANDLED; | 1330 | return IRQ_HANDLED; |
1329 | } | 1331 | } |
1330 | 1332 | ||
@@ -1346,9 +1348,11 @@ static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id) | |||
1346 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); | 1348 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); |
1347 | 1349 | ||
1348 | /* Check to see if we have a serious error condition */ | 1350 | /* Check to see if we have a serious error condition */ |
1349 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); | 1351 | if (queues & (1U << efx->fatal_irq_level)) { |
1350 | if (unlikely(syserr)) | 1352 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
1351 | return efx_nic_fatal_interrupt(efx); | 1353 | if (unlikely(syserr)) |
1354 | return efx_nic_fatal_interrupt(efx); | ||
1355 | } | ||
1352 | 1356 | ||
1353 | if (queues != 0) { | 1357 | if (queues != 0) { |
1354 | if (EFX_WORKAROUND_15783(efx)) | 1358 | if (EFX_WORKAROUND_15783(efx)) |
@@ -1362,33 +1366,28 @@ static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id) | |||
1362 | } | 1366 | } |
1363 | result = IRQ_HANDLED; | 1367 | result = IRQ_HANDLED; |
1364 | 1368 | ||
1365 | } else if (EFX_WORKAROUND_15783(efx) && | 1369 | } else if (EFX_WORKAROUND_15783(efx)) { |
1366 | efx->irq_zero_count++ == 0) { | ||
1367 | efx_qword_t *event; | 1370 | efx_qword_t *event; |
1368 | 1371 | ||
1369 | /* Ensure we rearm all event queues */ | 1372 | /* We can't return IRQ_HANDLED more than once on seeing ISR=0 |
1373 | * because this might be a shared interrupt. */ | ||
1374 | if (efx->irq_zero_count++ == 0) | ||
1375 | result = IRQ_HANDLED; | ||
1376 | |||
1377 | /* Ensure we schedule or rearm all event queues */ | ||
1370 | efx_for_each_channel(channel, efx) { | 1378 | efx_for_each_channel(channel, efx) { |
1371 | event = efx_event(channel, channel->eventq_read_ptr); | 1379 | event = efx_event(channel, channel->eventq_read_ptr); |
1372 | if (efx_event_present(event)) | 1380 | if (efx_event_present(event)) |
1373 | efx_schedule_channel(channel); | 1381 | efx_schedule_channel(channel); |
1382 | else | ||
1383 | efx_nic_eventq_read_ack(channel); | ||
1374 | } | 1384 | } |
1375 | |||
1376 | result = IRQ_HANDLED; | ||
1377 | } | 1385 | } |
1378 | 1386 | ||
1379 | if (result == IRQ_HANDLED) { | 1387 | if (result == IRQ_HANDLED) { |
1380 | efx->last_irq_cpu = raw_smp_processor_id(); | 1388 | efx->last_irq_cpu = raw_smp_processor_id(); |
1381 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | 1389 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", |
1382 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | 1390 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); |
1383 | } else if (EFX_WORKAROUND_15783(efx)) { | ||
1384 | /* We can't return IRQ_HANDLED more than once on seeing ISR0=0 | ||
1385 | * because this might be a shared interrupt, but we do need to | ||
1386 | * check the channel every time and preemptively rearm it if | ||
1387 | * it's idle. */ | ||
1388 | efx_for_each_channel(channel, efx) { | ||
1389 | if (!channel->work_pending) | ||
1390 | efx_nic_eventq_read_ack(channel); | ||
1391 | } | ||
1392 | } | 1391 | } |
1393 | 1392 | ||
1394 | return result; | 1393 | return result; |
@@ -1413,9 +1412,11 @@ static irqreturn_t efx_msi_interrupt(int irq, void *dev_id) | |||
1413 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | 1412 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); |
1414 | 1413 | ||
1415 | /* Check to see if we have a serious error condition */ | 1414 | /* Check to see if we have a serious error condition */ |
1416 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); | 1415 | if (channel->channel == efx->fatal_irq_level) { |
1417 | if (unlikely(syserr)) | 1416 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
1418 | return efx_nic_fatal_interrupt(efx); | 1417 | if (unlikely(syserr)) |
1418 | return efx_nic_fatal_interrupt(efx); | ||
1419 | } | ||
1419 | 1420 | ||
1420 | /* Schedule processing of the channel */ | 1421 | /* Schedule processing of the channel */ |
1421 | efx_schedule_channel(channel); | 1422 | efx_schedule_channel(channel); |
@@ -1440,7 +1441,7 @@ static void efx_setup_rss_indir_table(struct efx_nic *efx) | |||
1440 | offset < FR_BZ_RX_INDIRECTION_TBL + 0x800; | 1441 | offset < FR_BZ_RX_INDIRECTION_TBL + 0x800; |
1441 | offset += 0x10) { | 1442 | offset += 0x10) { |
1442 | EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, | 1443 | EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, |
1443 | i % efx->n_rx_queues); | 1444 | i % efx->n_rx_channels); |
1444 | efx_writed(efx, &dword, offset); | 1445 | efx_writed(efx, &dword, offset); |
1445 | i++; | 1446 | i++; |
1446 | } | 1447 | } |
@@ -1553,6 +1554,13 @@ void efx_nic_init_common(struct efx_nic *efx) | |||
1553 | FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); | 1554 | FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); |
1554 | efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER); | 1555 | efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER); |
1555 | 1556 | ||
1557 | if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx)) | ||
1558 | /* Use an interrupt level unused by event queues */ | ||
1559 | efx->fatal_irq_level = 0x1f; | ||
1560 | else | ||
1561 | /* Use a valid MSI-X vector */ | ||
1562 | efx->fatal_irq_level = 0; | ||
1563 | |||
1556 | /* Enable all the genuinely fatal interrupts. (They are still | 1564 | /* Enable all the genuinely fatal interrupts. (They are still |
1557 | * masked by the overall interrupt mask, controlled by | 1565 | * masked by the overall interrupt mask, controlled by |
1558 | * falcon_interrupts()). | 1566 | * falcon_interrupts()). |
@@ -1563,6 +1571,8 @@ void efx_nic_init_common(struct efx_nic *efx) | |||
1563 | FRF_AZ_ILL_ADR_INT_KER_EN, 1, | 1571 | FRF_AZ_ILL_ADR_INT_KER_EN, 1, |
1564 | FRF_AZ_RBUF_OWN_INT_KER_EN, 1, | 1572 | FRF_AZ_RBUF_OWN_INT_KER_EN, 1, |
1565 | FRF_AZ_TBUF_OWN_INT_KER_EN, 1); | 1573 | FRF_AZ_TBUF_OWN_INT_KER_EN, 1); |
1574 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) | ||
1575 | EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1); | ||
1566 | EFX_INVERT_OWORD(temp); | 1576 | EFX_INVERT_OWORD(temp); |
1567 | efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); | 1577 | efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); |
1568 | 1578 | ||