diff options
Diffstat (limited to 'drivers/net/sfc/mdio_10g.h')
-rw-r--r-- | drivers/net/sfc/mdio_10g.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/sfc/mdio_10g.h b/drivers/net/sfc/mdio_10g.h index 80c63dde8864..409118228b1d 100644 --- a/drivers/net/sfc/mdio_10g.h +++ b/drivers/net/sfc/mdio_10g.h | |||
@@ -33,6 +33,8 @@ | |||
33 | #define MDIO_MMD_TC (6) | 33 | #define MDIO_MMD_TC (6) |
34 | /* Auto negotiation */ | 34 | /* Auto negotiation */ |
35 | #define MDIO_MMD_AN (7) | 35 | #define MDIO_MMD_AN (7) |
36 | /* Clause 22 extension */ | ||
37 | #define MDIO_MMD_C22EXT 29 | ||
36 | 38 | ||
37 | /* Generic register locations */ | 39 | /* Generic register locations */ |
38 | #define MDIO_MMDREG_CTRL1 (0) | 40 | #define MDIO_MMDREG_CTRL1 (0) |
@@ -82,6 +84,7 @@ | |||
82 | #define MDIO_MMDREG_DEVS_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS) | 84 | #define MDIO_MMDREG_DEVS_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS) |
83 | #define MDIO_MMDREG_DEVS_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD) | 85 | #define MDIO_MMDREG_DEVS_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD) |
84 | #define MDIO_MMDREG_DEVS_AN DEV_PRESENT_BIT(MDIO_MMD_AN) | 86 | #define MDIO_MMDREG_DEVS_AN DEV_PRESENT_BIT(MDIO_MMD_AN) |
87 | #define MDIO_MMDREG_DEVS_C22EXT DEV_PRESENT_BIT(MDIO_MMD_C22EXT) | ||
85 | 88 | ||
86 | /* Bits in MMDREG_SPEED */ | 89 | /* Bits in MMDREG_SPEED */ |
87 | #define MDIO_MMDREG_SPEED_10G_LBN 0 | 90 | #define MDIO_MMDREG_SPEED_10G_LBN 0 |
@@ -125,6 +128,11 @@ | |||
125 | #define MDIO_PMAPMD_CTRL2_10_BT (0xf) | 128 | #define MDIO_PMAPMD_CTRL2_10_BT (0xf) |
126 | #define MDIO_PMAPMD_CTRL2_TYPE_MASK (0xf) | 129 | #define MDIO_PMAPMD_CTRL2_TYPE_MASK (0xf) |
127 | 130 | ||
131 | /* PMA 10GBT registers */ | ||
132 | #define MDIO_PMAPMD_10GBT_TXPWR (131) | ||
133 | #define MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN (0) | ||
134 | #define MDIO_PMAPMD_10GBT_TXPWR_SHORT_WIDTH (1) | ||
135 | |||
128 | /* PHY XGXS lane state */ | 136 | /* PHY XGXS lane state */ |
129 | #define MDIO_PHYXS_LANE_STATE (0x18) | 137 | #define MDIO_PHYXS_LANE_STATE (0x18) |
130 | #define MDIO_PHYXS_LANE_ALIGNED_LBN (12) | 138 | #define MDIO_PHYXS_LANE_ALIGNED_LBN (12) |