diff options
Diffstat (limited to 'drivers/net/qlcnic/qlcnic_hdr.h')
-rw-r--r-- | drivers/net/qlcnic/qlcnic_hdr.h | 84 |
1 files changed, 79 insertions, 5 deletions
diff --git a/drivers/net/qlcnic/qlcnic_hdr.h b/drivers/net/qlcnic/qlcnic_hdr.h index ad9d167723c4..7b81cab27002 100644 --- a/drivers/net/qlcnic/qlcnic_hdr.h +++ b/drivers/net/qlcnic/qlcnic_hdr.h | |||
@@ -208,6 +208,39 @@ enum { | |||
208 | QLCNIC_HW_PX_MAP_CRB_PGR0 | 208 | QLCNIC_HW_PX_MAP_CRB_PGR0 |
209 | }; | 209 | }; |
210 | 210 | ||
211 | #define BIT_0 0x1 | ||
212 | #define BIT_1 0x2 | ||
213 | #define BIT_2 0x4 | ||
214 | #define BIT_3 0x8 | ||
215 | #define BIT_4 0x10 | ||
216 | #define BIT_5 0x20 | ||
217 | #define BIT_6 0x40 | ||
218 | #define BIT_7 0x80 | ||
219 | #define BIT_8 0x100 | ||
220 | #define BIT_9 0x200 | ||
221 | #define BIT_10 0x400 | ||
222 | #define BIT_11 0x800 | ||
223 | #define BIT_12 0x1000 | ||
224 | #define BIT_13 0x2000 | ||
225 | #define BIT_14 0x4000 | ||
226 | #define BIT_15 0x8000 | ||
227 | #define BIT_16 0x10000 | ||
228 | #define BIT_17 0x20000 | ||
229 | #define BIT_18 0x40000 | ||
230 | #define BIT_19 0x80000 | ||
231 | #define BIT_20 0x100000 | ||
232 | #define BIT_21 0x200000 | ||
233 | #define BIT_22 0x400000 | ||
234 | #define BIT_23 0x800000 | ||
235 | #define BIT_24 0x1000000 | ||
236 | #define BIT_25 0x2000000 | ||
237 | #define BIT_26 0x4000000 | ||
238 | #define BIT_27 0x8000000 | ||
239 | #define BIT_28 0x10000000 | ||
240 | #define BIT_29 0x20000000 | ||
241 | #define BIT_30 0x40000000 | ||
242 | #define BIT_31 0x80000000 | ||
243 | |||
211 | /* This field defines CRB adr [31:20] of the agents */ | 244 | /* This field defines CRB adr [31:20] of the agents */ |
212 | 245 | ||
213 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \ | 246 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \ |
@@ -668,10 +701,11 @@ enum { | |||
668 | #define QLCNIC_CRB_DEV_REF_COUNT (QLCNIC_CAM_RAM(0x138)) | 701 | #define QLCNIC_CRB_DEV_REF_COUNT (QLCNIC_CAM_RAM(0x138)) |
669 | #define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140)) | 702 | #define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140)) |
670 | 703 | ||
671 | #define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144)) | 704 | #define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144)) |
672 | #define QLCNIC_CRB_DRV_SCRATCH (QLCNIC_CAM_RAM(0x148)) | 705 | #define QLCNIC_CRB_DRV_SCRATCH (QLCNIC_CAM_RAM(0x148)) |
673 | #define QLCNIC_CRB_DEV_PARTITION_INFO (QLCNIC_CAM_RAM(0x14c)) | 706 | #define QLCNIC_CRB_DEV_PARTITION_INFO (QLCNIC_CAM_RAM(0x14c)) |
674 | #define QLCNIC_CRB_DRV_IDC_VER (QLCNIC_CAM_RAM(0x174)) | 707 | #define QLCNIC_CRB_DRV_IDC_VER (QLCNIC_CAM_RAM(0x174)) |
708 | #define QLCNIC_CRB_DEV_NPAR_STATE (QLCNIC_CAM_RAM(0x19c)) | ||
675 | #define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c) | 709 | #define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c) |
676 | #define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860) | 710 | #define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860) |
677 | 711 | ||
@@ -684,15 +718,26 @@ enum { | |||
684 | #define QLCNIC_DEV_FAILED 0x6 | 718 | #define QLCNIC_DEV_FAILED 0x6 |
685 | #define QLCNIC_DEV_QUISCENT 0x7 | 719 | #define QLCNIC_DEV_QUISCENT 0x7 |
686 | 720 | ||
721 | #define QLCNIC_DEV_NPAR_NOT_RDY 0 | ||
722 | #define QLCNIC_DEV_NPAR_RDY 1 | ||
723 | |||
724 | #define QLC_DEV_CHECK_ACTIVE(VAL, FN) ((VAL) &= (1 << (FN * 4))) | ||
687 | #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) | 725 | #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) |
688 | #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) | 726 | #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) |
689 | #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) | 727 | #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) |
690 | #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) | 728 | #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) |
691 | #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) | 729 | #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) |
692 | 730 | ||
731 | #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) | ||
732 | #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) | ||
733 | |||
734 | #define QLCNIC_TYPE_NIC 1 | ||
735 | #define QLCNIC_TYPE_FCOE 2 | ||
736 | #define QLCNIC_TYPE_ISCSI 3 | ||
737 | |||
693 | #define QLCNIC_RCODE_DRIVER_INFO 0x20000000 | 738 | #define QLCNIC_RCODE_DRIVER_INFO 0x20000000 |
694 | #define QLCNIC_RCODE_DRIVER_CAN_RELOAD 0x40000000 | 739 | #define QLCNIC_RCODE_DRIVER_CAN_RELOAD BIT_30 |
695 | #define QLCNIC_RCODE_FATAL_ERROR 0x80000000 | 740 | #define QLCNIC_RCODE_FATAL_ERROR BIT_31 |
696 | #define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff) | 741 | #define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff) |
697 | #define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0xfffff) | 742 | #define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0xfffff) |
698 | 743 | ||
@@ -721,6 +766,35 @@ struct qlcnic_legacy_intr_set { | |||
721 | u32 pci_int_reg; | 766 | u32 pci_int_reg; |
722 | }; | 767 | }; |
723 | 768 | ||
769 | #define QLCNIC_FW_API 0x1b216c | ||
770 | #define QLCNIC_DRV_OP_MODE 0x1b2170 | ||
771 | #define QLCNIC_MSIX_BASE 0x132110 | ||
772 | #define QLCNIC_MAX_PCI_FUNC 8 | ||
773 | |||
774 | /* PCI function operational mode */ | ||
775 | enum { | ||
776 | QLCNIC_MGMT_FUNC = 0, | ||
777 | QLCNIC_PRIV_FUNC = 1, | ||
778 | QLCNIC_NON_PRIV_FUNC = 2 | ||
779 | }; | ||
780 | |||
781 | /* FW HAL api version */ | ||
782 | enum { | ||
783 | QLCNIC_FW_BASE = 1, | ||
784 | QLCNIC_FW_NPAR = 2 | ||
785 | }; | ||
786 | |||
787 | #define QLC_DEV_DRV_DEFAULT 0x11111111 | ||
788 | |||
789 | #define LSB(x) ((uint8_t)(x)) | ||
790 | #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) | ||
791 | |||
792 | #define LSW(x) ((uint16_t)((uint32_t)(x))) | ||
793 | #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) | ||
794 | |||
795 | #define LSD(x) ((uint32_t)((uint64_t)(x))) | ||
796 | #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) | ||
797 | |||
724 | #define QLCNIC_LEGACY_INTR_CONFIG \ | 798 | #define QLCNIC_LEGACY_INTR_CONFIG \ |
725 | { \ | 799 | { \ |
726 | { \ | 800 | { \ |