diff options
Diffstat (limited to 'drivers/net/pxa168_eth.c')
-rw-r--r-- | drivers/net/pxa168_eth.c | 1666 |
1 files changed, 1666 insertions, 0 deletions
diff --git a/drivers/net/pxa168_eth.c b/drivers/net/pxa168_eth.c new file mode 100644 index 000000000000..85eddda276bd --- /dev/null +++ b/drivers/net/pxa168_eth.c | |||
@@ -0,0 +1,1666 @@ | |||
1 | /* | ||
2 | * PXA168 ethernet driver. | ||
3 | * Most of the code is derived from mv643xx ethernet driver. | ||
4 | * | ||
5 | * Copyright (C) 2010 Marvell International Ltd. | ||
6 | * Sachin Sanap <ssanap@marvell.com> | ||
7 | * Philip Rakity <prakity@marvell.com> | ||
8 | * Mark Brown <markb@marvell.com> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or | ||
11 | * modify it under the terms of the GNU General Public License | ||
12 | * as published by the Free Software Foundation; either version 2 | ||
13 | * of the License, or (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
23 | */ | ||
24 | |||
25 | #include <linux/init.h> | ||
26 | #include <linux/dma-mapping.h> | ||
27 | #include <linux/in.h> | ||
28 | #include <linux/ip.h> | ||
29 | #include <linux/tcp.h> | ||
30 | #include <linux/udp.h> | ||
31 | #include <linux/etherdevice.h> | ||
32 | #include <linux/bitops.h> | ||
33 | #include <linux/delay.h> | ||
34 | #include <linux/ethtool.h> | ||
35 | #include <linux/platform_device.h> | ||
36 | #include <linux/module.h> | ||
37 | #include <linux/kernel.h> | ||
38 | #include <linux/workqueue.h> | ||
39 | #include <linux/clk.h> | ||
40 | #include <linux/phy.h> | ||
41 | #include <linux/io.h> | ||
42 | #include <linux/types.h> | ||
43 | #include <asm/pgtable.h> | ||
44 | #include <asm/system.h> | ||
45 | #include <linux/delay.h> | ||
46 | #include <linux/dma-mapping.h> | ||
47 | #include <asm/cacheflush.h> | ||
48 | #include <linux/pxa168_eth.h> | ||
49 | |||
50 | #define DRIVER_NAME "pxa168-eth" | ||
51 | #define DRIVER_VERSION "0.3" | ||
52 | |||
53 | /* | ||
54 | * Registers | ||
55 | */ | ||
56 | |||
57 | #define PHY_ADDRESS 0x0000 | ||
58 | #define SMI 0x0010 | ||
59 | #define PORT_CONFIG 0x0400 | ||
60 | #define PORT_CONFIG_EXT 0x0408 | ||
61 | #define PORT_COMMAND 0x0410 | ||
62 | #define PORT_STATUS 0x0418 | ||
63 | #define HTPR 0x0428 | ||
64 | #define SDMA_CONFIG 0x0440 | ||
65 | #define SDMA_CMD 0x0448 | ||
66 | #define INT_CAUSE 0x0450 | ||
67 | #define INT_W_CLEAR 0x0454 | ||
68 | #define INT_MASK 0x0458 | ||
69 | #define ETH_F_RX_DESC_0 0x0480 | ||
70 | #define ETH_C_RX_DESC_0 0x04A0 | ||
71 | #define ETH_C_TX_DESC_1 0x04E4 | ||
72 | |||
73 | /* smi register */ | ||
74 | #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */ | ||
75 | #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */ | ||
76 | #define SMI_OP_W (0 << 26) /* Write operation */ | ||
77 | #define SMI_OP_R (1 << 26) /* Read operation */ | ||
78 | |||
79 | #define PHY_WAIT_ITERATIONS 10 | ||
80 | |||
81 | #define PXA168_ETH_PHY_ADDR_DEFAULT 0 | ||
82 | /* RX & TX descriptor command */ | ||
83 | #define BUF_OWNED_BY_DMA (1 << 31) | ||
84 | |||
85 | /* RX descriptor status */ | ||
86 | #define RX_EN_INT (1 << 23) | ||
87 | #define RX_FIRST_DESC (1 << 17) | ||
88 | #define RX_LAST_DESC (1 << 16) | ||
89 | #define RX_ERROR (1 << 15) | ||
90 | |||
91 | /* TX descriptor command */ | ||
92 | #define TX_EN_INT (1 << 23) | ||
93 | #define TX_GEN_CRC (1 << 22) | ||
94 | #define TX_ZERO_PADDING (1 << 18) | ||
95 | #define TX_FIRST_DESC (1 << 17) | ||
96 | #define TX_LAST_DESC (1 << 16) | ||
97 | #define TX_ERROR (1 << 15) | ||
98 | |||
99 | /* SDMA_CMD */ | ||
100 | #define SDMA_CMD_AT (1 << 31) | ||
101 | #define SDMA_CMD_TXDL (1 << 24) | ||
102 | #define SDMA_CMD_TXDH (1 << 23) | ||
103 | #define SDMA_CMD_AR (1 << 15) | ||
104 | #define SDMA_CMD_ERD (1 << 7) | ||
105 | |||
106 | /* Bit definitions of the Port Config Reg */ | ||
107 | #define PCR_HS (1 << 12) | ||
108 | #define PCR_EN (1 << 7) | ||
109 | #define PCR_PM (1 << 0) | ||
110 | |||
111 | /* Bit definitions of the Port Config Extend Reg */ | ||
112 | #define PCXR_2BSM (1 << 28) | ||
113 | #define PCXR_DSCP_EN (1 << 21) | ||
114 | #define PCXR_MFL_1518 (0 << 14) | ||
115 | #define PCXR_MFL_1536 (1 << 14) | ||
116 | #define PCXR_MFL_2048 (2 << 14) | ||
117 | #define PCXR_MFL_64K (3 << 14) | ||
118 | #define PCXR_FLP (1 << 11) | ||
119 | #define PCXR_PRIO_TX_OFF 3 | ||
120 | #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) | ||
121 | |||
122 | /* Bit definitions of the SDMA Config Reg */ | ||
123 | #define SDCR_BSZ_OFF 12 | ||
124 | #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF) | ||
125 | #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF) | ||
126 | #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF) | ||
127 | #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF) | ||
128 | #define SDCR_BLMR (1 << 6) | ||
129 | #define SDCR_BLMT (1 << 7) | ||
130 | #define SDCR_RIFB (1 << 9) | ||
131 | #define SDCR_RC_OFF 2 | ||
132 | #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) | ||
133 | |||
134 | /* | ||
135 | * Bit definitions of the Interrupt Cause Reg | ||
136 | * and Interrupt MASK Reg is the same | ||
137 | */ | ||
138 | #define ICR_RXBUF (1 << 0) | ||
139 | #define ICR_TXBUF_H (1 << 2) | ||
140 | #define ICR_TXBUF_L (1 << 3) | ||
141 | #define ICR_TXEND_H (1 << 6) | ||
142 | #define ICR_TXEND_L (1 << 7) | ||
143 | #define ICR_RXERR (1 << 8) | ||
144 | #define ICR_TXERR_H (1 << 10) | ||
145 | #define ICR_TXERR_L (1 << 11) | ||
146 | #define ICR_TX_UDR (1 << 13) | ||
147 | #define ICR_MII_CH (1 << 28) | ||
148 | |||
149 | #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ | ||
150 | ICR_TXERR_H | ICR_TXERR_L |\ | ||
151 | ICR_TXEND_H | ICR_TXEND_L |\ | ||
152 | ICR_RXBUF | ICR_RXERR | ICR_MII_CH) | ||
153 | |||
154 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | ||
155 | |||
156 | #define NUM_RX_DESCS 64 | ||
157 | #define NUM_TX_DESCS 64 | ||
158 | |||
159 | #define HASH_ADD 0 | ||
160 | #define HASH_DELETE 1 | ||
161 | #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ | ||
162 | #define HOP_NUMBER 12 | ||
163 | |||
164 | /* Bit definitions for Port status */ | ||
165 | #define PORT_SPEED_100 (1 << 0) | ||
166 | #define FULL_DUPLEX (1 << 1) | ||
167 | #define FLOW_CONTROL_ENABLED (1 << 2) | ||
168 | #define LINK_UP (1 << 3) | ||
169 | |||
170 | /* Bit definitions for work to be done */ | ||
171 | #define WORK_LINK (1 << 0) | ||
172 | #define WORK_TX_DONE (1 << 1) | ||
173 | |||
174 | /* | ||
175 | * Misc definitions. | ||
176 | */ | ||
177 | #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) | ||
178 | |||
179 | struct rx_desc { | ||
180 | u32 cmd_sts; /* Descriptor command status */ | ||
181 | u16 byte_cnt; /* Descriptor buffer byte count */ | ||
182 | u16 buf_size; /* Buffer size */ | ||
183 | u32 buf_ptr; /* Descriptor buffer pointer */ | ||
184 | u32 next_desc_ptr; /* Next descriptor pointer */ | ||
185 | }; | ||
186 | |||
187 | struct tx_desc { | ||
188 | u32 cmd_sts; /* Command/status field */ | ||
189 | u16 reserved; | ||
190 | u16 byte_cnt; /* buffer byte count */ | ||
191 | u32 buf_ptr; /* pointer to buffer for this descriptor */ | ||
192 | u32 next_desc_ptr; /* Pointer to next descriptor */ | ||
193 | }; | ||
194 | |||
195 | struct pxa168_eth_private { | ||
196 | int port_num; /* User Ethernet port number */ | ||
197 | |||
198 | int rx_resource_err; /* Rx ring resource error flag */ | ||
199 | |||
200 | /* Next available and first returning Rx resource */ | ||
201 | int rx_curr_desc_q, rx_used_desc_q; | ||
202 | |||
203 | /* Next available and first returning Tx resource */ | ||
204 | int tx_curr_desc_q, tx_used_desc_q; | ||
205 | |||
206 | struct rx_desc *p_rx_desc_area; | ||
207 | dma_addr_t rx_desc_dma; | ||
208 | int rx_desc_area_size; | ||
209 | struct sk_buff **rx_skb; | ||
210 | |||
211 | struct tx_desc *p_tx_desc_area; | ||
212 | dma_addr_t tx_desc_dma; | ||
213 | int tx_desc_area_size; | ||
214 | struct sk_buff **tx_skb; | ||
215 | |||
216 | struct work_struct tx_timeout_task; | ||
217 | |||
218 | struct net_device *dev; | ||
219 | struct napi_struct napi; | ||
220 | u8 work_todo; | ||
221 | int skb_size; | ||
222 | |||
223 | struct net_device_stats stats; | ||
224 | /* Size of Tx Ring per queue */ | ||
225 | int tx_ring_size; | ||
226 | /* Number of tx descriptors in use */ | ||
227 | int tx_desc_count; | ||
228 | /* Size of Rx Ring per queue */ | ||
229 | int rx_ring_size; | ||
230 | /* Number of rx descriptors in use */ | ||
231 | int rx_desc_count; | ||
232 | |||
233 | /* | ||
234 | * Used in case RX Ring is empty, which can occur when | ||
235 | * system does not have resources (skb's) | ||
236 | */ | ||
237 | struct timer_list timeout; | ||
238 | struct mii_bus *smi_bus; | ||
239 | struct phy_device *phy; | ||
240 | |||
241 | /* clock */ | ||
242 | struct clk *clk; | ||
243 | struct pxa168_eth_platform_data *pd; | ||
244 | /* | ||
245 | * Ethernet controller base address. | ||
246 | */ | ||
247 | void __iomem *base; | ||
248 | |||
249 | /* Pointer to the hardware address filter table */ | ||
250 | void *htpr; | ||
251 | dma_addr_t htpr_dma; | ||
252 | }; | ||
253 | |||
254 | struct addr_table_entry { | ||
255 | __le32 lo; | ||
256 | __le32 hi; | ||
257 | }; | ||
258 | |||
259 | /* Bit fields of a Hash Table Entry */ | ||
260 | enum hash_table_entry { | ||
261 | HASH_ENTRY_VALID = 1, | ||
262 | SKIP = 2, | ||
263 | HASH_ENTRY_RECEIVE_DISCARD = 4, | ||
264 | HASH_ENTRY_RECEIVE_DISCARD_BIT = 2 | ||
265 | }; | ||
266 | |||
267 | static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd); | ||
268 | static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd); | ||
269 | static int pxa168_init_hw(struct pxa168_eth_private *pep); | ||
270 | static void eth_port_reset(struct net_device *dev); | ||
271 | static void eth_port_start(struct net_device *dev); | ||
272 | static int pxa168_eth_open(struct net_device *dev); | ||
273 | static int pxa168_eth_stop(struct net_device *dev); | ||
274 | static int ethernet_phy_setup(struct net_device *dev); | ||
275 | |||
276 | static inline u32 rdl(struct pxa168_eth_private *pep, int offset) | ||
277 | { | ||
278 | return readl(pep->base + offset); | ||
279 | } | ||
280 | |||
281 | static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) | ||
282 | { | ||
283 | writel(data, pep->base + offset); | ||
284 | } | ||
285 | |||
286 | static void abort_dma(struct pxa168_eth_private *pep) | ||
287 | { | ||
288 | int delay; | ||
289 | int max_retries = 40; | ||
290 | |||
291 | do { | ||
292 | wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); | ||
293 | udelay(100); | ||
294 | |||
295 | delay = 10; | ||
296 | while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT)) | ||
297 | && delay-- > 0) { | ||
298 | udelay(10); | ||
299 | } | ||
300 | } while (max_retries-- > 0 && delay <= 0); | ||
301 | |||
302 | if (max_retries <= 0) | ||
303 | printk(KERN_ERR "%s : DMA Stuck\n", __func__); | ||
304 | } | ||
305 | |||
306 | static int ethernet_phy_get(struct pxa168_eth_private *pep) | ||
307 | { | ||
308 | unsigned int reg_data; | ||
309 | |||
310 | reg_data = rdl(pep, PHY_ADDRESS); | ||
311 | |||
312 | return (reg_data >> (5 * pep->port_num)) & 0x1f; | ||
313 | } | ||
314 | |||
315 | static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr) | ||
316 | { | ||
317 | u32 reg_data; | ||
318 | int addr_shift = 5 * pep->port_num; | ||
319 | |||
320 | reg_data = rdl(pep, PHY_ADDRESS); | ||
321 | reg_data &= ~(0x1f << addr_shift); | ||
322 | reg_data |= (phy_addr & 0x1f) << addr_shift; | ||
323 | wrl(pep, PHY_ADDRESS, reg_data); | ||
324 | } | ||
325 | |||
326 | static void ethernet_phy_reset(struct pxa168_eth_private *pep) | ||
327 | { | ||
328 | int data; | ||
329 | |||
330 | data = phy_read(pep->phy, MII_BMCR); | ||
331 | if (data < 0) | ||
332 | return; | ||
333 | |||
334 | data |= BMCR_RESET; | ||
335 | if (phy_write(pep->phy, MII_BMCR, data) < 0) | ||
336 | return; | ||
337 | |||
338 | do { | ||
339 | data = phy_read(pep->phy, MII_BMCR); | ||
340 | } while (data >= 0 && data & BMCR_RESET); | ||
341 | } | ||
342 | |||
343 | static void rxq_refill(struct net_device *dev) | ||
344 | { | ||
345 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
346 | struct sk_buff *skb; | ||
347 | struct rx_desc *p_used_rx_desc; | ||
348 | int used_rx_desc; | ||
349 | |||
350 | while (pep->rx_desc_count < pep->rx_ring_size) { | ||
351 | int size; | ||
352 | |||
353 | skb = dev_alloc_skb(pep->skb_size); | ||
354 | if (!skb) | ||
355 | break; | ||
356 | if (SKB_DMA_REALIGN) | ||
357 | skb_reserve(skb, SKB_DMA_REALIGN); | ||
358 | pep->rx_desc_count++; | ||
359 | /* Get 'used' Rx descriptor */ | ||
360 | used_rx_desc = pep->rx_used_desc_q; | ||
361 | p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc]; | ||
362 | size = skb->end - skb->data; | ||
363 | p_used_rx_desc->buf_ptr = dma_map_single(NULL, | ||
364 | skb->data, | ||
365 | size, | ||
366 | DMA_FROM_DEVICE); | ||
367 | p_used_rx_desc->buf_size = size; | ||
368 | pep->rx_skb[used_rx_desc] = skb; | ||
369 | |||
370 | /* Return the descriptor to DMA ownership */ | ||
371 | wmb(); | ||
372 | p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; | ||
373 | wmb(); | ||
374 | |||
375 | /* Move the used descriptor pointer to the next descriptor */ | ||
376 | pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size; | ||
377 | |||
378 | /* Any Rx return cancels the Rx resource error status */ | ||
379 | pep->rx_resource_err = 0; | ||
380 | |||
381 | skb_reserve(skb, ETH_HW_IP_ALIGN); | ||
382 | } | ||
383 | |||
384 | /* | ||
385 | * If RX ring is empty of SKB, set a timer to try allocating | ||
386 | * again at a later time. | ||
387 | */ | ||
388 | if (pep->rx_desc_count == 0) { | ||
389 | pep->timeout.expires = jiffies + (HZ / 10); | ||
390 | add_timer(&pep->timeout); | ||
391 | } | ||
392 | } | ||
393 | |||
394 | static inline void rxq_refill_timer_wrapper(unsigned long data) | ||
395 | { | ||
396 | struct pxa168_eth_private *pep = (void *)data; | ||
397 | napi_schedule(&pep->napi); | ||
398 | } | ||
399 | |||
400 | static inline u8 flip_8_bits(u8 x) | ||
401 | { | ||
402 | return (((x) & 0x01) << 3) | (((x) & 0x02) << 1) | ||
403 | | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3) | ||
404 | | (((x) & 0x10) << 3) | (((x) & 0x20) << 1) | ||
405 | | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3); | ||
406 | } | ||
407 | |||
408 | static void nibble_swap_every_byte(unsigned char *mac_addr) | ||
409 | { | ||
410 | int i; | ||
411 | for (i = 0; i < ETH_ALEN; i++) { | ||
412 | mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) | | ||
413 | ((mac_addr[i] & 0xf0) >> 4); | ||
414 | } | ||
415 | } | ||
416 | |||
417 | static void inverse_every_nibble(unsigned char *mac_addr) | ||
418 | { | ||
419 | int i; | ||
420 | for (i = 0; i < ETH_ALEN; i++) | ||
421 | mac_addr[i] = flip_8_bits(mac_addr[i]); | ||
422 | } | ||
423 | |||
424 | /* | ||
425 | * ---------------------------------------------------------------------------- | ||
426 | * This function will calculate the hash function of the address. | ||
427 | * Inputs | ||
428 | * mac_addr_orig - MAC address. | ||
429 | * Outputs | ||
430 | * return the calculated entry. | ||
431 | */ | ||
432 | static u32 hash_function(unsigned char *mac_addr_orig) | ||
433 | { | ||
434 | u32 hash_result; | ||
435 | u32 addr0; | ||
436 | u32 addr1; | ||
437 | u32 addr2; | ||
438 | u32 addr3; | ||
439 | unsigned char mac_addr[ETH_ALEN]; | ||
440 | |||
441 | /* Make a copy of MAC address since we are going to performe bit | ||
442 | * operations on it | ||
443 | */ | ||
444 | memcpy(mac_addr, mac_addr_orig, ETH_ALEN); | ||
445 | |||
446 | nibble_swap_every_byte(mac_addr); | ||
447 | inverse_every_nibble(mac_addr); | ||
448 | |||
449 | addr0 = (mac_addr[5] >> 2) & 0x3f; | ||
450 | addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2); | ||
451 | addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1; | ||
452 | addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8); | ||
453 | |||
454 | hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); | ||
455 | hash_result = hash_result & 0x07ff; | ||
456 | return hash_result; | ||
457 | } | ||
458 | |||
459 | /* | ||
460 | * ---------------------------------------------------------------------------- | ||
461 | * This function will add/del an entry to the address table. | ||
462 | * Inputs | ||
463 | * pep - ETHERNET . | ||
464 | * mac_addr - MAC address. | ||
465 | * skip - if 1, skip this address.Used in case of deleting an entry which is a | ||
466 | * part of chain in the hash table.We cant just delete the entry since | ||
467 | * that will break the chain.We need to defragment the tables time to | ||
468 | * time. | ||
469 | * rd - 0 Discard packet upon match. | ||
470 | * - 1 Receive packet upon match. | ||
471 | * Outputs | ||
472 | * address table entry is added/deleted. | ||
473 | * 0 if success. | ||
474 | * -ENOSPC if table full | ||
475 | */ | ||
476 | static int add_del_hash_entry(struct pxa168_eth_private *pep, | ||
477 | unsigned char *mac_addr, | ||
478 | u32 rd, u32 skip, int del) | ||
479 | { | ||
480 | struct addr_table_entry *entry, *start; | ||
481 | u32 new_high; | ||
482 | u32 new_low; | ||
483 | u32 i; | ||
484 | |||
485 | new_low = (((mac_addr[1] >> 4) & 0xf) << 15) | ||
486 | | (((mac_addr[1] >> 0) & 0xf) << 11) | ||
487 | | (((mac_addr[0] >> 4) & 0xf) << 7) | ||
488 | | (((mac_addr[0] >> 0) & 0xf) << 3) | ||
489 | | (((mac_addr[3] >> 4) & 0x1) << 31) | ||
490 | | (((mac_addr[3] >> 0) & 0xf) << 27) | ||
491 | | (((mac_addr[2] >> 4) & 0xf) << 23) | ||
492 | | (((mac_addr[2] >> 0) & 0xf) << 19) | ||
493 | | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT) | ||
494 | | HASH_ENTRY_VALID; | ||
495 | |||
496 | new_high = (((mac_addr[5] >> 4) & 0xf) << 15) | ||
497 | | (((mac_addr[5] >> 0) & 0xf) << 11) | ||
498 | | (((mac_addr[4] >> 4) & 0xf) << 7) | ||
499 | | (((mac_addr[4] >> 0) & 0xf) << 3) | ||
500 | | (((mac_addr[3] >> 5) & 0x7) << 0); | ||
501 | |||
502 | /* | ||
503 | * Pick the appropriate table, start scanning for free/reusable | ||
504 | * entries at the index obtained by hashing the specified MAC address | ||
505 | */ | ||
506 | start = (struct addr_table_entry *)(pep->htpr); | ||
507 | entry = start + hash_function(mac_addr); | ||
508 | for (i = 0; i < HOP_NUMBER; i++) { | ||
509 | if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) { | ||
510 | break; | ||
511 | } else { | ||
512 | /* if same address put in same position */ | ||
513 | if (((le32_to_cpu(entry->lo) & 0xfffffff8) == | ||
514 | (new_low & 0xfffffff8)) && | ||
515 | (le32_to_cpu(entry->hi) == new_high)) { | ||
516 | break; | ||
517 | } | ||
518 | } | ||
519 | if (entry == start + 0x7ff) | ||
520 | entry = start; | ||
521 | else | ||
522 | entry++; | ||
523 | } | ||
524 | |||
525 | if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) && | ||
526 | (le32_to_cpu(entry->hi) != new_high) && del) | ||
527 | return 0; | ||
528 | |||
529 | if (i == HOP_NUMBER) { | ||
530 | if (!del) { | ||
531 | printk(KERN_INFO "%s: table section is full, need to " | ||
532 | "move to 16kB implementation?\n", | ||
533 | __FILE__); | ||
534 | return -ENOSPC; | ||
535 | } else | ||
536 | return 0; | ||
537 | } | ||
538 | |||
539 | /* | ||
540 | * Update the selected entry | ||
541 | */ | ||
542 | if (del) { | ||
543 | entry->hi = 0; | ||
544 | entry->lo = 0; | ||
545 | } else { | ||
546 | entry->hi = cpu_to_le32(new_high); | ||
547 | entry->lo = cpu_to_le32(new_low); | ||
548 | } | ||
549 | |||
550 | return 0; | ||
551 | } | ||
552 | |||
553 | /* | ||
554 | * ---------------------------------------------------------------------------- | ||
555 | * Create an addressTable entry from MAC address info | ||
556 | * found in the specifed net_device struct | ||
557 | * | ||
558 | * Input : pointer to ethernet interface network device structure | ||
559 | * Output : N/A | ||
560 | */ | ||
561 | static void update_hash_table_mac_address(struct pxa168_eth_private *pep, | ||
562 | unsigned char *oaddr, | ||
563 | unsigned char *addr) | ||
564 | { | ||
565 | /* Delete old entry */ | ||
566 | if (oaddr) | ||
567 | add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE); | ||
568 | /* Add new entry */ | ||
569 | add_del_hash_entry(pep, addr, 1, 0, HASH_ADD); | ||
570 | } | ||
571 | |||
572 | static int init_hash_table(struct pxa168_eth_private *pep) | ||
573 | { | ||
574 | /* | ||
575 | * Hardware expects CPU to build a hash table based on a predefined | ||
576 | * hash function and populate it based on hardware address. The | ||
577 | * location of the hash table is identified by 32-bit pointer stored | ||
578 | * in HTPR internal register. Two possible sizes exists for the hash | ||
579 | * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB | ||
580 | * (16kB of DRAM required (4 x 4 kB banks)).We currently only support | ||
581 | * 1/2kB. | ||
582 | */ | ||
583 | /* TODO: Add support for 8kB hash table and alternative hash | ||
584 | * function.Driver can dynamically switch to them if the 1/2kB hash | ||
585 | * table is full. | ||
586 | */ | ||
587 | if (pep->htpr == NULL) { | ||
588 | pep->htpr = dma_alloc_coherent(pep->dev->dev.parent, | ||
589 | HASH_ADDR_TABLE_SIZE, | ||
590 | &pep->htpr_dma, GFP_KERNEL); | ||
591 | if (pep->htpr == NULL) | ||
592 | return -ENOMEM; | ||
593 | } | ||
594 | memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); | ||
595 | wrl(pep, HTPR, pep->htpr_dma); | ||
596 | return 0; | ||
597 | } | ||
598 | |||
599 | static void pxa168_eth_set_rx_mode(struct net_device *dev) | ||
600 | { | ||
601 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
602 | struct netdev_hw_addr *ha; | ||
603 | u32 val; | ||
604 | |||
605 | val = rdl(pep, PORT_CONFIG); | ||
606 | if (dev->flags & IFF_PROMISC) | ||
607 | val |= PCR_PM; | ||
608 | else | ||
609 | val &= ~PCR_PM; | ||
610 | wrl(pep, PORT_CONFIG, val); | ||
611 | |||
612 | /* | ||
613 | * Remove the old list of MAC address and add dev->addr | ||
614 | * and multicast address. | ||
615 | */ | ||
616 | memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); | ||
617 | update_hash_table_mac_address(pep, NULL, dev->dev_addr); | ||
618 | |||
619 | netdev_for_each_mc_addr(ha, dev) | ||
620 | update_hash_table_mac_address(pep, NULL, ha->addr); | ||
621 | } | ||
622 | |||
623 | static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr) | ||
624 | { | ||
625 | struct sockaddr *sa = addr; | ||
626 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
627 | unsigned char oldMac[ETH_ALEN]; | ||
628 | |||
629 | if (!is_valid_ether_addr(sa->sa_data)) | ||
630 | return -EINVAL; | ||
631 | memcpy(oldMac, dev->dev_addr, ETH_ALEN); | ||
632 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); | ||
633 | netif_addr_lock_bh(dev); | ||
634 | update_hash_table_mac_address(pep, oldMac, dev->dev_addr); | ||
635 | netif_addr_unlock_bh(dev); | ||
636 | return 0; | ||
637 | } | ||
638 | |||
639 | static void eth_port_start(struct net_device *dev) | ||
640 | { | ||
641 | unsigned int val = 0; | ||
642 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
643 | int tx_curr_desc, rx_curr_desc; | ||
644 | |||
645 | /* Perform PHY reset, if there is a PHY. */ | ||
646 | if (pep->phy != NULL) { | ||
647 | struct ethtool_cmd cmd; | ||
648 | |||
649 | pxa168_get_settings(pep->dev, &cmd); | ||
650 | ethernet_phy_reset(pep); | ||
651 | pxa168_set_settings(pep->dev, &cmd); | ||
652 | } | ||
653 | |||
654 | /* Assignment of Tx CTRP of given queue */ | ||
655 | tx_curr_desc = pep->tx_curr_desc_q; | ||
656 | wrl(pep, ETH_C_TX_DESC_1, | ||
657 | (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc))); | ||
658 | |||
659 | /* Assignment of Rx CRDP of given queue */ | ||
660 | rx_curr_desc = pep->rx_curr_desc_q; | ||
661 | wrl(pep, ETH_C_RX_DESC_0, | ||
662 | (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); | ||
663 | |||
664 | wrl(pep, ETH_F_RX_DESC_0, | ||
665 | (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); | ||
666 | |||
667 | /* Clear all interrupts */ | ||
668 | wrl(pep, INT_CAUSE, 0); | ||
669 | |||
670 | /* Enable all interrupts for receive, transmit and error. */ | ||
671 | wrl(pep, INT_MASK, ALL_INTS); | ||
672 | |||
673 | val = rdl(pep, PORT_CONFIG); | ||
674 | val |= PCR_EN; | ||
675 | wrl(pep, PORT_CONFIG, val); | ||
676 | |||
677 | /* Start RX DMA engine */ | ||
678 | val = rdl(pep, SDMA_CMD); | ||
679 | val |= SDMA_CMD_ERD; | ||
680 | wrl(pep, SDMA_CMD, val); | ||
681 | } | ||
682 | |||
683 | static void eth_port_reset(struct net_device *dev) | ||
684 | { | ||
685 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
686 | unsigned int val = 0; | ||
687 | |||
688 | /* Stop all interrupts for receive, transmit and error. */ | ||
689 | wrl(pep, INT_MASK, 0); | ||
690 | |||
691 | /* Clear all interrupts */ | ||
692 | wrl(pep, INT_CAUSE, 0); | ||
693 | |||
694 | /* Stop RX DMA */ | ||
695 | val = rdl(pep, SDMA_CMD); | ||
696 | val &= ~SDMA_CMD_ERD; /* abort dma command */ | ||
697 | |||
698 | /* Abort any transmit and receive operations and put DMA | ||
699 | * in idle state. | ||
700 | */ | ||
701 | abort_dma(pep); | ||
702 | |||
703 | /* Disable port */ | ||
704 | val = rdl(pep, PORT_CONFIG); | ||
705 | val &= ~PCR_EN; | ||
706 | wrl(pep, PORT_CONFIG, val); | ||
707 | } | ||
708 | |||
709 | /* | ||
710 | * txq_reclaim - Free the tx desc data for completed descriptors | ||
711 | * If force is non-zero, frees uncompleted descriptors as well | ||
712 | */ | ||
713 | static int txq_reclaim(struct net_device *dev, int force) | ||
714 | { | ||
715 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
716 | struct tx_desc *desc; | ||
717 | u32 cmd_sts; | ||
718 | struct sk_buff *skb; | ||
719 | int tx_index; | ||
720 | dma_addr_t addr; | ||
721 | int count; | ||
722 | int released = 0; | ||
723 | |||
724 | netif_tx_lock(dev); | ||
725 | |||
726 | pep->work_todo &= ~WORK_TX_DONE; | ||
727 | while (pep->tx_desc_count > 0) { | ||
728 | tx_index = pep->tx_used_desc_q; | ||
729 | desc = &pep->p_tx_desc_area[tx_index]; | ||
730 | cmd_sts = desc->cmd_sts; | ||
731 | if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) { | ||
732 | if (released > 0) { | ||
733 | goto txq_reclaim_end; | ||
734 | } else { | ||
735 | released = -1; | ||
736 | goto txq_reclaim_end; | ||
737 | } | ||
738 | } | ||
739 | pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size; | ||
740 | pep->tx_desc_count--; | ||
741 | addr = desc->buf_ptr; | ||
742 | count = desc->byte_cnt; | ||
743 | skb = pep->tx_skb[tx_index]; | ||
744 | if (skb) | ||
745 | pep->tx_skb[tx_index] = NULL; | ||
746 | |||
747 | if (cmd_sts & TX_ERROR) { | ||
748 | if (net_ratelimit()) | ||
749 | printk(KERN_ERR "%s: Error in TX\n", dev->name); | ||
750 | dev->stats.tx_errors++; | ||
751 | } | ||
752 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | ||
753 | if (skb) | ||
754 | dev_kfree_skb_irq(skb); | ||
755 | released++; | ||
756 | } | ||
757 | txq_reclaim_end: | ||
758 | netif_tx_unlock(dev); | ||
759 | return released; | ||
760 | } | ||
761 | |||
762 | static void pxa168_eth_tx_timeout(struct net_device *dev) | ||
763 | { | ||
764 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
765 | |||
766 | printk(KERN_INFO "%s: TX timeout desc_count %d\n", | ||
767 | dev->name, pep->tx_desc_count); | ||
768 | |||
769 | schedule_work(&pep->tx_timeout_task); | ||
770 | } | ||
771 | |||
772 | static void pxa168_eth_tx_timeout_task(struct work_struct *work) | ||
773 | { | ||
774 | struct pxa168_eth_private *pep = container_of(work, | ||
775 | struct pxa168_eth_private, | ||
776 | tx_timeout_task); | ||
777 | struct net_device *dev = pep->dev; | ||
778 | pxa168_eth_stop(dev); | ||
779 | pxa168_eth_open(dev); | ||
780 | } | ||
781 | |||
782 | static int rxq_process(struct net_device *dev, int budget) | ||
783 | { | ||
784 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
785 | struct net_device_stats *stats = &dev->stats; | ||
786 | unsigned int received_packets = 0; | ||
787 | struct sk_buff *skb; | ||
788 | |||
789 | while (budget-- > 0) { | ||
790 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; | ||
791 | struct rx_desc *rx_desc; | ||
792 | unsigned int cmd_sts; | ||
793 | |||
794 | /* Do not process Rx ring in case of Rx ring resource error */ | ||
795 | if (pep->rx_resource_err) | ||
796 | break; | ||
797 | rx_curr_desc = pep->rx_curr_desc_q; | ||
798 | rx_used_desc = pep->rx_used_desc_q; | ||
799 | rx_desc = &pep->p_rx_desc_area[rx_curr_desc]; | ||
800 | cmd_sts = rx_desc->cmd_sts; | ||
801 | rmb(); | ||
802 | if (cmd_sts & (BUF_OWNED_BY_DMA)) | ||
803 | break; | ||
804 | skb = pep->rx_skb[rx_curr_desc]; | ||
805 | pep->rx_skb[rx_curr_desc] = NULL; | ||
806 | |||
807 | rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size; | ||
808 | pep->rx_curr_desc_q = rx_next_curr_desc; | ||
809 | |||
810 | /* Rx descriptors exhausted. */ | ||
811 | /* Set the Rx ring resource error flag */ | ||
812 | if (rx_next_curr_desc == rx_used_desc) | ||
813 | pep->rx_resource_err = 1; | ||
814 | pep->rx_desc_count--; | ||
815 | dma_unmap_single(NULL, rx_desc->buf_ptr, | ||
816 | rx_desc->buf_size, | ||
817 | DMA_FROM_DEVICE); | ||
818 | received_packets++; | ||
819 | /* | ||
820 | * Update statistics. | ||
821 | * Note byte count includes 4 byte CRC count | ||
822 | */ | ||
823 | stats->rx_packets++; | ||
824 | stats->rx_bytes += rx_desc->byte_cnt; | ||
825 | /* | ||
826 | * In case received a packet without first / last bits on OR | ||
827 | * the error summary bit is on, the packets needs to be droped. | ||
828 | */ | ||
829 | if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | ||
830 | (RX_FIRST_DESC | RX_LAST_DESC)) | ||
831 | || (cmd_sts & RX_ERROR)) { | ||
832 | |||
833 | stats->rx_dropped++; | ||
834 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | ||
835 | (RX_FIRST_DESC | RX_LAST_DESC)) { | ||
836 | if (net_ratelimit()) | ||
837 | printk(KERN_ERR | ||
838 | "%s: Rx pkt on multiple desc\n", | ||
839 | dev->name); | ||
840 | } | ||
841 | if (cmd_sts & RX_ERROR) | ||
842 | stats->rx_errors++; | ||
843 | dev_kfree_skb_irq(skb); | ||
844 | } else { | ||
845 | /* | ||
846 | * The -4 is for the CRC in the trailer of the | ||
847 | * received packet | ||
848 | */ | ||
849 | skb_put(skb, rx_desc->byte_cnt - 4); | ||
850 | skb->protocol = eth_type_trans(skb, dev); | ||
851 | netif_receive_skb(skb); | ||
852 | } | ||
853 | dev->last_rx = jiffies; | ||
854 | } | ||
855 | /* Fill RX ring with skb's */ | ||
856 | rxq_refill(dev); | ||
857 | return received_packets; | ||
858 | } | ||
859 | |||
860 | static int pxa168_eth_collect_events(struct pxa168_eth_private *pep, | ||
861 | struct net_device *dev) | ||
862 | { | ||
863 | u32 icr; | ||
864 | int ret = 0; | ||
865 | |||
866 | icr = rdl(pep, INT_CAUSE); | ||
867 | if (icr == 0) | ||
868 | return IRQ_NONE; | ||
869 | |||
870 | wrl(pep, INT_CAUSE, ~icr); | ||
871 | if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) { | ||
872 | pep->work_todo |= WORK_TX_DONE; | ||
873 | ret = 1; | ||
874 | } | ||
875 | if (icr & ICR_RXBUF) | ||
876 | ret = 1; | ||
877 | if (icr & ICR_MII_CH) { | ||
878 | pep->work_todo |= WORK_LINK; | ||
879 | ret = 1; | ||
880 | } | ||
881 | return ret; | ||
882 | } | ||
883 | |||
884 | static void handle_link_event(struct pxa168_eth_private *pep) | ||
885 | { | ||
886 | struct net_device *dev = pep->dev; | ||
887 | u32 port_status; | ||
888 | int speed; | ||
889 | int duplex; | ||
890 | int fc; | ||
891 | |||
892 | port_status = rdl(pep, PORT_STATUS); | ||
893 | if (!(port_status & LINK_UP)) { | ||
894 | if (netif_carrier_ok(dev)) { | ||
895 | printk(KERN_INFO "%s: link down\n", dev->name); | ||
896 | netif_carrier_off(dev); | ||
897 | txq_reclaim(dev, 1); | ||
898 | } | ||
899 | return; | ||
900 | } | ||
901 | if (port_status & PORT_SPEED_100) | ||
902 | speed = 100; | ||
903 | else | ||
904 | speed = 10; | ||
905 | |||
906 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | ||
907 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; | ||
908 | printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " | ||
909 | "flow control %sabled\n", dev->name, | ||
910 | speed, duplex ? "full" : "half", fc ? "en" : "dis"); | ||
911 | if (!netif_carrier_ok(dev)) | ||
912 | netif_carrier_on(dev); | ||
913 | } | ||
914 | |||
915 | static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id) | ||
916 | { | ||
917 | struct net_device *dev = (struct net_device *)dev_id; | ||
918 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
919 | |||
920 | if (unlikely(!pxa168_eth_collect_events(pep, dev))) | ||
921 | return IRQ_NONE; | ||
922 | /* Disable interrupts */ | ||
923 | wrl(pep, INT_MASK, 0); | ||
924 | napi_schedule(&pep->napi); | ||
925 | return IRQ_HANDLED; | ||
926 | } | ||
927 | |||
928 | static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep) | ||
929 | { | ||
930 | int skb_size; | ||
931 | |||
932 | /* | ||
933 | * Reserve 2+14 bytes for an ethernet header (the hardware | ||
934 | * automatically prepends 2 bytes of dummy data to each | ||
935 | * received packet), 16 bytes for up to four VLAN tags, and | ||
936 | * 4 bytes for the trailing FCS -- 36 bytes total. | ||
937 | */ | ||
938 | skb_size = pep->dev->mtu + 36; | ||
939 | |||
940 | /* | ||
941 | * Make sure that the skb size is a multiple of 8 bytes, as | ||
942 | * the lower three bits of the receive descriptor's buffer | ||
943 | * size field are ignored by the hardware. | ||
944 | */ | ||
945 | pep->skb_size = (skb_size + 7) & ~7; | ||
946 | |||
947 | /* | ||
948 | * If NET_SKB_PAD is smaller than a cache line, | ||
949 | * netdev_alloc_skb() will cause skb->data to be misaligned | ||
950 | * to a cache line boundary. If this is the case, include | ||
951 | * some extra space to allow re-aligning the data area. | ||
952 | */ | ||
953 | pep->skb_size += SKB_DMA_REALIGN; | ||
954 | |||
955 | } | ||
956 | |||
957 | static int set_port_config_ext(struct pxa168_eth_private *pep) | ||
958 | { | ||
959 | int skb_size; | ||
960 | |||
961 | pxa168_eth_recalc_skb_size(pep); | ||
962 | if (pep->skb_size <= 1518) | ||
963 | skb_size = PCXR_MFL_1518; | ||
964 | else if (pep->skb_size <= 1536) | ||
965 | skb_size = PCXR_MFL_1536; | ||
966 | else if (pep->skb_size <= 2048) | ||
967 | skb_size = PCXR_MFL_2048; | ||
968 | else | ||
969 | skb_size = PCXR_MFL_64K; | ||
970 | |||
971 | /* Extended Port Configuration */ | ||
972 | wrl(pep, | ||
973 | PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */ | ||
974 | PCXR_DSCP_EN | /* Enable DSCP in IP */ | ||
975 | skb_size | PCXR_FLP | /* do not force link pass */ | ||
976 | PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */ | ||
977 | |||
978 | return 0; | ||
979 | } | ||
980 | |||
981 | static int pxa168_init_hw(struct pxa168_eth_private *pep) | ||
982 | { | ||
983 | int err = 0; | ||
984 | |||
985 | /* Disable interrupts */ | ||
986 | wrl(pep, INT_MASK, 0); | ||
987 | wrl(pep, INT_CAUSE, 0); | ||
988 | /* Write to ICR to clear interrupts. */ | ||
989 | wrl(pep, INT_W_CLEAR, 0); | ||
990 | /* Abort any transmit and receive operations and put DMA | ||
991 | * in idle state. | ||
992 | */ | ||
993 | abort_dma(pep); | ||
994 | /* Initialize address hash table */ | ||
995 | err = init_hash_table(pep); | ||
996 | if (err) | ||
997 | return err; | ||
998 | /* SDMA configuration */ | ||
999 | wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ | ||
1000 | SDCR_RIFB | /* Rx interrupt on frame */ | ||
1001 | SDCR_BLMT | /* Little endian transmit */ | ||
1002 | SDCR_BLMR | /* Little endian receive */ | ||
1003 | SDCR_RC_MAX_RETRANS); /* Max retransmit count */ | ||
1004 | /* Port Configuration */ | ||
1005 | wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ | ||
1006 | set_port_config_ext(pep); | ||
1007 | |||
1008 | return err; | ||
1009 | } | ||
1010 | |||
1011 | static int rxq_init(struct net_device *dev) | ||
1012 | { | ||
1013 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1014 | struct rx_desc *p_rx_desc; | ||
1015 | int size = 0, i = 0; | ||
1016 | int rx_desc_num = pep->rx_ring_size; | ||
1017 | |||
1018 | /* Allocate RX skb rings */ | ||
1019 | pep->rx_skb = kmalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size, | ||
1020 | GFP_KERNEL); | ||
1021 | if (!pep->rx_skb) { | ||
1022 | printk(KERN_ERR "%s: Cannot alloc RX skb ring\n", dev->name); | ||
1023 | return -ENOMEM; | ||
1024 | } | ||
1025 | /* Allocate RX ring */ | ||
1026 | pep->rx_desc_count = 0; | ||
1027 | size = pep->rx_ring_size * sizeof(struct rx_desc); | ||
1028 | pep->rx_desc_area_size = size; | ||
1029 | pep->p_rx_desc_area = dma_alloc_coherent(pep->dev->dev.parent, size, | ||
1030 | &pep->rx_desc_dma, GFP_KERNEL); | ||
1031 | if (!pep->p_rx_desc_area) { | ||
1032 | printk(KERN_ERR "%s: Cannot alloc RX ring (size %d bytes)\n", | ||
1033 | dev->name, size); | ||
1034 | goto out; | ||
1035 | } | ||
1036 | memset((void *)pep->p_rx_desc_area, 0, size); | ||
1037 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | ||
1038 | p_rx_desc = (struct rx_desc *)pep->p_rx_desc_area; | ||
1039 | for (i = 0; i < rx_desc_num; i++) { | ||
1040 | p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma + | ||
1041 | ((i + 1) % rx_desc_num) * sizeof(struct rx_desc); | ||
1042 | } | ||
1043 | /* Save Rx desc pointer to driver struct. */ | ||
1044 | pep->rx_curr_desc_q = 0; | ||
1045 | pep->rx_used_desc_q = 0; | ||
1046 | pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc); | ||
1047 | return 0; | ||
1048 | out: | ||
1049 | kfree(pep->rx_skb); | ||
1050 | return -ENOMEM; | ||
1051 | } | ||
1052 | |||
1053 | static void rxq_deinit(struct net_device *dev) | ||
1054 | { | ||
1055 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1056 | int curr; | ||
1057 | |||
1058 | /* Free preallocated skb's on RX rings */ | ||
1059 | for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) { | ||
1060 | if (pep->rx_skb[curr]) { | ||
1061 | dev_kfree_skb(pep->rx_skb[curr]); | ||
1062 | pep->rx_desc_count--; | ||
1063 | } | ||
1064 | } | ||
1065 | if (pep->rx_desc_count) | ||
1066 | printk(KERN_ERR | ||
1067 | "Error in freeing Rx Ring. %d skb's still\n", | ||
1068 | pep->rx_desc_count); | ||
1069 | /* Free RX ring */ | ||
1070 | if (pep->p_rx_desc_area) | ||
1071 | dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size, | ||
1072 | pep->p_rx_desc_area, pep->rx_desc_dma); | ||
1073 | kfree(pep->rx_skb); | ||
1074 | } | ||
1075 | |||
1076 | static int txq_init(struct net_device *dev) | ||
1077 | { | ||
1078 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1079 | struct tx_desc *p_tx_desc; | ||
1080 | int size = 0, i = 0; | ||
1081 | int tx_desc_num = pep->tx_ring_size; | ||
1082 | |||
1083 | pep->tx_skb = kmalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size, | ||
1084 | GFP_KERNEL); | ||
1085 | if (!pep->tx_skb) { | ||
1086 | printk(KERN_ERR "%s: Cannot alloc TX skb ring\n", dev->name); | ||
1087 | return -ENOMEM; | ||
1088 | } | ||
1089 | /* Allocate TX ring */ | ||
1090 | pep->tx_desc_count = 0; | ||
1091 | size = pep->tx_ring_size * sizeof(struct tx_desc); | ||
1092 | pep->tx_desc_area_size = size; | ||
1093 | pep->p_tx_desc_area = dma_alloc_coherent(pep->dev->dev.parent, size, | ||
1094 | &pep->tx_desc_dma, GFP_KERNEL); | ||
1095 | if (!pep->p_tx_desc_area) { | ||
1096 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | ||
1097 | dev->name, size); | ||
1098 | goto out; | ||
1099 | } | ||
1100 | memset((void *)pep->p_tx_desc_area, 0, pep->tx_desc_area_size); | ||
1101 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ | ||
1102 | p_tx_desc = (struct tx_desc *)pep->p_tx_desc_area; | ||
1103 | for (i = 0; i < tx_desc_num; i++) { | ||
1104 | p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma + | ||
1105 | ((i + 1) % tx_desc_num) * sizeof(struct tx_desc); | ||
1106 | } | ||
1107 | pep->tx_curr_desc_q = 0; | ||
1108 | pep->tx_used_desc_q = 0; | ||
1109 | pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc); | ||
1110 | return 0; | ||
1111 | out: | ||
1112 | kfree(pep->tx_skb); | ||
1113 | return -ENOMEM; | ||
1114 | } | ||
1115 | |||
1116 | static void txq_deinit(struct net_device *dev) | ||
1117 | { | ||
1118 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1119 | |||
1120 | /* Free outstanding skb's on TX ring */ | ||
1121 | txq_reclaim(dev, 1); | ||
1122 | BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q); | ||
1123 | /* Free TX ring */ | ||
1124 | if (pep->p_tx_desc_area) | ||
1125 | dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size, | ||
1126 | pep->p_tx_desc_area, pep->tx_desc_dma); | ||
1127 | kfree(pep->tx_skb); | ||
1128 | } | ||
1129 | |||
1130 | static int pxa168_eth_open(struct net_device *dev) | ||
1131 | { | ||
1132 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1133 | int err; | ||
1134 | |||
1135 | err = request_irq(dev->irq, pxa168_eth_int_handler, | ||
1136 | IRQF_DISABLED, dev->name, dev); | ||
1137 | if (err) { | ||
1138 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); | ||
1139 | return -EAGAIN; | ||
1140 | } | ||
1141 | pep->rx_resource_err = 0; | ||
1142 | err = rxq_init(dev); | ||
1143 | if (err != 0) | ||
1144 | goto out_free_irq; | ||
1145 | err = txq_init(dev); | ||
1146 | if (err != 0) | ||
1147 | goto out_free_rx_skb; | ||
1148 | pep->rx_used_desc_q = 0; | ||
1149 | pep->rx_curr_desc_q = 0; | ||
1150 | |||
1151 | /* Fill RX ring with skb's */ | ||
1152 | rxq_refill(dev); | ||
1153 | pep->rx_used_desc_q = 0; | ||
1154 | pep->rx_curr_desc_q = 0; | ||
1155 | netif_carrier_off(dev); | ||
1156 | eth_port_start(dev); | ||
1157 | napi_enable(&pep->napi); | ||
1158 | return 0; | ||
1159 | out_free_rx_skb: | ||
1160 | rxq_deinit(dev); | ||
1161 | out_free_irq: | ||
1162 | free_irq(dev->irq, dev); | ||
1163 | return err; | ||
1164 | } | ||
1165 | |||
1166 | static int pxa168_eth_stop(struct net_device *dev) | ||
1167 | { | ||
1168 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1169 | eth_port_reset(dev); | ||
1170 | |||
1171 | /* Disable interrupts */ | ||
1172 | wrl(pep, INT_MASK, 0); | ||
1173 | wrl(pep, INT_CAUSE, 0); | ||
1174 | /* Write to ICR to clear interrupts. */ | ||
1175 | wrl(pep, INT_W_CLEAR, 0); | ||
1176 | napi_disable(&pep->napi); | ||
1177 | del_timer_sync(&pep->timeout); | ||
1178 | netif_carrier_off(dev); | ||
1179 | free_irq(dev->irq, dev); | ||
1180 | rxq_deinit(dev); | ||
1181 | txq_deinit(dev); | ||
1182 | |||
1183 | return 0; | ||
1184 | } | ||
1185 | |||
1186 | static int pxa168_eth_change_mtu(struct net_device *dev, int mtu) | ||
1187 | { | ||
1188 | int retval; | ||
1189 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1190 | |||
1191 | if ((mtu > 9500) || (mtu < 68)) | ||
1192 | return -EINVAL; | ||
1193 | |||
1194 | dev->mtu = mtu; | ||
1195 | retval = set_port_config_ext(pep); | ||
1196 | |||
1197 | if (!netif_running(dev)) | ||
1198 | return 0; | ||
1199 | |||
1200 | /* | ||
1201 | * Stop and then re-open the interface. This will allocate RX | ||
1202 | * skbs of the new MTU. | ||
1203 | * There is a possible danger that the open will not succeed, | ||
1204 | * due to memory being full. | ||
1205 | */ | ||
1206 | pxa168_eth_stop(dev); | ||
1207 | if (pxa168_eth_open(dev)) { | ||
1208 | dev_printk(KERN_ERR, &dev->dev, | ||
1209 | "fatal error on re-opening device after " | ||
1210 | "MTU change\n"); | ||
1211 | } | ||
1212 | |||
1213 | return 0; | ||
1214 | } | ||
1215 | |||
1216 | static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep) | ||
1217 | { | ||
1218 | int tx_desc_curr; | ||
1219 | |||
1220 | tx_desc_curr = pep->tx_curr_desc_q; | ||
1221 | pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size; | ||
1222 | BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q); | ||
1223 | pep->tx_desc_count++; | ||
1224 | |||
1225 | return tx_desc_curr; | ||
1226 | } | ||
1227 | |||
1228 | static int pxa168_rx_poll(struct napi_struct *napi, int budget) | ||
1229 | { | ||
1230 | struct pxa168_eth_private *pep = | ||
1231 | container_of(napi, struct pxa168_eth_private, napi); | ||
1232 | struct net_device *dev = pep->dev; | ||
1233 | int work_done = 0; | ||
1234 | |||
1235 | if (unlikely(pep->work_todo & WORK_LINK)) { | ||
1236 | pep->work_todo &= ~(WORK_LINK); | ||
1237 | handle_link_event(pep); | ||
1238 | } | ||
1239 | /* | ||
1240 | * We call txq_reclaim every time since in NAPI interupts are disabled | ||
1241 | * and due to this we miss the TX_DONE interrupt,which is not updated in | ||
1242 | * interrupt status register. | ||
1243 | */ | ||
1244 | txq_reclaim(dev, 0); | ||
1245 | if (netif_queue_stopped(dev) | ||
1246 | && pep->tx_ring_size - pep->tx_desc_count > 1) { | ||
1247 | netif_wake_queue(dev); | ||
1248 | } | ||
1249 | work_done = rxq_process(dev, budget); | ||
1250 | if (work_done < budget) { | ||
1251 | napi_complete(napi); | ||
1252 | wrl(pep, INT_MASK, ALL_INTS); | ||
1253 | } | ||
1254 | |||
1255 | return work_done; | ||
1256 | } | ||
1257 | |||
1258 | static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) | ||
1259 | { | ||
1260 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1261 | struct net_device_stats *stats = &dev->stats; | ||
1262 | struct tx_desc *desc; | ||
1263 | int tx_index; | ||
1264 | int length; | ||
1265 | |||
1266 | tx_index = eth_alloc_tx_desc_index(pep); | ||
1267 | desc = &pep->p_tx_desc_area[tx_index]; | ||
1268 | length = skb->len; | ||
1269 | pep->tx_skb[tx_index] = skb; | ||
1270 | desc->byte_cnt = length; | ||
1271 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | ||
1272 | wmb(); | ||
1273 | desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC | | ||
1274 | TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT; | ||
1275 | wmb(); | ||
1276 | wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); | ||
1277 | |||
1278 | stats->tx_bytes += skb->len; | ||
1279 | stats->tx_packets++; | ||
1280 | dev->trans_start = jiffies; | ||
1281 | if (pep->tx_ring_size - pep->tx_desc_count <= 1) { | ||
1282 | /* We handled the current skb, but now we are out of space.*/ | ||
1283 | netif_stop_queue(dev); | ||
1284 | } | ||
1285 | |||
1286 | return NETDEV_TX_OK; | ||
1287 | } | ||
1288 | |||
1289 | static int smi_wait_ready(struct pxa168_eth_private *pep) | ||
1290 | { | ||
1291 | int i = 0; | ||
1292 | |||
1293 | /* wait for the SMI register to become available */ | ||
1294 | for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) { | ||
1295 | if (i == PHY_WAIT_ITERATIONS) | ||
1296 | return -ETIMEDOUT; | ||
1297 | msleep(10); | ||
1298 | } | ||
1299 | |||
1300 | return 0; | ||
1301 | } | ||
1302 | |||
1303 | static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum) | ||
1304 | { | ||
1305 | struct pxa168_eth_private *pep = bus->priv; | ||
1306 | int i = 0; | ||
1307 | int val; | ||
1308 | |||
1309 | if (smi_wait_ready(pep)) { | ||
1310 | printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n"); | ||
1311 | return -ETIMEDOUT; | ||
1312 | } | ||
1313 | wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); | ||
1314 | /* now wait for the data to be valid */ | ||
1315 | for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) { | ||
1316 | if (i == PHY_WAIT_ITERATIONS) { | ||
1317 | printk(KERN_WARNING | ||
1318 | "pxa168_eth: SMI bus read not valid\n"); | ||
1319 | return -ENODEV; | ||
1320 | } | ||
1321 | msleep(10); | ||
1322 | } | ||
1323 | |||
1324 | return val & 0xffff; | ||
1325 | } | ||
1326 | |||
1327 | static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum, | ||
1328 | u16 value) | ||
1329 | { | ||
1330 | struct pxa168_eth_private *pep = bus->priv; | ||
1331 | |||
1332 | if (smi_wait_ready(pep)) { | ||
1333 | printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n"); | ||
1334 | return -ETIMEDOUT; | ||
1335 | } | ||
1336 | |||
1337 | wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | | ||
1338 | SMI_OP_W | (value & 0xffff)); | ||
1339 | |||
1340 | if (smi_wait_ready(pep)) { | ||
1341 | printk(KERN_ERR "pxa168_eth: SMI bus busy timeout\n"); | ||
1342 | return -ETIMEDOUT; | ||
1343 | } | ||
1344 | |||
1345 | return 0; | ||
1346 | } | ||
1347 | |||
1348 | static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, | ||
1349 | int cmd) | ||
1350 | { | ||
1351 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1352 | if (pep->phy != NULL) | ||
1353 | return phy_mii_ioctl(pep->phy, ifr, cmd); | ||
1354 | |||
1355 | return -EOPNOTSUPP; | ||
1356 | } | ||
1357 | |||
1358 | static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr) | ||
1359 | { | ||
1360 | struct mii_bus *bus = pep->smi_bus; | ||
1361 | struct phy_device *phydev; | ||
1362 | int start; | ||
1363 | int num; | ||
1364 | int i; | ||
1365 | |||
1366 | if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) { | ||
1367 | /* Scan entire range */ | ||
1368 | start = ethernet_phy_get(pep); | ||
1369 | num = 32; | ||
1370 | } else { | ||
1371 | /* Use phy addr specific to platform */ | ||
1372 | start = phy_addr & 0x1f; | ||
1373 | num = 1; | ||
1374 | } | ||
1375 | phydev = NULL; | ||
1376 | for (i = 0; i < num; i++) { | ||
1377 | int addr = (start + i) & 0x1f; | ||
1378 | if (bus->phy_map[addr] == NULL) | ||
1379 | mdiobus_scan(bus, addr); | ||
1380 | |||
1381 | if (phydev == NULL) { | ||
1382 | phydev = bus->phy_map[addr]; | ||
1383 | if (phydev != NULL) | ||
1384 | ethernet_phy_set_addr(pep, addr); | ||
1385 | } | ||
1386 | } | ||
1387 | |||
1388 | return phydev; | ||
1389 | } | ||
1390 | |||
1391 | static void phy_init(struct pxa168_eth_private *pep, int speed, int duplex) | ||
1392 | { | ||
1393 | struct phy_device *phy = pep->phy; | ||
1394 | ethernet_phy_reset(pep); | ||
1395 | |||
1396 | phy_attach(pep->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_MII); | ||
1397 | |||
1398 | if (speed == 0) { | ||
1399 | phy->autoneg = AUTONEG_ENABLE; | ||
1400 | phy->speed = 0; | ||
1401 | phy->duplex = 0; | ||
1402 | phy->supported &= PHY_BASIC_FEATURES; | ||
1403 | phy->advertising = phy->supported | ADVERTISED_Autoneg; | ||
1404 | } else { | ||
1405 | phy->autoneg = AUTONEG_DISABLE; | ||
1406 | phy->advertising = 0; | ||
1407 | phy->speed = speed; | ||
1408 | phy->duplex = duplex; | ||
1409 | } | ||
1410 | phy_start_aneg(phy); | ||
1411 | } | ||
1412 | |||
1413 | static int ethernet_phy_setup(struct net_device *dev) | ||
1414 | { | ||
1415 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1416 | |||
1417 | if (pep->pd->init) | ||
1418 | pep->pd->init(); | ||
1419 | pep->phy = phy_scan(pep, pep->pd->phy_addr & 0x1f); | ||
1420 | if (pep->phy != NULL) | ||
1421 | phy_init(pep, pep->pd->speed, pep->pd->duplex); | ||
1422 | update_hash_table_mac_address(pep, NULL, dev->dev_addr); | ||
1423 | |||
1424 | return 0; | ||
1425 | } | ||
1426 | |||
1427 | static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
1428 | { | ||
1429 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1430 | int err; | ||
1431 | |||
1432 | err = phy_read_status(pep->phy); | ||
1433 | if (err == 0) | ||
1434 | err = phy_ethtool_gset(pep->phy, cmd); | ||
1435 | |||
1436 | return err; | ||
1437 | } | ||
1438 | |||
1439 | static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
1440 | { | ||
1441 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1442 | |||
1443 | return phy_ethtool_sset(pep->phy, cmd); | ||
1444 | } | ||
1445 | |||
1446 | static void pxa168_get_drvinfo(struct net_device *dev, | ||
1447 | struct ethtool_drvinfo *info) | ||
1448 | { | ||
1449 | strncpy(info->driver, DRIVER_NAME, 32); | ||
1450 | strncpy(info->version, DRIVER_VERSION, 32); | ||
1451 | strncpy(info->fw_version, "N/A", 32); | ||
1452 | strncpy(info->bus_info, "N/A", 32); | ||
1453 | } | ||
1454 | |||
1455 | static u32 pxa168_get_link(struct net_device *dev) | ||
1456 | { | ||
1457 | return !!netif_carrier_ok(dev); | ||
1458 | } | ||
1459 | |||
1460 | static const struct ethtool_ops pxa168_ethtool_ops = { | ||
1461 | .get_settings = pxa168_get_settings, | ||
1462 | .set_settings = pxa168_set_settings, | ||
1463 | .get_drvinfo = pxa168_get_drvinfo, | ||
1464 | .get_link = pxa168_get_link, | ||
1465 | }; | ||
1466 | |||
1467 | static const struct net_device_ops pxa168_eth_netdev_ops = { | ||
1468 | .ndo_open = pxa168_eth_open, | ||
1469 | .ndo_stop = pxa168_eth_stop, | ||
1470 | .ndo_start_xmit = pxa168_eth_start_xmit, | ||
1471 | .ndo_set_rx_mode = pxa168_eth_set_rx_mode, | ||
1472 | .ndo_set_mac_address = pxa168_eth_set_mac_address, | ||
1473 | .ndo_validate_addr = eth_validate_addr, | ||
1474 | .ndo_do_ioctl = pxa168_eth_do_ioctl, | ||
1475 | .ndo_change_mtu = pxa168_eth_change_mtu, | ||
1476 | .ndo_tx_timeout = pxa168_eth_tx_timeout, | ||
1477 | }; | ||
1478 | |||
1479 | static int pxa168_eth_probe(struct platform_device *pdev) | ||
1480 | { | ||
1481 | struct pxa168_eth_private *pep = NULL; | ||
1482 | struct net_device *dev = NULL; | ||
1483 | struct resource *res; | ||
1484 | struct clk *clk; | ||
1485 | int err; | ||
1486 | |||
1487 | printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n"); | ||
1488 | |||
1489 | clk = clk_get(&pdev->dev, "MFUCLK"); | ||
1490 | if (IS_ERR(clk)) { | ||
1491 | printk(KERN_ERR "%s: Fast Ethernet failed to get clock\n", | ||
1492 | DRIVER_NAME); | ||
1493 | return -ENODEV; | ||
1494 | } | ||
1495 | clk_enable(clk); | ||
1496 | |||
1497 | dev = alloc_etherdev(sizeof(struct pxa168_eth_private)); | ||
1498 | if (!dev) { | ||
1499 | err = -ENOMEM; | ||
1500 | goto err_clk; | ||
1501 | } | ||
1502 | |||
1503 | platform_set_drvdata(pdev, dev); | ||
1504 | pep = netdev_priv(dev); | ||
1505 | pep->dev = dev; | ||
1506 | pep->clk = clk; | ||
1507 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1508 | if (res == NULL) { | ||
1509 | err = -ENODEV; | ||
1510 | goto err_netdev; | ||
1511 | } | ||
1512 | pep->base = ioremap(res->start, res->end - res->start + 1); | ||
1513 | if (pep->base == NULL) { | ||
1514 | err = -ENOMEM; | ||
1515 | goto err_netdev; | ||
1516 | } | ||
1517 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
1518 | BUG_ON(!res); | ||
1519 | dev->irq = res->start; | ||
1520 | dev->netdev_ops = &pxa168_eth_netdev_ops; | ||
1521 | dev->watchdog_timeo = 2 * HZ; | ||
1522 | dev->base_addr = 0; | ||
1523 | SET_ETHTOOL_OPS(dev, &pxa168_ethtool_ops); | ||
1524 | |||
1525 | INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task); | ||
1526 | |||
1527 | printk(KERN_INFO "%s:Using random mac address\n", DRIVER_NAME); | ||
1528 | random_ether_addr(dev->dev_addr); | ||
1529 | |||
1530 | pep->pd = pdev->dev.platform_data; | ||
1531 | pep->rx_ring_size = NUM_RX_DESCS; | ||
1532 | if (pep->pd->rx_queue_size) | ||
1533 | pep->rx_ring_size = pep->pd->rx_queue_size; | ||
1534 | |||
1535 | pep->tx_ring_size = NUM_TX_DESCS; | ||
1536 | if (pep->pd->tx_queue_size) | ||
1537 | pep->tx_ring_size = pep->pd->tx_queue_size; | ||
1538 | |||
1539 | pep->port_num = pep->pd->port_number; | ||
1540 | /* Hardware supports only 3 ports */ | ||
1541 | BUG_ON(pep->port_num > 2); | ||
1542 | netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size); | ||
1543 | |||
1544 | memset(&pep->timeout, 0, sizeof(struct timer_list)); | ||
1545 | init_timer(&pep->timeout); | ||
1546 | pep->timeout.function = rxq_refill_timer_wrapper; | ||
1547 | pep->timeout.data = (unsigned long)pep; | ||
1548 | |||
1549 | pep->smi_bus = mdiobus_alloc(); | ||
1550 | if (pep->smi_bus == NULL) { | ||
1551 | err = -ENOMEM; | ||
1552 | goto err_base; | ||
1553 | } | ||
1554 | pep->smi_bus->priv = pep; | ||
1555 | pep->smi_bus->name = "pxa168_eth smi"; | ||
1556 | pep->smi_bus->read = pxa168_smi_read; | ||
1557 | pep->smi_bus->write = pxa168_smi_write; | ||
1558 | snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); | ||
1559 | pep->smi_bus->parent = &pdev->dev; | ||
1560 | pep->smi_bus->phy_mask = 0xffffffff; | ||
1561 | err = mdiobus_register(pep->smi_bus); | ||
1562 | if (err) | ||
1563 | goto err_free_mdio; | ||
1564 | |||
1565 | pxa168_init_hw(pep); | ||
1566 | err = ethernet_phy_setup(dev); | ||
1567 | if (err) | ||
1568 | goto err_mdiobus; | ||
1569 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
1570 | err = register_netdev(dev); | ||
1571 | if (err) | ||
1572 | goto err_mdiobus; | ||
1573 | return 0; | ||
1574 | |||
1575 | err_mdiobus: | ||
1576 | mdiobus_unregister(pep->smi_bus); | ||
1577 | err_free_mdio: | ||
1578 | mdiobus_free(pep->smi_bus); | ||
1579 | err_base: | ||
1580 | iounmap(pep->base); | ||
1581 | err_netdev: | ||
1582 | free_netdev(dev); | ||
1583 | err_clk: | ||
1584 | clk_disable(clk); | ||
1585 | clk_put(clk); | ||
1586 | return err; | ||
1587 | } | ||
1588 | |||
1589 | static int pxa168_eth_remove(struct platform_device *pdev) | ||
1590 | { | ||
1591 | struct net_device *dev = platform_get_drvdata(pdev); | ||
1592 | struct pxa168_eth_private *pep = netdev_priv(dev); | ||
1593 | |||
1594 | if (pep->htpr) { | ||
1595 | dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE, | ||
1596 | pep->htpr, pep->htpr_dma); | ||
1597 | pep->htpr = NULL; | ||
1598 | } | ||
1599 | if (pep->clk) { | ||
1600 | clk_disable(pep->clk); | ||
1601 | clk_put(pep->clk); | ||
1602 | pep->clk = NULL; | ||
1603 | } | ||
1604 | if (pep->phy != NULL) | ||
1605 | phy_detach(pep->phy); | ||
1606 | |||
1607 | iounmap(pep->base); | ||
1608 | pep->base = NULL; | ||
1609 | mdiobus_unregister(pep->smi_bus); | ||
1610 | mdiobus_free(pep->smi_bus); | ||
1611 | unregister_netdev(dev); | ||
1612 | flush_scheduled_work(); | ||
1613 | free_netdev(dev); | ||
1614 | platform_set_drvdata(pdev, NULL); | ||
1615 | return 0; | ||
1616 | } | ||
1617 | |||
1618 | static void pxa168_eth_shutdown(struct platform_device *pdev) | ||
1619 | { | ||
1620 | struct net_device *dev = platform_get_drvdata(pdev); | ||
1621 | eth_port_reset(dev); | ||
1622 | } | ||
1623 | |||
1624 | #ifdef CONFIG_PM | ||
1625 | static int pxa168_eth_resume(struct platform_device *pdev) | ||
1626 | { | ||
1627 | return -ENOSYS; | ||
1628 | } | ||
1629 | |||
1630 | static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state) | ||
1631 | { | ||
1632 | return -ENOSYS; | ||
1633 | } | ||
1634 | |||
1635 | #else | ||
1636 | #define pxa168_eth_resume NULL | ||
1637 | #define pxa168_eth_suspend NULL | ||
1638 | #endif | ||
1639 | |||
1640 | static struct platform_driver pxa168_eth_driver = { | ||
1641 | .probe = pxa168_eth_probe, | ||
1642 | .remove = pxa168_eth_remove, | ||
1643 | .shutdown = pxa168_eth_shutdown, | ||
1644 | .resume = pxa168_eth_resume, | ||
1645 | .suspend = pxa168_eth_suspend, | ||
1646 | .driver = { | ||
1647 | .name = DRIVER_NAME, | ||
1648 | }, | ||
1649 | }; | ||
1650 | |||
1651 | static int __init pxa168_init_module(void) | ||
1652 | { | ||
1653 | return platform_driver_register(&pxa168_eth_driver); | ||
1654 | } | ||
1655 | |||
1656 | static void __exit pxa168_cleanup_module(void) | ||
1657 | { | ||
1658 | platform_driver_unregister(&pxa168_eth_driver); | ||
1659 | } | ||
1660 | |||
1661 | module_init(pxa168_init_module); | ||
1662 | module_exit(pxa168_cleanup_module); | ||
1663 | |||
1664 | MODULE_LICENSE("GPL"); | ||
1665 | MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168"); | ||
1666 | MODULE_ALIAS("platform:pxa168_eth"); | ||