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-rw-r--r--drivers/net/phy/Kconfig3
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/bcm63xx.c2
-rw-r--r--drivers/net/phy/broadcom.c2
-rw-r--r--drivers/net/phy/cicada.c2
-rw-r--r--drivers/net/phy/davicom.c2
-rw-r--r--drivers/net/phy/dp83640.c1110
-rw-r--r--drivers/net/phy/dp83640_reg.h267
-rw-r--r--drivers/net/phy/et1011c.c2
-rw-r--r--drivers/net/phy/icplus.c61
-rw-r--r--drivers/net/phy/lxt.c2
-rw-r--r--drivers/net/phy/marvell.c215
-rw-r--r--drivers/net/phy/mdio-gpio.c9
-rw-r--r--drivers/net/phy/micrel.c26
-rw-r--r--drivers/net/phy/national.c2
-rw-r--r--drivers/net/phy/phy.c37
-rw-r--r--drivers/net/phy/phy_device.c31
-rw-r--r--drivers/net/phy/qsemi.c2
-rw-r--r--drivers/net/phy/realtek.c2
-rw-r--r--drivers/net/phy/smsc.c2
-rw-r--r--drivers/net/phy/ste10Xp.c2
-rw-r--r--drivers/net/phy/vitesse.c2
22 files changed, 1684 insertions, 100 deletions
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index eb799b36c86a..a70244306c94 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -65,7 +65,7 @@ config BCM63XX_PHY
65config ICPLUS_PHY 65config ICPLUS_PHY
66 tristate "Drivers for ICPlus PHYs" 66 tristate "Drivers for ICPlus PHYs"
67 ---help--- 67 ---help---
68 Currently supports the IP175C PHY. 68 Currently supports the IP175C and IP1001 PHYs.
69 69
70config REALTEK_PHY 70config REALTEK_PHY
71 tristate "Drivers for Realtek PHYs" 71 tristate "Drivers for Realtek PHYs"
@@ -78,7 +78,6 @@ config NATIONAL_PHY
78 Currently supports the DP83865 PHY. 78 Currently supports the DP83865 PHY.
79 79
80config STE10XP 80config STE10XP
81 depends on PHYLIB
82 tristate "Driver for STMicroelectronics STe10Xp PHYs" 81 tristate "Driver for STMicroelectronics STe10Xp PHYs"
83 ---help--- 82 ---help---
84 This is the driver for the STe100p and STe101p PHYs. 83 This is the driver for the STe100p and STe101p PHYs.
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab65d02..2333215bbb32 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
19obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o 19obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
20obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o 20obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
21obj-$(CONFIG_NATIONAL_PHY) += national.o 21obj-$(CONFIG_NATIONAL_PHY) += national.o
22obj-$(CONFIG_DP83640_PHY) += dp83640.o
22obj-$(CONFIG_STE10XP) += ste10Xp.o 23obj-$(CONFIG_STE10XP) += ste10Xp.o
23obj-$(CONFIG_MICREL_PHY) += micrel.o 24obj-$(CONFIG_MICREL_PHY) += micrel.o
24obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o 25obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/bcm63xx.c b/drivers/net/phy/bcm63xx.c
index c12815679837..e16f98cb4f04 100644
--- a/drivers/net/phy/bcm63xx.c
+++ b/drivers/net/phy/bcm63xx.c
@@ -131,7 +131,7 @@ static void __exit bcm63xx_phy_exit(void)
131module_init(bcm63xx_phy_init); 131module_init(bcm63xx_phy_init);
132module_exit(bcm63xx_phy_exit); 132module_exit(bcm63xx_phy_exit);
133 133
134static struct mdio_device_id bcm63xx_tbl[] = { 134static struct mdio_device_id __maybe_unused bcm63xx_tbl[] = {
135 { 0x00406000, 0xfffffc00 }, 135 { 0x00406000, 0xfffffc00 },
136 { 0x002bdc00, 0xfffffc00 }, 136 { 0x002bdc00, 0xfffffc00 },
137 { } 137 { }
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 4accd83d3dfe..d84c4224dd12 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -930,7 +930,7 @@ static void __exit broadcom_exit(void)
930module_init(broadcom_init); 930module_init(broadcom_init);
931module_exit(broadcom_exit); 931module_exit(broadcom_exit);
932 932
933static struct mdio_device_id broadcom_tbl[] = { 933static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
934 { PHY_ID_BCM5411, 0xfffffff0 }, 934 { PHY_ID_BCM5411, 0xfffffff0 },
935 { PHY_ID_BCM5421, 0xfffffff0 }, 935 { PHY_ID_BCM5421, 0xfffffff0 },
936 { PHY_ID_BCM5461, 0xfffffff0 }, 936 { PHY_ID_BCM5461, 0xfffffff0 },
diff --git a/drivers/net/phy/cicada.c b/drivers/net/phy/cicada.c
index 1a325d63756b..d28173161c21 100644
--- a/drivers/net/phy/cicada.c
+++ b/drivers/net/phy/cicada.c
@@ -159,7 +159,7 @@ static void __exit cicada_exit(void)
159module_init(cicada_init); 159module_init(cicada_init);
160module_exit(cicada_exit); 160module_exit(cicada_exit);
161 161
162static struct mdio_device_id cicada_tbl[] = { 162static struct mdio_device_id __maybe_unused cicada_tbl[] = {
163 { 0x000fc410, 0x000ffff0 }, 163 { 0x000fc410, 0x000ffff0 },
164 { 0x000fc440, 0x000fffc0 }, 164 { 0x000fc440, 0x000fffc0 },
165 { } 165 { }
diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c
index 29c17617a2ec..2f774acdb551 100644
--- a/drivers/net/phy/davicom.c
+++ b/drivers/net/phy/davicom.c
@@ -219,7 +219,7 @@ static void __exit davicom_exit(void)
219module_init(davicom_init); 219module_init(davicom_init);
220module_exit(davicom_exit); 220module_exit(davicom_exit);
221 221
222static struct mdio_device_id davicom_tbl[] = { 222static struct mdio_device_id __maybe_unused davicom_tbl[] = {
223 { 0x0181b880, 0x0ffffff0 }, 223 { 0x0181b880, 0x0ffffff0 },
224 { 0x0181b8a0, 0x0ffffff0 }, 224 { 0x0181b8a0, 0x0ffffff0 },
225 { 0x00181b80, 0x0ffffff0 }, 225 { 0x00181b80, 0x0ffffff0 },
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 000000000000..2cd8dc5847b4
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1110 @@
1/*
2 * Driver for the National Semiconductor DP83640 PHYTER
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20#include <linux/ethtool.h>
21#include <linux/kernel.h>
22#include <linux/list.h>
23#include <linux/mii.h>
24#include <linux/module.h>
25#include <linux/net_tstamp.h>
26#include <linux/netdevice.h>
27#include <linux/phy.h>
28#include <linux/ptp_classify.h>
29#include <linux/ptp_clock_kernel.h>
30
31#include "dp83640_reg.h"
32
33#define DP83640_PHY_ID 0x20005ce1
34#define PAGESEL 0x13
35#define LAYER4 0x02
36#define LAYER2 0x01
37#define MAX_RXTS 4
38#define MAX_TXTS 4
39#define N_EXT_TS 1
40#define PSF_PTPVER 2
41#define PSF_EVNT 0x4000
42#define PSF_RX 0x2000
43#define PSF_TX 0x1000
44#define EXT_EVENT 1
45#define EXT_GPIO 1
46#define CAL_EVENT 2
47#define CAL_GPIO 9
48#define CAL_TRIGGER 2
49
50/* phyter seems to miss the mark by 16 ns */
51#define ADJTIME_FIX 16
52
53#if defined(__BIG_ENDIAN)
54#define ENDIAN_FLAG 0
55#elif defined(__LITTLE_ENDIAN)
56#define ENDIAN_FLAG PSF_ENDIAN
57#endif
58
59#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
60
61struct phy_rxts {
62 u16 ns_lo; /* ns[15:0] */
63 u16 ns_hi; /* overflow[1:0], ns[29:16] */
64 u16 sec_lo; /* sec[15:0] */
65 u16 sec_hi; /* sec[31:16] */
66 u16 seqid; /* sequenceId[15:0] */
67 u16 msgtype; /* messageType[3:0], hash[11:0] */
68};
69
70struct phy_txts {
71 u16 ns_lo; /* ns[15:0] */
72 u16 ns_hi; /* overflow[1:0], ns[29:16] */
73 u16 sec_lo; /* sec[15:0] */
74 u16 sec_hi; /* sec[31:16] */
75};
76
77struct rxts {
78 struct list_head list;
79 unsigned long tmo;
80 u64 ns;
81 u16 seqid;
82 u8 msgtype;
83 u16 hash;
84};
85
86struct dp83640_clock;
87
88struct dp83640_private {
89 struct list_head list;
90 struct dp83640_clock *clock;
91 struct phy_device *phydev;
92 struct work_struct ts_work;
93 int hwts_tx_en;
94 int hwts_rx_en;
95 int layer;
96 int version;
97 /* remember state of cfg0 during calibration */
98 int cfg0;
99 /* remember the last event time stamp */
100 struct phy_txts edata;
101 /* list of rx timestamps */
102 struct list_head rxts;
103 struct list_head rxpool;
104 struct rxts rx_pool_data[MAX_RXTS];
105 /* protects above three fields from concurrent access */
106 spinlock_t rx_lock;
107 /* queues of incoming and outgoing packets */
108 struct sk_buff_head rx_queue;
109 struct sk_buff_head tx_queue;
110};
111
112struct dp83640_clock {
113 /* keeps the instance in the 'phyter_clocks' list */
114 struct list_head list;
115 /* we create one clock instance per MII bus */
116 struct mii_bus *bus;
117 /* protects extended registers from concurrent access */
118 struct mutex extreg_lock;
119 /* remembers which page was last selected */
120 int page;
121 /* our advertised capabilities */
122 struct ptp_clock_info caps;
123 /* protects the three fields below from concurrent access */
124 struct mutex clock_lock;
125 /* the one phyter from which we shall read */
126 struct dp83640_private *chosen;
127 /* list of the other attached phyters, not chosen */
128 struct list_head phylist;
129 /* reference to our PTP hardware clock */
130 struct ptp_clock *ptp_clock;
131};
132
133/* globals */
134
135static int chosen_phy = -1;
136static ushort cal_gpio = 4;
137
138module_param(chosen_phy, int, 0444);
139module_param(cal_gpio, ushort, 0444);
140
141MODULE_PARM_DESC(chosen_phy, \
142 "The address of the PHY to use for the ancillary clock features");
143MODULE_PARM_DESC(cal_gpio, \
144 "Which GPIO line to use for synchronizing multiple PHYs");
145
146/* a list of clocks and a mutex to protect it */
147static LIST_HEAD(phyter_clocks);
148static DEFINE_MUTEX(phyter_clocks_lock);
149
150static void rx_timestamp_work(struct work_struct *work);
151
152/* extended register access functions */
153
154#define BROADCAST_ADDR 31
155
156static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
157{
158 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
159}
160
161/* Caller must hold extreg_lock. */
162static int ext_read(struct phy_device *phydev, int page, u32 regnum)
163{
164 struct dp83640_private *dp83640 = phydev->priv;
165 int val;
166
167 if (dp83640->clock->page != page) {
168 broadcast_write(phydev->bus, PAGESEL, page);
169 dp83640->clock->page = page;
170 }
171 val = phy_read(phydev, regnum);
172
173 return val;
174}
175
176/* Caller must hold extreg_lock. */
177static void ext_write(int broadcast, struct phy_device *phydev,
178 int page, u32 regnum, u16 val)
179{
180 struct dp83640_private *dp83640 = phydev->priv;
181
182 if (dp83640->clock->page != page) {
183 broadcast_write(phydev->bus, PAGESEL, page);
184 dp83640->clock->page = page;
185 }
186 if (broadcast)
187 broadcast_write(phydev->bus, regnum, val);
188 else
189 phy_write(phydev, regnum, val);
190}
191
192/* Caller must hold extreg_lock. */
193static int tdr_write(int bc, struct phy_device *dev,
194 const struct timespec *ts, u16 cmd)
195{
196 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
197 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
198 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
199 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
200
201 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
202
203 return 0;
204}
205
206/* convert phy timestamps into driver timestamps */
207
208static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
209{
210 u32 sec;
211
212 sec = p->sec_lo;
213 sec |= p->sec_hi << 16;
214
215 rxts->ns = p->ns_lo;
216 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
217 rxts->ns += ((u64)sec) * 1000000000ULL;
218 rxts->seqid = p->seqid;
219 rxts->msgtype = (p->msgtype >> 12) & 0xf;
220 rxts->hash = p->msgtype & 0x0fff;
221 rxts->tmo = jiffies + HZ;
222}
223
224static u64 phy2txts(struct phy_txts *p)
225{
226 u64 ns;
227 u32 sec;
228
229 sec = p->sec_lo;
230 sec |= p->sec_hi << 16;
231
232 ns = p->ns_lo;
233 ns |= (p->ns_hi & 0x3fff) << 16;
234 ns += ((u64)sec) * 1000000000ULL;
235
236 return ns;
237}
238
239/* ptp clock methods */
240
241static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
242{
243 struct dp83640_clock *clock =
244 container_of(ptp, struct dp83640_clock, caps);
245 struct phy_device *phydev = clock->chosen->phydev;
246 u64 rate;
247 int neg_adj = 0;
248 u16 hi, lo;
249
250 if (ppb < 0) {
251 neg_adj = 1;
252 ppb = -ppb;
253 }
254 rate = ppb;
255 rate <<= 26;
256 rate = div_u64(rate, 1953125);
257
258 hi = (rate >> 16) & PTP_RATE_HI_MASK;
259 if (neg_adj)
260 hi |= PTP_RATE_DIR;
261
262 lo = rate & 0xffff;
263
264 mutex_lock(&clock->extreg_lock);
265
266 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
267 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
268
269 mutex_unlock(&clock->extreg_lock);
270
271 return 0;
272}
273
274static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
275{
276 struct dp83640_clock *clock =
277 container_of(ptp, struct dp83640_clock, caps);
278 struct phy_device *phydev = clock->chosen->phydev;
279 struct timespec ts;
280 int err;
281
282 delta += ADJTIME_FIX;
283
284 ts = ns_to_timespec(delta);
285
286 mutex_lock(&clock->extreg_lock);
287
288 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
289
290 mutex_unlock(&clock->extreg_lock);
291
292 return err;
293}
294
295static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
296{
297 struct dp83640_clock *clock =
298 container_of(ptp, struct dp83640_clock, caps);
299 struct phy_device *phydev = clock->chosen->phydev;
300 unsigned int val[4];
301
302 mutex_lock(&clock->extreg_lock);
303
304 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
305
306 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
307 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
308 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
309 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
310
311 mutex_unlock(&clock->extreg_lock);
312
313 ts->tv_nsec = val[0] | (val[1] << 16);
314 ts->tv_sec = val[2] | (val[3] << 16);
315
316 return 0;
317}
318
319static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
320 const struct timespec *ts)
321{
322 struct dp83640_clock *clock =
323 container_of(ptp, struct dp83640_clock, caps);
324 struct phy_device *phydev = clock->chosen->phydev;
325 int err;
326
327 mutex_lock(&clock->extreg_lock);
328
329 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
330
331 mutex_unlock(&clock->extreg_lock);
332
333 return err;
334}
335
336static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
337 struct ptp_clock_request *rq, int on)
338{
339 struct dp83640_clock *clock =
340 container_of(ptp, struct dp83640_clock, caps);
341 struct phy_device *phydev = clock->chosen->phydev;
342 u16 evnt;
343
344 switch (rq->type) {
345 case PTP_CLK_REQ_EXTTS:
346 if (rq->extts.index != 0)
347 return -EINVAL;
348 evnt = EVNT_WR | (EXT_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
349 if (on) {
350 evnt |= (EXT_GPIO & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
351 evnt |= EVNT_RISE;
352 }
353 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
354 return 0;
355 default:
356 break;
357 }
358
359 return -EOPNOTSUPP;
360}
361
362static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
363static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
364
365static void enable_status_frames(struct phy_device *phydev, bool on)
366{
367 u16 cfg0 = 0, ver;
368
369 if (on)
370 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
371
372 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
373
374 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
375 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
376
377 if (!phydev->attached_dev) {
378 pr_warning("dp83640: expected to find an attached netdevice\n");
379 return;
380 }
381
382 if (on) {
383 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
384 pr_warning("dp83640: failed to add mc address\n");
385 } else {
386 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
387 pr_warning("dp83640: failed to delete mc address\n");
388 }
389}
390
391static bool is_status_frame(struct sk_buff *skb, int type)
392{
393 struct ethhdr *h = eth_hdr(skb);
394
395 if (PTP_CLASS_V2_L2 == type &&
396 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
397 return true;
398 else
399 return false;
400}
401
402static int expired(struct rxts *rxts)
403{
404 return time_after(jiffies, rxts->tmo);
405}
406
407/* Caller must hold rx_lock. */
408static void prune_rx_ts(struct dp83640_private *dp83640)
409{
410 struct list_head *this, *next;
411 struct rxts *rxts;
412
413 list_for_each_safe(this, next, &dp83640->rxts) {
414 rxts = list_entry(this, struct rxts, list);
415 if (expired(rxts)) {
416 list_del_init(&rxts->list);
417 list_add(&rxts->list, &dp83640->rxpool);
418 }
419 }
420}
421
422/* synchronize the phyters so they act as one clock */
423
424static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
425{
426 int val;
427 phy_write(phydev, PAGESEL, 0);
428 val = phy_read(phydev, PHYCR2);
429 if (on)
430 val |= BC_WRITE;
431 else
432 val &= ~BC_WRITE;
433 phy_write(phydev, PHYCR2, val);
434 phy_write(phydev, PAGESEL, init_page);
435}
436
437static void recalibrate(struct dp83640_clock *clock)
438{
439 s64 now, diff;
440 struct phy_txts event_ts;
441 struct timespec ts;
442 struct list_head *this;
443 struct dp83640_private *tmp;
444 struct phy_device *master = clock->chosen->phydev;
445 u16 cfg0, evnt, ptp_trig, trigger, val;
446
447 trigger = CAL_TRIGGER;
448
449 mutex_lock(&clock->extreg_lock);
450
451 /*
452 * enable broadcast, disable status frames, enable ptp clock
453 */
454 list_for_each(this, &clock->phylist) {
455 tmp = list_entry(this, struct dp83640_private, list);
456 enable_broadcast(tmp->phydev, clock->page, 1);
457 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
458 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
459 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
460 }
461 enable_broadcast(master, clock->page, 1);
462 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
463 ext_write(0, master, PAGE5, PSF_CFG0, 0);
464 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
465
466 /*
467 * enable an event timestamp
468 */
469 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
470 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
471 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
472
473 list_for_each(this, &clock->phylist) {
474 tmp = list_entry(this, struct dp83640_private, list);
475 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
476 }
477 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
478
479 /*
480 * configure a trigger
481 */
482 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
483 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
484 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
485 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
486
487 /* load trigger */
488 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
489 val |= TRIG_LOAD;
490 ext_write(0, master, PAGE4, PTP_CTL, val);
491
492 /* enable trigger */
493 val &= ~TRIG_LOAD;
494 val |= TRIG_EN;
495 ext_write(0, master, PAGE4, PTP_CTL, val);
496
497 /* disable trigger */
498 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
499 val |= TRIG_DIS;
500 ext_write(0, master, PAGE4, PTP_CTL, val);
501
502 /*
503 * read out and correct offsets
504 */
505 val = ext_read(master, PAGE4, PTP_STS);
506 pr_info("master PTP_STS 0x%04hx", val);
507 val = ext_read(master, PAGE4, PTP_ESTS);
508 pr_info("master PTP_ESTS 0x%04hx", val);
509 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
510 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
511 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
512 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
513 now = phy2txts(&event_ts);
514
515 list_for_each(this, &clock->phylist) {
516 tmp = list_entry(this, struct dp83640_private, list);
517 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
518 pr_info("slave PTP_STS 0x%04hx", val);
519 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
520 pr_info("slave PTP_ESTS 0x%04hx", val);
521 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
522 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
523 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
524 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
525 diff = now - (s64) phy2txts(&event_ts);
526 pr_info("slave offset %lld nanoseconds\n", diff);
527 diff += ADJTIME_FIX;
528 ts = ns_to_timespec(diff);
529 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
530 }
531
532 /*
533 * restore status frames
534 */
535 list_for_each(this, &clock->phylist) {
536 tmp = list_entry(this, struct dp83640_private, list);
537 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
538 }
539 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
540
541 mutex_unlock(&clock->extreg_lock);
542}
543
544/* time stamping methods */
545
546static int decode_evnt(struct dp83640_private *dp83640,
547 void *data, u16 ests)
548{
549 struct phy_txts *phy_txts;
550 struct ptp_clock_event event;
551 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
552 u16 ext_status = 0;
553
554 if (ests & MULT_EVNT) {
555 ext_status = *(u16 *) data;
556 data += sizeof(ext_status);
557 }
558
559 phy_txts = data;
560
561 switch (words) { /* fall through in every case */
562 case 3:
563 dp83640->edata.sec_hi = phy_txts->sec_hi;
564 case 2:
565 dp83640->edata.sec_lo = phy_txts->sec_lo;
566 case 1:
567 dp83640->edata.ns_hi = phy_txts->ns_hi;
568 case 0:
569 dp83640->edata.ns_lo = phy_txts->ns_lo;
570 }
571
572 event.type = PTP_CLOCK_EXTTS;
573 event.index = 0;
574 event.timestamp = phy2txts(&dp83640->edata);
575
576 ptp_clock_event(dp83640->clock->ptp_clock, &event);
577
578 words = ext_status ? words + 2 : words + 1;
579 return words * sizeof(u16);
580}
581
582static void decode_rxts(struct dp83640_private *dp83640,
583 struct phy_rxts *phy_rxts)
584{
585 struct rxts *rxts;
586 unsigned long flags;
587
588 spin_lock_irqsave(&dp83640->rx_lock, flags);
589
590 prune_rx_ts(dp83640);
591
592 if (list_empty(&dp83640->rxpool)) {
593 pr_warning("dp83640: rx timestamp pool is empty\n");
594 goto out;
595 }
596 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
597 list_del_init(&rxts->list);
598 phy2rxts(phy_rxts, rxts);
599 list_add_tail(&rxts->list, &dp83640->rxts);
600out:
601 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
602}
603
604static void decode_txts(struct dp83640_private *dp83640,
605 struct phy_txts *phy_txts)
606{
607 struct skb_shared_hwtstamps shhwtstamps;
608 struct sk_buff *skb;
609 u64 ns;
610
611 /* We must already have the skb that triggered this. */
612
613 skb = skb_dequeue(&dp83640->tx_queue);
614
615 if (!skb) {
616 pr_warning("dp83640: have timestamp but tx_queue empty\n");
617 return;
618 }
619 ns = phy2txts(phy_txts);
620 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
621 shhwtstamps.hwtstamp = ns_to_ktime(ns);
622 skb_complete_tx_timestamp(skb, &shhwtstamps);
623}
624
625static void decode_status_frame(struct dp83640_private *dp83640,
626 struct sk_buff *skb)
627{
628 struct phy_rxts *phy_rxts;
629 struct phy_txts *phy_txts;
630 u8 *ptr;
631 int len, size;
632 u16 ests, type;
633
634 ptr = skb->data + 2;
635
636 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
637
638 type = *(u16 *)ptr;
639 ests = type & 0x0fff;
640 type = type & 0xf000;
641 len -= sizeof(type);
642 ptr += sizeof(type);
643
644 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
645
646 phy_rxts = (struct phy_rxts *) ptr;
647 decode_rxts(dp83640, phy_rxts);
648 size = sizeof(*phy_rxts);
649
650 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
651
652 phy_txts = (struct phy_txts *) ptr;
653 decode_txts(dp83640, phy_txts);
654 size = sizeof(*phy_txts);
655
656 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
657
658 size = decode_evnt(dp83640, ptr, ests);
659
660 } else {
661 size = 0;
662 break;
663 }
664 ptr += size;
665 }
666}
667
668static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
669{
670 u16 *seqid;
671 unsigned int offset;
672 u8 *msgtype, *data = skb_mac_header(skb);
673
674 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
675
676 switch (type) {
677 case PTP_CLASS_V1_IPV4:
678 case PTP_CLASS_V2_IPV4:
679 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
680 break;
681 case PTP_CLASS_V1_IPV6:
682 case PTP_CLASS_V2_IPV6:
683 offset = OFF_PTP6;
684 break;
685 case PTP_CLASS_V2_L2:
686 offset = ETH_HLEN;
687 break;
688 case PTP_CLASS_V2_VLAN:
689 offset = ETH_HLEN + VLAN_HLEN;
690 break;
691 default:
692 return 0;
693 }
694
695 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
696 return 0;
697
698 if (unlikely(type & PTP_CLASS_V1))
699 msgtype = data + offset + OFF_PTP_CONTROL;
700 else
701 msgtype = data + offset;
702
703 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
704
705 return (rxts->msgtype == (*msgtype & 0xf) &&
706 rxts->seqid == ntohs(*seqid));
707}
708
709static void dp83640_free_clocks(void)
710{
711 struct dp83640_clock *clock;
712 struct list_head *this, *next;
713
714 mutex_lock(&phyter_clocks_lock);
715
716 list_for_each_safe(this, next, &phyter_clocks) {
717 clock = list_entry(this, struct dp83640_clock, list);
718 if (!list_empty(&clock->phylist)) {
719 pr_warning("phy list non-empty while unloading");
720 BUG();
721 }
722 list_del(&clock->list);
723 mutex_destroy(&clock->extreg_lock);
724 mutex_destroy(&clock->clock_lock);
725 put_device(&clock->bus->dev);
726 kfree(clock);
727 }
728
729 mutex_unlock(&phyter_clocks_lock);
730}
731
732static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
733{
734 INIT_LIST_HEAD(&clock->list);
735 clock->bus = bus;
736 mutex_init(&clock->extreg_lock);
737 mutex_init(&clock->clock_lock);
738 INIT_LIST_HEAD(&clock->phylist);
739 clock->caps.owner = THIS_MODULE;
740 sprintf(clock->caps.name, "dp83640 timer");
741 clock->caps.max_adj = 1953124;
742 clock->caps.n_alarm = 0;
743 clock->caps.n_ext_ts = N_EXT_TS;
744 clock->caps.n_per_out = 0;
745 clock->caps.pps = 0;
746 clock->caps.adjfreq = ptp_dp83640_adjfreq;
747 clock->caps.adjtime = ptp_dp83640_adjtime;
748 clock->caps.gettime = ptp_dp83640_gettime;
749 clock->caps.settime = ptp_dp83640_settime;
750 clock->caps.enable = ptp_dp83640_enable;
751 /*
752 * Get a reference to this bus instance.
753 */
754 get_device(&bus->dev);
755}
756
757static int choose_this_phy(struct dp83640_clock *clock,
758 struct phy_device *phydev)
759{
760 if (chosen_phy == -1 && !clock->chosen)
761 return 1;
762
763 if (chosen_phy == phydev->addr)
764 return 1;
765
766 return 0;
767}
768
769static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
770{
771 if (clock)
772 mutex_lock(&clock->clock_lock);
773 return clock;
774}
775
776/*
777 * Look up and lock a clock by bus instance.
778 * If there is no clock for this bus, then create it first.
779 */
780static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
781{
782 struct dp83640_clock *clock = NULL, *tmp;
783 struct list_head *this;
784
785 mutex_lock(&phyter_clocks_lock);
786
787 list_for_each(this, &phyter_clocks) {
788 tmp = list_entry(this, struct dp83640_clock, list);
789 if (tmp->bus == bus) {
790 clock = tmp;
791 break;
792 }
793 }
794 if (clock)
795 goto out;
796
797 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
798 if (!clock)
799 goto out;
800
801 dp83640_clock_init(clock, bus);
802 list_add_tail(&phyter_clocks, &clock->list);
803out:
804 mutex_unlock(&phyter_clocks_lock);
805
806 return dp83640_clock_get(clock);
807}
808
809static void dp83640_clock_put(struct dp83640_clock *clock)
810{
811 mutex_unlock(&clock->clock_lock);
812}
813
814static int dp83640_probe(struct phy_device *phydev)
815{
816 struct dp83640_clock *clock;
817 struct dp83640_private *dp83640;
818 int err = -ENOMEM, i;
819
820 if (phydev->addr == BROADCAST_ADDR)
821 return 0;
822
823 clock = dp83640_clock_get_bus(phydev->bus);
824 if (!clock)
825 goto no_clock;
826
827 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
828 if (!dp83640)
829 goto no_memory;
830
831 dp83640->phydev = phydev;
832 INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
833
834 INIT_LIST_HEAD(&dp83640->rxts);
835 INIT_LIST_HEAD(&dp83640->rxpool);
836 for (i = 0; i < MAX_RXTS; i++)
837 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
838
839 phydev->priv = dp83640;
840
841 spin_lock_init(&dp83640->rx_lock);
842 skb_queue_head_init(&dp83640->rx_queue);
843 skb_queue_head_init(&dp83640->tx_queue);
844
845 dp83640->clock = clock;
846
847 if (choose_this_phy(clock, phydev)) {
848 clock->chosen = dp83640;
849 clock->ptp_clock = ptp_clock_register(&clock->caps);
850 if (IS_ERR(clock->ptp_clock)) {
851 err = PTR_ERR(clock->ptp_clock);
852 goto no_register;
853 }
854 } else
855 list_add_tail(&dp83640->list, &clock->phylist);
856
857 if (clock->chosen && !list_empty(&clock->phylist))
858 recalibrate(clock);
859 else
860 enable_broadcast(dp83640->phydev, clock->page, 1);
861
862 dp83640_clock_put(clock);
863 return 0;
864
865no_register:
866 clock->chosen = NULL;
867 kfree(dp83640);
868no_memory:
869 dp83640_clock_put(clock);
870no_clock:
871 return err;
872}
873
874static void dp83640_remove(struct phy_device *phydev)
875{
876 struct dp83640_clock *clock;
877 struct list_head *this, *next;
878 struct dp83640_private *tmp, *dp83640 = phydev->priv;
879
880 if (phydev->addr == BROADCAST_ADDR)
881 return;
882
883 enable_status_frames(phydev, false);
884 cancel_work_sync(&dp83640->ts_work);
885
886 clock = dp83640_clock_get(dp83640->clock);
887
888 if (dp83640 == clock->chosen) {
889 ptp_clock_unregister(clock->ptp_clock);
890 clock->chosen = NULL;
891 } else {
892 list_for_each_safe(this, next, &clock->phylist) {
893 tmp = list_entry(this, struct dp83640_private, list);
894 if (tmp == dp83640) {
895 list_del_init(&tmp->list);
896 break;
897 }
898 }
899 }
900
901 dp83640_clock_put(clock);
902 kfree(dp83640);
903}
904
905static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
906{
907 struct dp83640_private *dp83640 = phydev->priv;
908 struct hwtstamp_config cfg;
909 u16 txcfg0, rxcfg0;
910
911 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
912 return -EFAULT;
913
914 if (cfg.flags) /* reserved for future extensions */
915 return -EINVAL;
916
917 switch (cfg.tx_type) {
918 case HWTSTAMP_TX_OFF:
919 dp83640->hwts_tx_en = 0;
920 break;
921 case HWTSTAMP_TX_ON:
922 dp83640->hwts_tx_en = 1;
923 break;
924 default:
925 return -ERANGE;
926 }
927
928 switch (cfg.rx_filter) {
929 case HWTSTAMP_FILTER_NONE:
930 dp83640->hwts_rx_en = 0;
931 dp83640->layer = 0;
932 dp83640->version = 0;
933 break;
934 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
935 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
936 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
937 dp83640->hwts_rx_en = 1;
938 dp83640->layer = LAYER4;
939 dp83640->version = 1;
940 break;
941 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
942 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
943 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
944 dp83640->hwts_rx_en = 1;
945 dp83640->layer = LAYER4;
946 dp83640->version = 2;
947 break;
948 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
949 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
950 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
951 dp83640->hwts_rx_en = 1;
952 dp83640->layer = LAYER2;
953 dp83640->version = 2;
954 break;
955 case HWTSTAMP_FILTER_PTP_V2_EVENT:
956 case HWTSTAMP_FILTER_PTP_V2_SYNC:
957 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
958 dp83640->hwts_rx_en = 1;
959 dp83640->layer = LAYER4|LAYER2;
960 dp83640->version = 2;
961 break;
962 default:
963 return -ERANGE;
964 }
965
966 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
967 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
968
969 if (dp83640->layer & LAYER2) {
970 txcfg0 |= TX_L2_EN;
971 rxcfg0 |= RX_L2_EN;
972 }
973 if (dp83640->layer & LAYER4) {
974 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
975 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
976 }
977
978 if (dp83640->hwts_tx_en)
979 txcfg0 |= TX_TS_EN;
980
981 if (dp83640->hwts_rx_en)
982 rxcfg0 |= RX_TS_EN;
983
984 mutex_lock(&dp83640->clock->extreg_lock);
985
986 if (dp83640->hwts_tx_en || dp83640->hwts_rx_en) {
987 enable_status_frames(phydev, true);
988 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
989 }
990
991 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
992 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
993
994 mutex_unlock(&dp83640->clock->extreg_lock);
995
996 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
997}
998
999static void rx_timestamp_work(struct work_struct *work)
1000{
1001 struct dp83640_private *dp83640 =
1002 container_of(work, struct dp83640_private, ts_work);
1003 struct list_head *this, *next;
1004 struct rxts *rxts;
1005 struct skb_shared_hwtstamps *shhwtstamps;
1006 struct sk_buff *skb;
1007 unsigned int type;
1008 unsigned long flags;
1009
1010 /* Deliver each deferred packet, with or without a time stamp. */
1011
1012 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
1013 type = SKB_PTP_TYPE(skb);
1014 spin_lock_irqsave(&dp83640->rx_lock, flags);
1015 list_for_each_safe(this, next, &dp83640->rxts) {
1016 rxts = list_entry(this, struct rxts, list);
1017 if (match(skb, type, rxts)) {
1018 shhwtstamps = skb_hwtstamps(skb);
1019 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1020 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1021 list_del_init(&rxts->list);
1022 list_add(&rxts->list, &dp83640->rxpool);
1023 break;
1024 }
1025 }
1026 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1027 netif_rx(skb);
1028 }
1029
1030 /* Clear out expired time stamps. */
1031
1032 spin_lock_irqsave(&dp83640->rx_lock, flags);
1033 prune_rx_ts(dp83640);
1034 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1035}
1036
1037static bool dp83640_rxtstamp(struct phy_device *phydev,
1038 struct sk_buff *skb, int type)
1039{
1040 struct dp83640_private *dp83640 = phydev->priv;
1041
1042 if (!dp83640->hwts_rx_en)
1043 return false;
1044
1045 if (is_status_frame(skb, type)) {
1046 decode_status_frame(dp83640, skb);
1047 kfree_skb(skb);
1048 return true;
1049 }
1050
1051 SKB_PTP_TYPE(skb) = type;
1052 skb_queue_tail(&dp83640->rx_queue, skb);
1053 schedule_work(&dp83640->ts_work);
1054
1055 return true;
1056}
1057
1058static void dp83640_txtstamp(struct phy_device *phydev,
1059 struct sk_buff *skb, int type)
1060{
1061 struct dp83640_private *dp83640 = phydev->priv;
1062
1063 if (!dp83640->hwts_tx_en) {
1064 kfree_skb(skb);
1065 return;
1066 }
1067 skb_queue_tail(&dp83640->tx_queue, skb);
1068 schedule_work(&dp83640->ts_work);
1069}
1070
1071static struct phy_driver dp83640_driver = {
1072 .phy_id = DP83640_PHY_ID,
1073 .phy_id_mask = 0xfffffff0,
1074 .name = "NatSemi DP83640",
1075 .features = PHY_BASIC_FEATURES,
1076 .flags = 0,
1077 .probe = dp83640_probe,
1078 .remove = dp83640_remove,
1079 .config_aneg = genphy_config_aneg,
1080 .read_status = genphy_read_status,
1081 .hwtstamp = dp83640_hwtstamp,
1082 .rxtstamp = dp83640_rxtstamp,
1083 .txtstamp = dp83640_txtstamp,
1084 .driver = {.owner = THIS_MODULE,}
1085};
1086
1087static int __init dp83640_init(void)
1088{
1089 return phy_driver_register(&dp83640_driver);
1090}
1091
1092static void __exit dp83640_exit(void)
1093{
1094 dp83640_free_clocks();
1095 phy_driver_unregister(&dp83640_driver);
1096}
1097
1098MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1099MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
1100MODULE_LICENSE("GPL");
1101
1102module_init(dp83640_init);
1103module_exit(dp83640_exit);
1104
1105static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1106 { DP83640_PHY_ID, 0xfffffff0 },
1107 { }
1108};
1109
1110MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h
new file mode 100644
index 000000000000..e7fe41117003
--- /dev/null
+++ b/drivers/net/phy/dp83640_reg.h
@@ -0,0 +1,267 @@
1/* dp83640_reg.h
2 * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011
3 */
4#ifndef HAVE_DP83640_REGISTERS
5#define HAVE_DP83640_REGISTERS
6
7#define PAGE0 0x0000
8#define PHYCR2 0x001c /* PHY Control Register 2 */
9
10#define PAGE4 0x0004
11#define PTP_CTL 0x0014 /* PTP Control Register */
12#define PTP_TDR 0x0015 /* PTP Time Data Register */
13#define PTP_STS 0x0016 /* PTP Status Register */
14#define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
15#define PTP_RATEL 0x0018 /* PTP Rate Low Register */
16#define PTP_RATEH 0x0019 /* PTP Rate High Register */
17#define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
18#define PTP_WRCKSUM 0x001b /* PTP Write Checksum */
19#define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
20#define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
21#define PTP_ESTS 0x001e /* PTP Event Status Register */
22#define PTP_EDATA 0x001f /* PTP Event Data Register */
23
24#define PAGE5 0x0005
25#define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
26#define PTP_EVNT 0x0015 /* PTP Event Configuration Register */
27#define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */
28#define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */
29#define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
30#define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */
31#define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */
32#define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */
33#define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */
34#define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */
35#define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
36#define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
37
38#define PAGE6 0x0006
39#define PTP_COC 0x0014 /* PTP Clock Output Control Register */
40#define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
41#define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
42#define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
43#define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */
44#define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */
45#define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */
46#define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
47#define PTP_ETR 0x001c /* PTP Ethernet Type Register */
48#define PTP_OFF 0x001d /* PTP Offset Register */
49#define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */
50#define PTP_RXHASH 0x001f /* PTP Receive Hash Register */
51
52/* Bit definitions for the PHYCR2 register */
53#define BC_WRITE (1<<11) /* Broadcast Write Enable */
54
55/* Bit definitions for the PTP_CTL register */
56#define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
57#define TRIG_SEL_MASK (0x7)
58#define TRIG_DIS (1<<9) /* Disable PTP Trigger */
59#define TRIG_EN (1<<8) /* Enable PTP Trigger */
60#define TRIG_READ (1<<7) /* Read PTP Trigger */
61#define TRIG_LOAD (1<<6) /* Load PTP Trigger */
62#define PTP_RD_CLK (1<<5) /* Read PTP Clock */
63#define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */
64#define PTP_STEP_CLK (1<<3) /* Step PTP Clock */
65#define PTP_ENABLE (1<<2) /* Enable PTP Clock */
66#define PTP_DISABLE (1<<1) /* Disable PTP Clock */
67#define PTP_RESET (1<<0) /* Reset PTP Clock */
68
69/* Bit definitions for the PTP_STS register */
70#define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */
71#define RXTS_RDY (1<<10) /* Receive Timestamp Ready */
72#define TRIG_DONE (1<<9) /* PTP Trigger Done */
73#define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */
74#define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
75#define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
76#define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
77#define EVENT_IE (1<<0) /* Event Interrupt Enable */
78
79/* Bit definitions for the PTP_TSTS register */
80#define TRIG7_ERROR (1<<15) /* Trigger 7 Error */
81#define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
82#define TRIG6_ERROR (1<<13) /* Trigger 6 Error */
83#define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */
84#define TRIG5_ERROR (1<<11) /* Trigger 5 Error */
85#define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */
86#define TRIG4_ERROR (1<<9) /* Trigger 4 Error */
87#define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */
88#define TRIG3_ERROR (1<<7) /* Trigger 3 Error */
89#define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */
90#define TRIG2_ERROR (1<<5) /* Trigger 2 Error */
91#define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */
92#define TRIG1_ERROR (1<<3) /* Trigger 1 Error */
93#define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */
94#define TRIG0_ERROR (1<<1) /* Trigger 0 Error */
95#define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
96
97/* Bit definitions for the PTP_RATEH register */
98#define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */
99#define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */
100#define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
101#define PTP_RATE_HI_MASK (0x3ff)
102
103/* Bit definitions for the PTP_ESTS register */
104#define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */
105#define EVNTS_MISSED_MASK (0x7)
106#define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */
107#define EVNT_TS_LEN_MASK (0x3)
108#define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */
109#define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */
110#define EVNT_NUM_MASK (0x7)
111#define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */
112#define EVENT_DET (1<<0) /* PTP Event Detected */
113
114/* Bit definitions for the PTP_EDATA register */
115#define E7_RISE (1<<15) /* Indicates direction of Event 7 */
116#define E7_DET (1<<14) /* Indicates Event 7 detected */
117#define E6_RISE (1<<13) /* Indicates direction of Event 6 */
118#define E6_DET (1<<12) /* Indicates Event 6 detected */
119#define E5_RISE (1<<11) /* Indicates direction of Event 5 */
120#define E5_DET (1<<10) /* Indicates Event 5 detected */
121#define E4_RISE (1<<9) /* Indicates direction of Event 4 */
122#define E4_DET (1<<8) /* Indicates Event 4 detected */
123#define E3_RISE (1<<7) /* Indicates direction of Event 3 */
124#define E3_DET (1<<6) /* Indicates Event 3 detected */
125#define E2_RISE (1<<5) /* Indicates direction of Event 2 */
126#define E2_DET (1<<4) /* Indicates Event 2 detected */
127#define E1_RISE (1<<3) /* Indicates direction of Event 1 */
128#define E1_DET (1<<2) /* Indicates Event 1 detected */
129#define E0_RISE (1<<1) /* Indicates direction of Event 0 */
130#define E0_DET (1<<0) /* Indicates Event 0 detected */
131
132/* Bit definitions for the PTP_TRIG register */
133#define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */
134#define TRIG_PER (1<<14) /* generate a periodic signal */
135#define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */
136#define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */
137#define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */
138#define TRIG_GPIO_MASK (0xf)
139#define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
140#define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */
141#define TRIG_CSEL_MASK (0x7)
142#define TRIG_WR (1<<0) /* Trigger Configuration Write */
143
144/* Bit definitions for the PTP_EVNT register */
145#define EVNT_RISE (1<<14) /* Event Rise Detect Enable */
146#define EVNT_FALL (1<<13) /* Event Fall Detect Enable */
147#define EVNT_SINGLE (1<<12) /* enable single event capture operation */
148#define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */
149#define EVNT_GPIO_MASK (0xf)
150#define EVNT_SEL_SHIFT (1) /* Event Select */
151#define EVNT_SEL_MASK (0x7)
152#define EVNT_WR (1<<0) /* Event Configuration Write */
153
154/* Bit definitions for the PTP_TXCFG0 register */
155#define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */
156#define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */
157#define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */
158#define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */
159#define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */
160#define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */
161#define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */
162#define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
163#define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
164#define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
165#define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
166#define TX_PTP_VER_MASK (0xf)
167#define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
168
169/* Bit definitions for the PTP_TXCFG1 register */
170#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
171#define BYTE0_MASK_MASK (0xff)
172#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
173#define BYTE0_DATA_MASK (0xff)
174
175/* Bit definitions for the PSF_CFG0 register */
176#define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */
177#define MAC_SRC_ADD_MASK (0x3)
178#define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */
179#define MIN_PRE_MASK (0x7)
180#define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */
181#define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */
182#define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */
183#define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */
184#define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */
185#define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */
186#define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */
187#define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
188
189/* Bit definitions for the PTP_RXCFG0 register */
190#define DOMAIN_EN (1<<15) /* Domain Match Enable */
191#define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */
192#define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */
193#define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */
194#define RX_SLAVE (1<<11) /* Receive Slave Only */
195#define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */
196#define IP1588_EN_MASK (0xf)
197#define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
198#define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
199#define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
200#define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
201#define RX_PTP_VER_MASK (0xf)
202#define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
203
204/* Bit definitions for the PTP_RXCFG1 register */
205#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
206#define BYTE0_MASK_MASK (0xff)
207#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
208#define BYTE0_DATA_MASK (0xff)
209
210/* Bit definitions for the PTP_RXCFG3 register */
211#define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */
212#define TS_MIN_IFG_MASK (0xf)
213#define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */
214#define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */
215#define TS_APPEND (1<<9) /* Append Timestamp for L2 */
216#define TS_INSERT (1<<8) /* Enable Timestamp Insertion */
217#define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */
218#define PTP_DOMAIN_MASK (0xff)
219
220/* Bit definitions for the PTP_RXCFG4 register */
221#define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */
222#define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */
223#define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */
224#define TS_SEC_LEN_MASK (0x3)
225#define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */
226#define RXTS_NS_OFF_MASK (0x3f)
227#define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */
228#define RXTS_SEC_OFF_MASK (0x3f)
229
230/* Bit definitions for the PTP_COC register */
231#define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
232#define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
233#define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
234#define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
235#define PTP_CLKDIV_MASK (0xff)
236
237/* Bit definitions for the PSF_CFG1 register */
238#define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */
239#define PTPRESERVED_MASK (0xf)
240#define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */
241#define VERSIONPTP_MASK (0xf)
242#define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */
243#define TRANSPORT_SPECIFIC_MASK (0xf)
244#define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */
245#define MESSAGETYPE_MASK (0xf)
246
247/* Bit definitions for the PTP_SFDCFG register */
248#define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */
249#define TX_SFD_GPIO_MASK (0xf)
250#define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */
251#define RX_SFD_GPIO_MASK (0xf)
252
253/* Bit definitions for the PTP_INTCTL register */
254#define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */
255#define PTP_INT_GPIO_MASK (0xf)
256
257/* Bit definitions for the PTP_CLKSRC register */
258#define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */
259#define CLK_SRC_MASK (0x3)
260#define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
261#define CLK_SRC_PER_MASK (0x7f)
262
263/* Bit definitions for the PTP_OFF register */
264#define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */
265#define PTP_OFFSET_MASK (0xff)
266
267#endif
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
index 13995f52d6af..a8eb19ec3183 100644
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -111,7 +111,7 @@ static void __exit et1011c_exit(void)
111module_init(et1011c_init); 111module_init(et1011c_init);
112module_exit(et1011c_exit); 112module_exit(et1011c_exit);
113 113
114static struct mdio_device_id et1011c_tbl[] = { 114static struct mdio_device_id __maybe_unused et1011c_tbl[] = {
115 { 0x0282f014, 0xfffffff0 }, 115 { 0x0282f014, 0xfffffff0 },
116 { } 116 { }
117}; 117};
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index 3f2583f18a39..9a09e24c30bc 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -30,7 +30,7 @@
30#include <asm/irq.h> 30#include <asm/irq.h>
31#include <asm/uaccess.h> 31#include <asm/uaccess.h>
32 32
33MODULE_DESCRIPTION("ICPlus IP175C PHY driver"); 33MODULE_DESCRIPTION("ICPlus IP175C/IC1001 PHY drivers");
34MODULE_AUTHOR("Michael Barkowski"); 34MODULE_AUTHOR("Michael Barkowski");
35MODULE_LICENSE("GPL"); 35MODULE_LICENSE("GPL");
36 36
@@ -89,6 +89,33 @@ static int ip175c_config_init(struct phy_device *phydev)
89 return 0; 89 return 0;
90} 90}
91 91
92static int ip1001_config_init(struct phy_device *phydev)
93{
94 int err, value;
95
96 /* Software Reset PHY */
97 value = phy_read(phydev, MII_BMCR);
98 value |= BMCR_RESET;
99 err = phy_write(phydev, MII_BMCR, value);
100 if (err < 0)
101 return err;
102
103 do {
104 value = phy_read(phydev, MII_BMCR);
105 } while (value & BMCR_RESET);
106
107 /* Additional delay (2ns) used to adjust RX clock phase
108 * at GMII/ RGMII interface */
109 value = phy_read(phydev, 16);
110 value |= 0x3;
111
112 err = phy_write(phydev, 16, value);
113 if (err < 0)
114 return err;
115
116 return err;
117}
118
92static int ip175c_read_status(struct phy_device *phydev) 119static int ip175c_read_status(struct phy_device *phydev)
93{ 120{
94 if (phydev->addr == 4) /* WAN port */ 121 if (phydev->addr == 4) /* WAN port */
@@ -121,21 +148,43 @@ static struct phy_driver ip175c_driver = {
121 .driver = { .owner = THIS_MODULE,}, 148 .driver = { .owner = THIS_MODULE,},
122}; 149};
123 150
124static int __init ip175c_init(void) 151static struct phy_driver ip1001_driver = {
152 .phy_id = 0x02430d90,
153 .name = "ICPlus IP1001",
154 .phy_id_mask = 0x0ffffff0,
155 .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
156 SUPPORTED_Asym_Pause,
157 .config_init = &ip1001_config_init,
158 .config_aneg = &genphy_config_aneg,
159 .read_status = &genphy_read_status,
160 .suspend = genphy_suspend,
161 .resume = genphy_resume,
162 .driver = { .owner = THIS_MODULE,},
163};
164
165static int __init icplus_init(void)
125{ 166{
167 int ret = 0;
168
169 ret = phy_driver_register(&ip1001_driver);
170 if (ret < 0)
171 return -ENODEV;
172
126 return phy_driver_register(&ip175c_driver); 173 return phy_driver_register(&ip175c_driver);
127} 174}
128 175
129static void __exit ip175c_exit(void) 176static void __exit icplus_exit(void)
130{ 177{
178 phy_driver_unregister(&ip1001_driver);
131 phy_driver_unregister(&ip175c_driver); 179 phy_driver_unregister(&ip175c_driver);
132} 180}
133 181
134module_init(ip175c_init); 182module_init(icplus_init);
135module_exit(ip175c_exit); 183module_exit(icplus_exit);
136 184
137static struct mdio_device_id icplus_tbl[] = { 185static struct mdio_device_id __maybe_unused icplus_tbl[] = {
138 { 0x02430d80, 0x0ffffff0 }, 186 { 0x02430d80, 0x0ffffff0 },
187 { 0x02430d90, 0x0ffffff0 },
139 { } 188 { }
140}; 189};
141 190
diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c
index 29c39ff85de5..6f6e8b616a62 100644
--- a/drivers/net/phy/lxt.c
+++ b/drivers/net/phy/lxt.c
@@ -223,7 +223,7 @@ static void __exit lxt_exit(void)
223module_init(lxt_init); 223module_init(lxt_init);
224module_exit(lxt_exit); 224module_exit(lxt_exit);
225 225
226static struct mdio_device_id lxt_tbl[] = { 226static struct mdio_device_id __maybe_unused lxt_tbl[] = {
227 { 0x78100000, 0xfffffff0 }, 227 { 0x78100000, 0xfffffff0 },
228 { 0x001378e0, 0xfffffff0 }, 228 { 0x001378e0, 0xfffffff0 },
229 { 0x00137a10, 0xfffffff0 }, 229 { 0x00137a10, 0xfffffff0 },
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 0101f2bdf400..e8b9c53c304b 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -30,11 +30,14 @@
30#include <linux/ethtool.h> 30#include <linux/ethtool.h>
31#include <linux/phy.h> 31#include <linux/phy.h>
32#include <linux/marvell_phy.h> 32#include <linux/marvell_phy.h>
33#include <linux/of.h>
33 34
34#include <asm/io.h> 35#include <asm/io.h>
35#include <asm/irq.h> 36#include <asm/irq.h>
36#include <asm/uaccess.h> 37#include <asm/uaccess.h>
37 38
39#define MII_MARVELL_PHY_PAGE 22
40
38#define MII_M1011_IEVENT 0x13 41#define MII_M1011_IEVENT 0x13
39#define MII_M1011_IEVENT_CLEAR 0x0000 42#define MII_M1011_IEVENT_CLEAR 0x0000
40 43
@@ -74,13 +77,12 @@
74#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4) 77#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
75#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4)) 78#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
76 79
77#define MII_88EC048_PHY_MSCR1_REG 16 80#define MII_88E1318S_PHY_MSCR1_REG 16
78#define MII_88EC048_PHY_MSCR1_PAD_ODD BIT(6) 81#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
79 82
80#define MII_88E1121_PHY_LED_CTRL 16 83#define MII_88E1121_PHY_LED_CTRL 16
81#define MII_88E1121_PHY_LED_PAGE 3 84#define MII_88E1121_PHY_LED_PAGE 3
82#define MII_88E1121_PHY_LED_DEF 0x0030 85#define MII_88E1121_PHY_LED_DEF 0x0030
83#define MII_88E1121_PHY_PAGE 22
84 86
85#define MII_M1011_PHY_STATUS 0x11 87#define MII_M1011_PHY_STATUS 0x11
86#define MII_M1011_PHY_STATUS_1000 0x8000 88#define MII_M1011_PHY_STATUS_1000 0x8000
@@ -186,32 +188,120 @@ static int marvell_config_aneg(struct phy_device *phydev)
186 return 0; 188 return 0;
187} 189}
188 190
191#ifdef CONFIG_OF_MDIO
192/*
193 * Set and/or override some configuration registers based on the
194 * marvell,reg-init property stored in the of_node for the phydev.
195 *
196 * marvell,reg-init = <reg-page reg mask value>,...;
197 *
198 * There may be one or more sets of <reg-page reg mask value>:
199 *
200 * reg-page: which register bank to use.
201 * reg: the register.
202 * mask: if non-zero, ANDed with existing register value.
203 * value: ORed with the masked value and written to the regiser.
204 *
205 */
206static int marvell_of_reg_init(struct phy_device *phydev)
207{
208 const __be32 *paddr;
209 int len, i, saved_page, current_page, page_changed, ret;
210
211 if (!phydev->dev.of_node)
212 return 0;
213
214 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
215 if (!paddr || len < (4 * sizeof(*paddr)))
216 return 0;
217
218 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
219 if (saved_page < 0)
220 return saved_page;
221 page_changed = 0;
222 current_page = saved_page;
223
224 ret = 0;
225 len /= sizeof(*paddr);
226 for (i = 0; i < len - 3; i += 4) {
227 u16 reg_page = be32_to_cpup(paddr + i);
228 u16 reg = be32_to_cpup(paddr + i + 1);
229 u16 mask = be32_to_cpup(paddr + i + 2);
230 u16 val_bits = be32_to_cpup(paddr + i + 3);
231 int val;
232
233 if (reg_page != current_page) {
234 current_page = reg_page;
235 page_changed = 1;
236 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
237 if (ret < 0)
238 goto err;
239 }
240
241 val = 0;
242 if (mask) {
243 val = phy_read(phydev, reg);
244 if (val < 0) {
245 ret = val;
246 goto err;
247 }
248 val &= mask;
249 }
250 val |= val_bits;
251
252 ret = phy_write(phydev, reg, val);
253 if (ret < 0)
254 goto err;
255
256 }
257err:
258 if (page_changed) {
259 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
260 if (ret == 0)
261 ret = i;
262 }
263 return ret;
264}
265#else
266static int marvell_of_reg_init(struct phy_device *phydev)
267{
268 return 0;
269}
270#endif /* CONFIG_OF_MDIO */
271
189static int m88e1121_config_aneg(struct phy_device *phydev) 272static int m88e1121_config_aneg(struct phy_device *phydev)
190{ 273{
191 int err, oldpage, mscr; 274 int err, oldpage, mscr;
192 275
193 oldpage = phy_read(phydev, MII_88E1121_PHY_PAGE); 276 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
194 277
195 err = phy_write(phydev, MII_88E1121_PHY_PAGE, 278 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
196 MII_88E1121_PHY_MSCR_PAGE); 279 MII_88E1121_PHY_MSCR_PAGE);
197 if (err < 0) 280 if (err < 0)
198 return err; 281 return err;
199 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
200 MII_88E1121_PHY_MSCR_DELAY_MASK;
201 282
202 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 283 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
203 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY | 284 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
204 MII_88E1121_PHY_MSCR_TX_DELAY); 285 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
205 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 286 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
206 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
207 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
208 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
209 287
210 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); 288 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
211 if (err < 0) 289 MII_88E1121_PHY_MSCR_DELAY_MASK;
212 return err; 290
291 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
292 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
293 MII_88E1121_PHY_MSCR_TX_DELAY);
294 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
295 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
296 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
297 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
298
299 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
300 if (err < 0)
301 return err;
302 }
213 303
214 phy_write(phydev, MII_88E1121_PHY_PAGE, oldpage); 304 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
215 305
216 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 306 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
217 if (err < 0) 307 if (err < 0)
@@ -222,36 +312,36 @@ static int m88e1121_config_aneg(struct phy_device *phydev)
222 if (err < 0) 312 if (err < 0)
223 return err; 313 return err;
224 314
225 oldpage = phy_read(phydev, MII_88E1121_PHY_PAGE); 315 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
226 316
227 phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); 317 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
228 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF); 318 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
229 phy_write(phydev, MII_88E1121_PHY_PAGE, oldpage); 319 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
230 320
231 err = genphy_config_aneg(phydev); 321 err = genphy_config_aneg(phydev);
232 322
233 return err; 323 return err;
234} 324}
235 325
236static int m88ec048_config_aneg(struct phy_device *phydev) 326static int m88e1318_config_aneg(struct phy_device *phydev)
237{ 327{
238 int err, oldpage, mscr; 328 int err, oldpage, mscr;
239 329
240 oldpage = phy_read(phydev, MII_88E1121_PHY_PAGE); 330 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
241 331
242 err = phy_write(phydev, MII_88E1121_PHY_PAGE, 332 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
243 MII_88E1121_PHY_MSCR_PAGE); 333 MII_88E1121_PHY_MSCR_PAGE);
244 if (err < 0) 334 if (err < 0)
245 return err; 335 return err;
246 336
247 mscr = phy_read(phydev, MII_88EC048_PHY_MSCR1_REG); 337 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
248 mscr |= MII_88EC048_PHY_MSCR1_PAD_ODD; 338 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
249 339
250 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); 340 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
251 if (err < 0) 341 if (err < 0)
252 return err; 342 return err;
253 343
254 err = phy_write(phydev, MII_88E1121_PHY_PAGE, oldpage); 344 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
255 if (err < 0) 345 if (err < 0)
256 return err; 346 return err;
257 347
@@ -361,6 +451,9 @@ static int m88e1111_config_init(struct phy_device *phydev)
361 return err; 451 return err;
362 } 452 }
363 453
454 err = marvell_of_reg_init(phydev);
455 if (err < 0)
456 return err;
364 457
365 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 458 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
366 if (err < 0) 459 if (err < 0)
@@ -391,7 +484,7 @@ static int m88e1118_config_init(struct phy_device *phydev)
391 int err; 484 int err;
392 485
393 /* Change address */ 486 /* Change address */
394 err = phy_write(phydev, 0x16, 0x0002); 487 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
395 if (err < 0) 488 if (err < 0)
396 return err; 489 return err;
397 490
@@ -401,7 +494,7 @@ static int m88e1118_config_init(struct phy_device *phydev)
401 return err; 494 return err;
402 495
403 /* Change address */ 496 /* Change address */
404 err = phy_write(phydev, 0x16, 0x0003); 497 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
405 if (err < 0) 498 if (err < 0)
406 return err; 499 return err;
407 500
@@ -413,8 +506,42 @@ static int m88e1118_config_init(struct phy_device *phydev)
413 if (err < 0) 506 if (err < 0)
414 return err; 507 return err;
415 508
509 err = marvell_of_reg_init(phydev);
510 if (err < 0)
511 return err;
512
513 /* Reset address */
514 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
515 if (err < 0)
516 return err;
517
518 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
519 if (err < 0)
520 return err;
521
522 return 0;
523}
524
525static int m88e1149_config_init(struct phy_device *phydev)
526{
527 int err;
528
529 /* Change address */
530 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
531 if (err < 0)
532 return err;
533
534 /* Enable 1000 Mbit */
535 err = phy_write(phydev, 0x15, 0x1048);
536 if (err < 0)
537 return err;
538
539 err = marvell_of_reg_init(phydev);
540 if (err < 0)
541 return err;
542
416 /* Reset address */ 543 /* Reset address */
417 err = phy_write(phydev, 0x16, 0x0); 544 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
418 if (err < 0) 545 if (err < 0)
419 return err; 546 return err;
420 547
@@ -484,6 +611,10 @@ static int m88e1145_config_init(struct phy_device *phydev)
484 } 611 }
485 } 612 }
486 613
614 err = marvell_of_reg_init(phydev);
615 if (err < 0)
616 return err;
617
487 return 0; 618 return 0;
488} 619}
489 620
@@ -652,12 +783,12 @@ static struct phy_driver marvell_drivers[] = {
652 .driver = { .owner = THIS_MODULE }, 783 .driver = { .owner = THIS_MODULE },
653 }, 784 },
654 { 785 {
655 .phy_id = MARVELL_PHY_ID_88EC048, 786 .phy_id = MARVELL_PHY_ID_88E1318S,
656 .phy_id_mask = MARVELL_PHY_ID_MASK, 787 .phy_id_mask = MARVELL_PHY_ID_MASK,
657 .name = "Marvell 88EC048", 788 .name = "Marvell 88E1318S",
658 .features = PHY_GBIT_FEATURES, 789 .features = PHY_GBIT_FEATURES,
659 .flags = PHY_HAS_INTERRUPT, 790 .flags = PHY_HAS_INTERRUPT,
660 .config_aneg = &m88ec048_config_aneg, 791 .config_aneg = &m88e1318_config_aneg,
661 .read_status = &marvell_read_status, 792 .read_status = &marvell_read_status,
662 .ack_interrupt = &marvell_ack_interrupt, 793 .ack_interrupt = &marvell_ack_interrupt,
663 .config_intr = &marvell_config_intr, 794 .config_intr = &marvell_config_intr,
@@ -678,6 +809,19 @@ static struct phy_driver marvell_drivers[] = {
678 .driver = { .owner = THIS_MODULE }, 809 .driver = { .owner = THIS_MODULE },
679 }, 810 },
680 { 811 {
812 .phy_id = MARVELL_PHY_ID_88E1149R,
813 .phy_id_mask = MARVELL_PHY_ID_MASK,
814 .name = "Marvell 88E1149R",
815 .features = PHY_GBIT_FEATURES,
816 .flags = PHY_HAS_INTERRUPT,
817 .config_init = &m88e1149_config_init,
818 .config_aneg = &m88e1118_config_aneg,
819 .read_status = &genphy_read_status,
820 .ack_interrupt = &marvell_ack_interrupt,
821 .config_intr = &marvell_config_intr,
822 .driver = { .owner = THIS_MODULE },
823 },
824 {
681 .phy_id = MARVELL_PHY_ID_88E1240, 825 .phy_id = MARVELL_PHY_ID_88E1240,
682 .phy_id_mask = MARVELL_PHY_ID_MASK, 826 .phy_id_mask = MARVELL_PHY_ID_MASK,
683 .name = "Marvell 88E1240", 827 .name = "Marvell 88E1240",
@@ -721,13 +865,14 @@ static void __exit marvell_exit(void)
721module_init(marvell_init); 865module_init(marvell_init);
722module_exit(marvell_exit); 866module_exit(marvell_exit);
723 867
724static struct mdio_device_id marvell_tbl[] = { 868static struct mdio_device_id __maybe_unused marvell_tbl[] = {
725 { 0x01410c60, 0xfffffff0 }, 869 { 0x01410c60, 0xfffffff0 },
726 { 0x01410c90, 0xfffffff0 }, 870 { 0x01410c90, 0xfffffff0 },
727 { 0x01410cc0, 0xfffffff0 }, 871 { 0x01410cc0, 0xfffffff0 },
728 { 0x01410e10, 0xfffffff0 }, 872 { 0x01410e10, 0xfffffff0 },
729 { 0x01410cb0, 0xfffffff0 }, 873 { 0x01410cb0, 0xfffffff0 },
730 { 0x01410cd0, 0xfffffff0 }, 874 { 0x01410cd0, 0xfffffff0 },
875 { 0x01410e50, 0xfffffff0 },
731 { 0x01410e30, 0xfffffff0 }, 876 { 0x01410e30, 0xfffffff0 },
732 { 0x01410e90, 0xfffffff0 }, 877 { 0x01410e90, 0xfffffff0 },
733 { } 878 { }
diff --git a/drivers/net/phy/mdio-gpio.c b/drivers/net/phy/mdio-gpio.c
index f62c7b717bc8..47c8339a0359 100644
--- a/drivers/net/phy/mdio-gpio.c
+++ b/drivers/net/phy/mdio-gpio.c
@@ -188,8 +188,7 @@ static int __devexit mdio_gpio_remove(struct platform_device *pdev)
188 188
189#ifdef CONFIG_OF_GPIO 189#ifdef CONFIG_OF_GPIO
190 190
191static int __devinit mdio_ofgpio_probe(struct platform_device *ofdev, 191static int __devinit mdio_ofgpio_probe(struct platform_device *ofdev)
192 const struct of_device_id *match)
193{ 192{
194 struct mdio_gpio_platform_data *pdata; 193 struct mdio_gpio_platform_data *pdata;
195 struct mii_bus *new_bus; 194 struct mii_bus *new_bus;
@@ -240,7 +239,7 @@ static struct of_device_id mdio_ofgpio_match[] = {
240}; 239};
241MODULE_DEVICE_TABLE(of, mdio_ofgpio_match); 240MODULE_DEVICE_TABLE(of, mdio_ofgpio_match);
242 241
243static struct of_platform_driver mdio_ofgpio_driver = { 242static struct platform_driver mdio_ofgpio_driver = {
244 .driver = { 243 .driver = {
245 .name = "mdio-gpio", 244 .name = "mdio-gpio",
246 .owner = THIS_MODULE, 245 .owner = THIS_MODULE,
@@ -252,12 +251,12 @@ static struct of_platform_driver mdio_ofgpio_driver = {
252 251
253static inline int __init mdio_ofgpio_init(void) 252static inline int __init mdio_ofgpio_init(void)
254{ 253{
255 return of_register_platform_driver(&mdio_ofgpio_driver); 254 return platform_driver_register(&mdio_ofgpio_driver);
256} 255}
257 256
258static inline void __exit mdio_ofgpio_exit(void) 257static inline void __exit mdio_ofgpio_exit(void)
259{ 258{
260 of_unregister_platform_driver(&mdio_ofgpio_driver); 259 platform_driver_unregister(&mdio_ofgpio_driver);
261} 260}
262#else 261#else
263static inline int __init mdio_ofgpio_init(void) { return 0; } 262static inline int __init mdio_ofgpio_init(void) { return 0; }
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 8bb7db676a5c..590f902deb6b 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -19,13 +19,7 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/phy.h> 21#include <linux/phy.h>
22 22#include <linux/micrel_phy.h>
23#define PHY_ID_KSZ9021 0x00221611
24#define PHY_ID_KS8737 0x00221720
25#define PHY_ID_KS8041 0x00221510
26#define PHY_ID_KS8051 0x00221550
27/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */
28#define PHY_ID_KS8001 0x0022161A
29 23
30/* general Interrupt control/status reg in vendor specific block. */ 24/* general Interrupt control/status reg in vendor specific block. */
31#define MII_KSZPHY_INTCS 0x1B 25#define MII_KSZPHY_INTCS 0x1B
@@ -46,6 +40,7 @@
46#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9) 40#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
47#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14) 41#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
48#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14) 42#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
43#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
49 44
50static int kszphy_ack_interrupt(struct phy_device *phydev) 45static int kszphy_ack_interrupt(struct phy_device *phydev)
51{ 46{
@@ -106,6 +101,19 @@ static int kszphy_config_init(struct phy_device *phydev)
106 return 0; 101 return 0;
107} 102}
108 103
104static int ks8051_config_init(struct phy_device *phydev)
105{
106 int regval;
107
108 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
109 regval = phy_read(phydev, MII_KSZPHY_CTRL);
110 regval |= KSZ8051_RMII_50MHZ_CLK;
111 phy_write(phydev, MII_KSZPHY_CTRL, regval);
112 }
113
114 return 0;
115}
116
109static struct phy_driver ks8737_driver = { 117static struct phy_driver ks8737_driver = {
110 .phy_id = PHY_ID_KS8737, 118 .phy_id = PHY_ID_KS8737,
111 .phy_id_mask = 0x00fffff0, 119 .phy_id_mask = 0x00fffff0,
@@ -142,7 +150,7 @@ static struct phy_driver ks8051_driver = {
142 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause 150 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
143 | SUPPORTED_Asym_Pause), 151 | SUPPORTED_Asym_Pause),
144 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, 152 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
145 .config_init = kszphy_config_init, 153 .config_init = ks8051_config_init,
146 .config_aneg = genphy_config_aneg, 154 .config_aneg = genphy_config_aneg,
147 .read_status = genphy_read_status, 155 .read_status = genphy_read_status,
148 .ack_interrupt = kszphy_ack_interrupt, 156 .ack_interrupt = kszphy_ack_interrupt,
@@ -231,7 +239,7 @@ MODULE_DESCRIPTION("Micrel PHY driver");
231MODULE_AUTHOR("David J. Choi"); 239MODULE_AUTHOR("David J. Choi");
232MODULE_LICENSE("GPL"); 240MODULE_LICENSE("GPL");
233 241
234static struct mdio_device_id micrel_tbl[] = { 242static struct mdio_device_id __maybe_unused micrel_tbl[] = {
235 { PHY_ID_KSZ9021, 0x000fff10 }, 243 { PHY_ID_KSZ9021, 0x000fff10 },
236 { PHY_ID_KS8001, 0x00fffff0 }, 244 { PHY_ID_KS8001, 0x00fffff0 },
237 { PHY_ID_KS8737, 0x00fffff0 }, 245 { PHY_ID_KS8737, 0x00fffff0 },
diff --git a/drivers/net/phy/national.c b/drivers/net/phy/national.c
index a73ba0bcc0ce..0620ba963508 100644
--- a/drivers/net/phy/national.c
+++ b/drivers/net/phy/national.c
@@ -151,7 +151,7 @@ MODULE_LICENSE("GPL");
151module_init(ns_init); 151module_init(ns_init);
152module_exit(ns_exit); 152module_exit(ns_exit);
153 153
154static struct mdio_device_id ns_tbl[] = { 154static struct mdio_device_id __maybe_unused ns_tbl[] = {
155 { DP83865_PHY_ID, 0xfffffff0 }, 155 { DP83865_PHY_ID, 0xfffffff0 },
156 { } 156 { }
157}; 157};
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 1bb16cb79433..a47595760751 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -47,11 +47,11 @@ void phy_print_status(struct phy_device *phydev)
47 pr_info("PHY: %s - Link is %s", dev_name(&phydev->dev), 47 pr_info("PHY: %s - Link is %s", dev_name(&phydev->dev),
48 phydev->link ? "Up" : "Down"); 48 phydev->link ? "Up" : "Down");
49 if (phydev->link) 49 if (phydev->link)
50 printk(" - %d/%s", phydev->speed, 50 printk(KERN_CONT " - %d/%s", phydev->speed,
51 DUPLEX_FULL == phydev->duplex ? 51 DUPLEX_FULL == phydev->duplex ?
52 "Full" : "Half"); 52 "Full" : "Half");
53 53
54 printk("\n"); 54 printk(KERN_CONT "\n");
55} 55}
56EXPORT_SYMBOL(phy_print_status); 56EXPORT_SYMBOL(phy_print_status);
57 57
@@ -65,7 +65,7 @@ EXPORT_SYMBOL(phy_print_status);
65 * 65 *
66 * Returns 0 on success on < 0 on error. 66 * Returns 0 on success on < 0 on error.
67 */ 67 */
68int phy_clear_interrupt(struct phy_device *phydev) 68static int phy_clear_interrupt(struct phy_device *phydev)
69{ 69{
70 int err = 0; 70 int err = 0;
71 71
@@ -82,7 +82,7 @@ int phy_clear_interrupt(struct phy_device *phydev)
82 * 82 *
83 * Returns 0 on success on < 0 on error. 83 * Returns 0 on success on < 0 on error.
84 */ 84 */
85int phy_config_interrupt(struct phy_device *phydev, u32 interrupts) 85static int phy_config_interrupt(struct phy_device *phydev, u32 interrupts)
86{ 86{
87 int err = 0; 87 int err = 0;
88 88
@@ -208,7 +208,7 @@ static inline int phy_find_valid(int idx, u32 features)
208 * duplexes. Drop down by one in this order: 1000/FULL, 208 * duplexes. Drop down by one in this order: 1000/FULL,
209 * 1000/HALF, 100/FULL, 100/HALF, 10/FULL, 10/HALF. 209 * 1000/HALF, 100/FULL, 100/HALF, 10/FULL, 10/HALF.
210 */ 210 */
211void phy_sanitize_settings(struct phy_device *phydev) 211static void phy_sanitize_settings(struct phy_device *phydev)
212{ 212{
213 u32 features = phydev->supported; 213 u32 features = phydev->supported;
214 int idx; 214 int idx;
@@ -223,7 +223,6 @@ void phy_sanitize_settings(struct phy_device *phydev)
223 phydev->speed = settings[idx].speed; 223 phydev->speed = settings[idx].speed;
224 phydev->duplex = settings[idx].duplex; 224 phydev->duplex = settings[idx].duplex;
225} 225}
226EXPORT_SYMBOL(phy_sanitize_settings);
227 226
228/** 227/**
229 * phy_ethtool_sset - generic ethtool sset function, handles all the details 228 * phy_ethtool_sset - generic ethtool sset function, handles all the details
@@ -239,6 +238,8 @@ EXPORT_SYMBOL(phy_sanitize_settings);
239 */ 238 */
240int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd) 239int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd)
241{ 240{
241 u32 speed = ethtool_cmd_speed(cmd);
242
242 if (cmd->phy_address != phydev->addr) 243 if (cmd->phy_address != phydev->addr)
243 return -EINVAL; 244 return -EINVAL;
244 245
@@ -254,16 +255,16 @@ int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd)
254 return -EINVAL; 255 return -EINVAL;
255 256
256 if (cmd->autoneg == AUTONEG_DISABLE && 257 if (cmd->autoneg == AUTONEG_DISABLE &&
257 ((cmd->speed != SPEED_1000 && 258 ((speed != SPEED_1000 &&
258 cmd->speed != SPEED_100 && 259 speed != SPEED_100 &&
259 cmd->speed != SPEED_10) || 260 speed != SPEED_10) ||
260 (cmd->duplex != DUPLEX_HALF && 261 (cmd->duplex != DUPLEX_HALF &&
261 cmd->duplex != DUPLEX_FULL))) 262 cmd->duplex != DUPLEX_FULL)))
262 return -EINVAL; 263 return -EINVAL;
263 264
264 phydev->autoneg = cmd->autoneg; 265 phydev->autoneg = cmd->autoneg;
265 266
266 phydev->speed = cmd->speed; 267 phydev->speed = speed;
267 268
268 phydev->advertising = cmd->advertising; 269 phydev->advertising = cmd->advertising;
269 270
@@ -287,7 +288,7 @@ int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd)
287 288
288 cmd->advertising = phydev->advertising; 289 cmd->advertising = phydev->advertising;
289 290
290 cmd->speed = phydev->speed; 291 ethtool_cmd_speed_set(cmd, phydev->speed);
291 cmd->duplex = phydev->duplex; 292 cmd->duplex = phydev->duplex;
292 cmd->port = PORT_MII; 293 cmd->port = PORT_MII;
293 cmd->phy_address = phydev->addr; 294 cmd->phy_address = phydev->addr;
@@ -320,7 +321,8 @@ int phy_mii_ioctl(struct phy_device *phydev,
320 /* fall through */ 321 /* fall through */
321 322
322 case SIOCGMIIREG: 323 case SIOCGMIIREG:
323 mii_data->val_out = phy_read(phydev, mii_data->reg_num); 324 mii_data->val_out = mdiobus_read(phydev->bus, mii_data->phy_id,
325 mii_data->reg_num);
324 break; 326 break;
325 327
326 case SIOCSMIIREG: 328 case SIOCSMIIREG:
@@ -351,8 +353,9 @@ int phy_mii_ioctl(struct phy_device *phydev,
351 } 353 }
352 } 354 }
353 355
354 phy_write(phydev, mii_data->reg_num, val); 356 mdiobus_write(phydev->bus, mii_data->phy_id,
355 357 mii_data->reg_num, val);
358
356 if (mii_data->reg_num == MII_BMCR && 359 if (mii_data->reg_num == MII_BMCR &&
357 val & BMCR_RESET && 360 val & BMCR_RESET &&
358 phydev->drv->config_init) { 361 phydev->drv->config_init) {
@@ -532,7 +535,7 @@ static irqreturn_t phy_interrupt(int irq, void *phy_dat)
532 * phy_enable_interrupts - Enable the interrupts from the PHY side 535 * phy_enable_interrupts - Enable the interrupts from the PHY side
533 * @phydev: target phy_device struct 536 * @phydev: target phy_device struct
534 */ 537 */
535int phy_enable_interrupts(struct phy_device *phydev) 538static int phy_enable_interrupts(struct phy_device *phydev)
536{ 539{
537 int err; 540 int err;
538 541
@@ -545,13 +548,12 @@ int phy_enable_interrupts(struct phy_device *phydev)
545 548
546 return err; 549 return err;
547} 550}
548EXPORT_SYMBOL(phy_enable_interrupts);
549 551
550/** 552/**
551 * phy_disable_interrupts - Disable the PHY interrupts from the PHY side 553 * phy_disable_interrupts - Disable the PHY interrupts from the PHY side
552 * @phydev: target phy_device struct 554 * @phydev: target phy_device struct
553 */ 555 */
554int phy_disable_interrupts(struct phy_device *phydev) 556static int phy_disable_interrupts(struct phy_device *phydev)
555{ 557{
556 int err; 558 int err;
557 559
@@ -574,7 +576,6 @@ phy_err:
574 576
575 return err; 577 return err;
576} 578}
577EXPORT_SYMBOL(phy_disable_interrupts);
578 579
579/** 580/**
580 * phy_start_interrupts - request and enable interrupts for a PHY device 581 * phy_start_interrupts - request and enable interrupts for a PHY device
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 16ddc77313cb..ff109fe5af6b 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -57,6 +57,9 @@ extern void mdio_bus_exit(void);
57static LIST_HEAD(phy_fixup_list); 57static LIST_HEAD(phy_fixup_list);
58static DEFINE_MUTEX(phy_fixup_lock); 58static DEFINE_MUTEX(phy_fixup_lock);
59 59
60static int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
61 u32 flags, phy_interface_t interface);
62
60/* 63/*
61 * Creates a new phy_fixup and adds it to the list 64 * Creates a new phy_fixup and adds it to the list
62 * @bus_id: A string which matches phydev->dev.bus_id (or PHY_ANY_ID) 65 * @bus_id: A string which matches phydev->dev.bus_id (or PHY_ANY_ID)
@@ -146,7 +149,8 @@ int phy_scan_fixups(struct phy_device *phydev)
146} 149}
147EXPORT_SYMBOL(phy_scan_fixups); 150EXPORT_SYMBOL(phy_scan_fixups);
148 151
149struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id) 152static struct phy_device* phy_device_create(struct mii_bus *bus,
153 int addr, int phy_id)
150{ 154{
151 struct phy_device *dev; 155 struct phy_device *dev;
152 156
@@ -193,7 +197,6 @@ struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id)
193 197
194 return dev; 198 return dev;
195} 199}
196EXPORT_SYMBOL(phy_device_create);
197 200
198/** 201/**
199 * get_phy_id - reads the specified addr for its ID. 202 * get_phy_id - reads the specified addr for its ID.
@@ -316,7 +319,7 @@ EXPORT_SYMBOL(phy_find_first);
316 * If you want to monitor your own link state, don't call 319 * If you want to monitor your own link state, don't call
317 * this function. 320 * this function.
318 */ 321 */
319void phy_prepare_link(struct phy_device *phydev, 322static void phy_prepare_link(struct phy_device *phydev,
320 void (*handler)(struct net_device *)) 323 void (*handler)(struct net_device *))
321{ 324{
322 phydev->adjust_link = handler; 325 phydev->adjust_link = handler;
@@ -435,15 +438,15 @@ int phy_init_hw(struct phy_device *phydev)
435 * the attaching device, and given a callback for link status 438 * the attaching device, and given a callback for link status
436 * change. The phy_device is returned to the attaching driver. 439 * change. The phy_device is returned to the attaching driver.
437 */ 440 */
438int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, 441static int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
439 u32 flags, phy_interface_t interface) 442 u32 flags, phy_interface_t interface)
440{ 443{
441 struct device *d = &phydev->dev; 444 struct device *d = &phydev->dev;
445 int err;
442 446
443 /* Assume that if there is no driver, that it doesn't 447 /* Assume that if there is no driver, that it doesn't
444 * exist, and we should use the genphy driver. */ 448 * exist, and we should use the genphy driver. */
445 if (NULL == d->driver) { 449 if (NULL == d->driver) {
446 int err;
447 d->driver = &genphy_driver.driver; 450 d->driver = &genphy_driver.driver;
448 451
449 err = d->driver->probe(d); 452 err = d->driver->probe(d);
@@ -471,9 +474,12 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
471 /* Do initial configuration here, now that 474 /* Do initial configuration here, now that
472 * we have certain key parameters 475 * we have certain key parameters
473 * (dev_flags and interface) */ 476 * (dev_flags and interface) */
474 return phy_init_hw(phydev); 477 err = phy_init_hw(phydev);
478 if (err)
479 phy_detach(phydev);
480
481 return err;
475} 482}
476EXPORT_SYMBOL(phy_attach_direct);
477 483
478/** 484/**
479 * phy_attach - attach a network device to a particular PHY device 485 * phy_attach - attach a network device to a particular PHY device
@@ -532,7 +538,7 @@ EXPORT_SYMBOL(phy_detach);
532/* Generic PHY support and helper functions */ 538/* Generic PHY support and helper functions */
533 539
534/** 540/**
535 * genphy_config_advert - sanitize and advertise auto-negotation parameters 541 * genphy_config_advert - sanitize and advertise auto-negotiation parameters
536 * @phydev: target phy_device struct 542 * @phydev: target phy_device struct
537 * 543 *
538 * Description: Writes MII_ADVERTISE with the appropriate values, 544 * Description: Writes MII_ADVERTISE with the appropriate values,
@@ -540,7 +546,7 @@ EXPORT_SYMBOL(phy_detach);
540 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement 546 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
541 * hasn't changed, and > 0 if it has changed. 547 * hasn't changed, and > 0 if it has changed.
542 */ 548 */
543int genphy_config_advert(struct phy_device *phydev) 549static int genphy_config_advert(struct phy_device *phydev)
544{ 550{
545 u32 advertise; 551 u32 advertise;
546 int oldadv, adv; 552 int oldadv, adv;
@@ -605,7 +611,6 @@ int genphy_config_advert(struct phy_device *phydev)
605 611
606 return changed; 612 return changed;
607} 613}
608EXPORT_SYMBOL(genphy_config_advert);
609 614
610/** 615/**
611 * genphy_setup_forced - configures/forces speed/duplex from @phydev 616 * genphy_setup_forced - configures/forces speed/duplex from @phydev
@@ -615,7 +620,7 @@ EXPORT_SYMBOL(genphy_config_advert);
615 * to the values in phydev. Assumes that the values are valid. 620 * to the values in phydev. Assumes that the values are valid.
616 * Please see phy_sanitize_settings(). 621 * Please see phy_sanitize_settings().
617 */ 622 */
618int genphy_setup_forced(struct phy_device *phydev) 623static int genphy_setup_forced(struct phy_device *phydev)
619{ 624{
620 int err; 625 int err;
621 int ctl = 0; 626 int ctl = 0;
@@ -682,7 +687,7 @@ int genphy_config_aneg(struct phy_device *phydev)
682 return result; 687 return result;
683 688
684 if (result == 0) { 689 if (result == 0) {
685 /* Advertisment hasn't changed, but maybe aneg was never on to 690 /* Advertisement hasn't changed, but maybe aneg was never on to
686 * begin with? Or maybe phy was isolated? */ 691 * begin with? Or maybe phy was isolated? */
687 int ctl = phy_read(phydev, MII_BMCR); 692 int ctl = phy_read(phydev, MII_BMCR);
688 693
diff --git a/drivers/net/phy/qsemi.c b/drivers/net/phy/qsemi.c
index 6736b23f1b28..fe0d0a15d5e1 100644
--- a/drivers/net/phy/qsemi.c
+++ b/drivers/net/phy/qsemi.c
@@ -138,7 +138,7 @@ static void __exit qs6612_exit(void)
138module_init(qs6612_init); 138module_init(qs6612_init);
139module_exit(qs6612_exit); 139module_exit(qs6612_exit);
140 140
141static struct mdio_device_id qs6612_tbl[] = { 141static struct mdio_device_id __maybe_unused qs6612_tbl[] = {
142 { 0x00181440, 0xfffffff0 }, 142 { 0x00181440, 0xfffffff0 },
143 { } 143 { }
144}; 144};
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index f567c0e1aaa1..a4eae750a414 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -79,7 +79,7 @@ static void __exit realtek_exit(void)
79module_init(realtek_init); 79module_init(realtek_init);
80module_exit(realtek_exit); 80module_exit(realtek_exit);
81 81
82static struct mdio_device_id realtek_tbl[] = { 82static struct mdio_device_id __maybe_unused realtek_tbl[] = {
83 { 0x001cc912, 0x001fffff }, 83 { 0x001cc912, 0x001fffff },
84 { } 84 { }
85}; 85};
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 78fa988256fc..342505c976d6 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -254,7 +254,7 @@ MODULE_LICENSE("GPL");
254module_init(smsc_init); 254module_init(smsc_init);
255module_exit(smsc_exit); 255module_exit(smsc_exit);
256 256
257static struct mdio_device_id smsc_tbl[] = { 257static struct mdio_device_id __maybe_unused smsc_tbl[] = {
258 { 0x0007c0a0, 0xfffffff0 }, 258 { 0x0007c0a0, 0xfffffff0 },
259 { 0x0007c0b0, 0xfffffff0 }, 259 { 0x0007c0b0, 0xfffffff0 },
260 { 0x0007c0c0, 0xfffffff0 }, 260 { 0x0007c0c0, 0xfffffff0 },
diff --git a/drivers/net/phy/ste10Xp.c b/drivers/net/phy/ste10Xp.c
index 72290099e5e1..187a2fa814f2 100644
--- a/drivers/net/phy/ste10Xp.c
+++ b/drivers/net/phy/ste10Xp.c
@@ -132,7 +132,7 @@ static void __exit ste10Xp_exit(void)
132module_init(ste10Xp_init); 132module_init(ste10Xp_init);
133module_exit(ste10Xp_exit); 133module_exit(ste10Xp_exit);
134 134
135static struct mdio_device_id ste10Xp_tbl[] = { 135static struct mdio_device_id __maybe_unused ste10Xp_tbl[] = {
136 { STE101P_PHY_ID, 0xfffffff0 }, 136 { STE101P_PHY_ID, 0xfffffff0 },
137 { STE100P_PHY_ID, 0xffffffff }, 137 { STE100P_PHY_ID, 0xffffffff },
138 { } 138 { }
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 45cce50a2799..5d8f6e17bd55 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -192,7 +192,7 @@ static void __exit vsc82xx_exit(void)
192module_init(vsc82xx_init); 192module_init(vsc82xx_init);
193module_exit(vsc82xx_exit); 193module_exit(vsc82xx_exit);
194 194
195static struct mdio_device_id vitesse_tbl[] = { 195static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
196 { PHY_ID_VSC8244, 0x000fffc0 }, 196 { PHY_ID_VSC8244, 0x000fffc0 },
197 { PHY_ID_VSC8221, 0x000ffff0 }, 197 { PHY_ID_VSC8221, 0x000ffff0 },
198 { } 198 { }
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 14:15:48 -0400