diff options
Diffstat (limited to 'drivers/net/netxen/netxen_nic_hw.c')
-rw-r--r-- | drivers/net/netxen/netxen_nic_hw.c | 131 |
1 files changed, 53 insertions, 78 deletions
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index b1cf46a0c48c..5c496f8d7c49 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #define MASK(n) ((1ULL<<(n))-1) | 32 | #define MASK(n) ((1ULL<<(n))-1) |
33 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) | 33 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) |
34 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) | 34 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) |
35 | #define OCM_WIN_P3P(addr) (addr & 0xffc0000) | ||
36 | #define MS_WIN(addr) (addr & 0x0ffc0000) | 35 | #define MS_WIN(addr) (addr & 0x0ffc0000) |
37 | 36 | ||
38 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | 37 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) |
@@ -63,9 +62,6 @@ static inline void writeq(u64 val, void __iomem *addr) | |||
63 | } | 62 | } |
64 | #endif | 63 | #endif |
65 | 64 | ||
66 | #define ADDR_IN_RANGE(addr, low, high) \ | ||
67 | (((addr) < (high)) && ((addr) >= (low))) | ||
68 | |||
69 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ | 65 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
70 | ((adapter)->ahw.pci_base0 + (off)) | 66 | ((adapter)->ahw.pci_base0 + (off)) |
71 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | 67 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ |
@@ -538,7 +534,7 @@ netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, | |||
538 | void netxen_p2_nic_set_multi(struct net_device *netdev) | 534 | void netxen_p2_nic_set_multi(struct net_device *netdev) |
539 | { | 535 | { |
540 | struct netxen_adapter *adapter = netdev_priv(netdev); | 536 | struct netxen_adapter *adapter = netdev_priv(netdev); |
541 | struct dev_mc_list *mc_ptr; | 537 | struct netdev_hw_addr *ha; |
542 | u8 null_addr[6]; | 538 | u8 null_addr[6]; |
543 | int i; | 539 | int i; |
544 | 540 | ||
@@ -572,8 +568,8 @@ void netxen_p2_nic_set_multi(struct net_device *netdev) | |||
572 | netxen_nic_enable_mcast_filter(adapter); | 568 | netxen_nic_enable_mcast_filter(adapter); |
573 | 569 | ||
574 | i = 0; | 570 | i = 0; |
575 | netdev_for_each_mc_addr(mc_ptr, netdev) | 571 | netdev_for_each_mc_addr(ha, netdev) |
576 | netxen_nic_set_mcast_addr(adapter, i++, mc_ptr->dmi_addr); | 572 | netxen_nic_set_mcast_addr(adapter, i++, ha->addr); |
577 | 573 | ||
578 | /* Clear out remaining addresses */ | 574 | /* Clear out remaining addresses */ |
579 | while (i < adapter->max_mc_count) | 575 | while (i < adapter->max_mc_count) |
@@ -681,7 +677,7 @@ static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, | |||
681 | void netxen_p3_nic_set_multi(struct net_device *netdev) | 677 | void netxen_p3_nic_set_multi(struct net_device *netdev) |
682 | { | 678 | { |
683 | struct netxen_adapter *adapter = netdev_priv(netdev); | 679 | struct netxen_adapter *adapter = netdev_priv(netdev); |
684 | struct dev_mc_list *mc_ptr; | 680 | struct netdev_hw_addr *ha; |
685 | u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | 681 | u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
686 | u32 mode = VPORT_MISS_MODE_DROP; | 682 | u32 mode = VPORT_MISS_MODE_DROP; |
687 | LIST_HEAD(del_list); | 683 | LIST_HEAD(del_list); |
@@ -708,8 +704,8 @@ void netxen_p3_nic_set_multi(struct net_device *netdev) | |||
708 | } | 704 | } |
709 | 705 | ||
710 | if (!netdev_mc_empty(netdev)) { | 706 | if (!netdev_mc_empty(netdev)) { |
711 | netdev_for_each_mc_addr(mc_ptr, netdev) | 707 | netdev_for_each_mc_addr(ha, netdev) |
712 | nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list); | 708 | nx_p3_nic_add_mac(adapter, ha->addr, &del_list); |
713 | } | 709 | } |
714 | 710 | ||
715 | send_fw_cmd: | 711 | send_fw_cmd: |
@@ -1391,18 +1387,8 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |||
1391 | u64 addr, u32 *start) | 1387 | u64 addr, u32 *start) |
1392 | { | 1388 | { |
1393 | u32 window; | 1389 | u32 window; |
1394 | struct pci_dev *pdev = adapter->pdev; | ||
1395 | 1390 | ||
1396 | if ((addr & 0x00ff800) == 0xff800) { | 1391 | window = OCM_WIN(addr); |
1397 | if (printk_ratelimit()) | ||
1398 | dev_warn(&pdev->dev, "QM access not handled\n"); | ||
1399 | return -EIO; | ||
1400 | } | ||
1401 | |||
1402 | if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) | ||
1403 | window = OCM_WIN_P3P(addr); | ||
1404 | else | ||
1405 | window = OCM_WIN(addr); | ||
1406 | 1392 | ||
1407 | writel(window, adapter->ahw.ocm_win_crb); | 1393 | writel(window, adapter->ahw.ocm_win_crb); |
1408 | /* read back to flush */ | 1394 | /* read back to flush */ |
@@ -1419,7 +1405,7 @@ netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off, | |||
1419 | { | 1405 | { |
1420 | void __iomem *addr, *mem_ptr = NULL; | 1406 | void __iomem *addr, *mem_ptr = NULL; |
1421 | resource_size_t mem_base; | 1407 | resource_size_t mem_base; |
1422 | int ret = -EIO; | 1408 | int ret; |
1423 | u32 start; | 1409 | u32 start; |
1424 | 1410 | ||
1425 | spin_lock(&adapter->ahw.mem_lock); | 1411 | spin_lock(&adapter->ahw.mem_lock); |
@@ -1428,20 +1414,23 @@ netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off, | |||
1428 | if (ret != 0) | 1414 | if (ret != 0) |
1429 | goto unlock; | 1415 | goto unlock; |
1430 | 1416 | ||
1431 | addr = pci_base_offset(adapter, start); | 1417 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
1432 | if (addr) | 1418 | addr = adapter->ahw.pci_base0 + start; |
1433 | goto noremap; | 1419 | } else { |
1434 | 1420 | addr = pci_base_offset(adapter, start); | |
1435 | mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK); | 1421 | if (addr) |
1422 | goto noremap; | ||
1423 | |||
1424 | mem_base = pci_resource_start(adapter->pdev, 0) + | ||
1425 | (start & PAGE_MASK); | ||
1426 | mem_ptr = ioremap(mem_base, PAGE_SIZE); | ||
1427 | if (mem_ptr == NULL) { | ||
1428 | ret = -EIO; | ||
1429 | goto unlock; | ||
1430 | } | ||
1436 | 1431 | ||
1437 | mem_ptr = ioremap(mem_base, PAGE_SIZE); | 1432 | addr = mem_ptr + (start & (PAGE_SIZE-1)); |
1438 | if (mem_ptr == NULL) { | ||
1439 | ret = -EIO; | ||
1440 | goto unlock; | ||
1441 | } | 1433 | } |
1442 | |||
1443 | addr = mem_ptr + (start & (PAGE_SIZE - 1)); | ||
1444 | |||
1445 | noremap: | 1434 | noremap: |
1446 | if (op == 0) /* read */ | 1435 | if (op == 0) /* read */ |
1447 | *data = readq(addr); | 1436 | *data = readq(addr); |
@@ -1456,6 +1445,28 @@ unlock: | |||
1456 | return ret; | 1445 | return ret; |
1457 | } | 1446 | } |
1458 | 1447 | ||
1448 | void | ||
1449 | netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data) | ||
1450 | { | ||
1451 | void __iomem *addr = adapter->ahw.pci_base0 + | ||
1452 | NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); | ||
1453 | |||
1454 | spin_lock(&adapter->ahw.mem_lock); | ||
1455 | *data = readq(addr); | ||
1456 | spin_unlock(&adapter->ahw.mem_lock); | ||
1457 | } | ||
1458 | |||
1459 | void | ||
1460 | netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data) | ||
1461 | { | ||
1462 | void __iomem *addr = adapter->ahw.pci_base0 + | ||
1463 | NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); | ||
1464 | |||
1465 | spin_lock(&adapter->ahw.mem_lock); | ||
1466 | writeq(data, addr); | ||
1467 | spin_unlock(&adapter->ahw.mem_lock); | ||
1468 | } | ||
1469 | |||
1459 | #define MAX_CTL_CHECK 1000 | 1470 | #define MAX_CTL_CHECK 1000 |
1460 | 1471 | ||
1461 | static int | 1472 | static int |
@@ -1621,9 +1632,8 @@ static int | |||
1621 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | 1632 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
1622 | u64 off, u64 data) | 1633 | u64 off, u64 data) |
1623 | { | 1634 | { |
1624 | int i, j, ret; | 1635 | int j, ret; |
1625 | u32 temp, off8; | 1636 | u32 temp, off8; |
1626 | u64 stride; | ||
1627 | void __iomem *mem_crb; | 1637 | void __iomem *mem_crb; |
1628 | 1638 | ||
1629 | /* Only 64-bit aligned access */ | 1639 | /* Only 64-bit aligned access */ |
@@ -1650,44 +1660,17 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | |||
1650 | return -EIO; | 1660 | return -EIO; |
1651 | 1661 | ||
1652 | correct: | 1662 | correct: |
1653 | stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8; | 1663 | off8 = off & 0xfffffff8; |
1654 | |||
1655 | off8 = off & ~(stride-1); | ||
1656 | 1664 | ||
1657 | spin_lock(&adapter->ahw.mem_lock); | 1665 | spin_lock(&adapter->ahw.mem_lock); |
1658 | 1666 | ||
1659 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); | 1667 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1660 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); | 1668 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); |
1661 | 1669 | ||
1662 | i = 0; | ||
1663 | if (stride == 16) { | ||
1664 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | ||
1665 | writel((TA_CTL_START | TA_CTL_ENABLE), | ||
1666 | (mem_crb + TEST_AGT_CTRL)); | ||
1667 | |||
1668 | for (j = 0; j < MAX_CTL_CHECK; j++) { | ||
1669 | temp = readl(mem_crb + TEST_AGT_CTRL); | ||
1670 | if ((temp & TA_CTL_BUSY) == 0) | ||
1671 | break; | ||
1672 | } | ||
1673 | |||
1674 | if (j >= MAX_CTL_CHECK) { | ||
1675 | ret = -EIO; | ||
1676 | goto done; | ||
1677 | } | ||
1678 | |||
1679 | i = (off & 0xf) ? 0 : 2; | ||
1680 | writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)), | ||
1681 | mem_crb + MIU_TEST_AGT_WRDATA(i)); | ||
1682 | writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)), | ||
1683 | mem_crb + MIU_TEST_AGT_WRDATA(i+1)); | ||
1684 | i = (off & 0xf) ? 2 : 0; | ||
1685 | } | ||
1686 | |||
1687 | writel(data & 0xffffffff, | 1670 | writel(data & 0xffffffff, |
1688 | mem_crb + MIU_TEST_AGT_WRDATA(i)); | 1671 | mem_crb + MIU_TEST_AGT_WRDATA_LO); |
1689 | writel((data >> 32) & 0xffffffff, | 1672 | writel((data >> 32) & 0xffffffff, |
1690 | mem_crb + MIU_TEST_AGT_WRDATA(i+1)); | 1673 | mem_crb + MIU_TEST_AGT_WRDATA_HI); |
1691 | 1674 | ||
1692 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); | 1675 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); |
1693 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), | 1676 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), |
@@ -1707,7 +1690,6 @@ correct: | |||
1707 | } else | 1690 | } else |
1708 | ret = 0; | 1691 | ret = 0; |
1709 | 1692 | ||
1710 | done: | ||
1711 | spin_unlock(&adapter->ahw.mem_lock); | 1693 | spin_unlock(&adapter->ahw.mem_lock); |
1712 | 1694 | ||
1713 | return ret; | 1695 | return ret; |
@@ -1719,7 +1701,7 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |||
1719 | { | 1701 | { |
1720 | int j, ret; | 1702 | int j, ret; |
1721 | u32 temp, off8; | 1703 | u32 temp, off8; |
1722 | u64 val, stride; | 1704 | u64 val; |
1723 | void __iomem *mem_crb; | 1705 | void __iomem *mem_crb; |
1724 | 1706 | ||
1725 | /* Only 64-bit aligned access */ | 1707 | /* Only 64-bit aligned access */ |
@@ -1748,9 +1730,7 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |||
1748 | return -EIO; | 1730 | return -EIO; |
1749 | 1731 | ||
1750 | correct: | 1732 | correct: |
1751 | stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8; | 1733 | off8 = off & 0xfffffff8; |
1752 | |||
1753 | off8 = off & ~(stride-1); | ||
1754 | 1734 | ||
1755 | spin_lock(&adapter->ahw.mem_lock); | 1735 | spin_lock(&adapter->ahw.mem_lock); |
1756 | 1736 | ||
@@ -1771,13 +1751,8 @@ correct: | |||
1771 | "failed to read through agent\n"); | 1751 | "failed to read through agent\n"); |
1772 | ret = -EIO; | 1752 | ret = -EIO; |
1773 | } else { | 1753 | } else { |
1774 | off8 = MIU_TEST_AGT_RDDATA_LO; | 1754 | val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32; |
1775 | if ((stride == 16) && (off & 0xf)) | 1755 | val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO); |
1776 | off8 = MIU_TEST_AGT_RDDATA_UPPER_LO; | ||
1777 | |||
1778 | temp = readl(mem_crb + off8 + 4); | ||
1779 | val = (u64)temp << 32; | ||
1780 | val |= readl(mem_crb + off8); | ||
1781 | *data = val; | 1756 | *data = val; |
1782 | ret = 0; | 1757 | ret = 0; |
1783 | } | 1758 | } |