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path: root/drivers/net/mlx4/fw.c
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Diffstat (limited to 'drivers/net/mlx4/fw.c')
-rw-r--r--drivers/net/mlx4/fw.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/net/mlx4/fw.c b/drivers/net/mlx4/fw.c
index 2b5006b9be67..57278224ba1e 100644
--- a/drivers/net/mlx4/fw.c
+++ b/drivers/net/mlx4/fw.c
@@ -46,6 +46,10 @@ enum {
46extern void __buggy_use_of_MLX4_GET(void); 46extern void __buggy_use_of_MLX4_GET(void);
47extern void __buggy_use_of_MLX4_PUT(void); 47extern void __buggy_use_of_MLX4_PUT(void);
48 48
49static int enable_qos;
50module_param(enable_qos, bool, 0444);
51MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
52
49#define MLX4_GET(dest, source, offset) \ 53#define MLX4_GET(dest, source, offset) \
50 do { \ 54 do { \
51 void *__p = (char *) (source) + (offset); \ 55 void *__p = (char *) (source) + (offset); \
@@ -198,7 +202,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
198#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 202#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
199#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 203#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
200#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 204#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
201#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x97 205#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
202#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 206#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
203#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 207#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
204 208
@@ -373,12 +377,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
373 } 377 }
374 } 378 }
375 379
376 if (dev_cap->bmme_flags & 1) 380 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
377 mlx4_dbg(dev, "Base MM extensions: yes " 381 dev_cap->bmme_flags, dev_cap->reserved_lkey);
378 "(flags %d, rsvd L_Key %08x)\n",
379 dev_cap->bmme_flags, dev_cap->reserved_lkey);
380 else
381 mlx4_dbg(dev, "Base MM extensions: no\n");
382 382
383 /* 383 /*
384 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 384 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
@@ -737,6 +737,10 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
737 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 737 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
738 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 738 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
739 739
740 /* Enable QoS support if module parameter set */
741 if (enable_qos)
742 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
743
740 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 744 /* QPC/EEC/CQC/EQC/RDMARC attributes */
741 745
742 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 746 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);