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path: root/drivers/net/jme.c
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-rw-r--r--drivers/net/jme.c604
1 files changed, 393 insertions, 211 deletions
diff --git a/drivers/net/jme.c b/drivers/net/jme.c
index 99f24f5cac53..b5b174a8c149 100644
--- a/drivers/net/jme.c
+++ b/drivers/net/jme.c
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright 2008 JMicron Technology Corporation 4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/ 5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
6 * 7 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * 9 *
@@ -21,6 +22,8 @@
21 * 22 *
22 */ 23 */
23 24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
24#include <linux/module.h> 27#include <linux/module.h>
25#include <linux/kernel.h> 28#include <linux/kernel.h>
26#include <linux/pci.h> 29#include <linux/pci.h>
@@ -73,7 +76,7 @@ read_again:
73 } 76 }
74 77
75 if (i == 0) { 78 if (i == 0) {
76 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg); 79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
77 return 0; 80 return 0;
78 } 81 }
79 82
@@ -102,7 +105,7 @@ jme_mdio_write(struct net_device *netdev,
102 } 105 }
103 106
104 if (i == 0) 107 if (i == 0)
105 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg); 108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
106} 109}
107 110
108static inline void 111static inline void
@@ -132,7 +135,7 @@ jme_reset_phy_processor(struct jme_adapter *jme)
132 135
133static void 136static void
134jme_setup_wakeup_frame(struct jme_adapter *jme, 137jme_setup_wakeup_frame(struct jme_adapter *jme,
135 u32 *mask, u32 crc, int fnr) 138 const u32 *mask, u32 crc, int fnr)
136{ 139{
137 int i; 140 int i;
138 141
@@ -158,16 +161,92 @@ jme_setup_wakeup_frame(struct jme_adapter *jme,
158} 161}
159 162
160static inline void 163static inline void
164jme_mac_rxclk_off(struct jme_adapter *jme)
165{
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168}
169
170static inline void
171jme_mac_rxclk_on(struct jme_adapter *jme)
172{
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175}
176
177static inline void
178jme_mac_txclk_off(struct jme_adapter *jme)
179{
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
182}
183
184static inline void
185jme_mac_txclk_on(struct jme_adapter *jme)
186{
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190 else
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
193}
194
195static inline void
196jme_reset_ghc_speed(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_reset_250A2_workaround(struct jme_adapter *jme)
204{
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206 GPREG1_RSSPATCH);
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208}
209
210static inline void
211jme_assert_ghc_reset(struct jme_adapter *jme)
212{
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215}
216
217static inline void
218jme_clear_ghc_reset(struct jme_adapter *jme)
219{
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
222}
223
224static inline void
161jme_reset_mac_processor(struct jme_adapter *jme) 225jme_reset_mac_processor(struct jme_adapter *jme)
162{ 226{
163 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0}; 227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
164 u32 crc = 0xCDCDCDCD; 228 u32 crc = 0xCDCDCDCD;
165 u32 gpreg0; 229 u32 gpreg0;
166 int i; 230 int i;
167 231
168 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST); 232 jme_reset_ghc_speed(jme);
169 udelay(2); 233 jme_reset_250A2_workaround(jme);
170 jwrite32(jme, JME_GHC, jme->reg_ghc); 234
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
237 udelay(1);
238 jme_assert_ghc_reset(jme);
239 udelay(1);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
242 udelay(1);
243 jme_clear_ghc_reset(jme);
244 udelay(1);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
247 udelay(1);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
171 250
172 jwrite32(jme, JME_RXDBA_LO, 0x00000000); 251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
173 jwrite32(jme, JME_RXDBA_HI, 0x00000000); 252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
@@ -187,14 +266,6 @@ jme_reset_mac_processor(struct jme_adapter *jme)
187 else 266 else
188 gpreg0 = GPREG0_DEFAULT; 267 gpreg0 = GPREG0_DEFAULT;
189 jwrite32(jme, JME_GPREG0, gpreg0); 268 jwrite32(jme, JME_GPREG0, gpreg0);
190 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
191}
192
193static inline void
194jme_reset_ghc_speed(struct jme_adapter *jme)
195{
196 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
197 jwrite32(jme, JME_GHC, jme->reg_ghc);
198} 269}
199 270
200static inline void 271static inline void
@@ -202,7 +273,7 @@ jme_clear_pm(struct jme_adapter *jme)
202{ 273{
203 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs); 274 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
204 pci_set_power_state(jme->pdev, PCI_D0); 275 pci_set_power_state(jme->pdev, PCI_D0);
205 pci_enable_wake(jme->pdev, PCI_D0, false); 276 device_set_wakeup_enable(&jme->pdev->dev, false);
206} 277}
207 278
208static int 279static int
@@ -227,7 +298,7 @@ jme_reload_eeprom(struct jme_adapter *jme)
227 } 298 }
228 299
229 if (i == 0) { 300 if (i == 0) {
230 jeprintk(jme->pdev, "eeprom reload timeout\n"); 301 pr_err("eeprom reload timeout\n");
231 return -EIO; 302 return -EIO;
232 } 303 }
233 } 304 }
@@ -333,13 +404,13 @@ jme_linkstat_from_phy(struct jme_adapter *jme)
333} 404}
334 405
335static inline void 406static inline void
336jme_set_phyfifoa(struct jme_adapter *jme) 407jme_set_phyfifo_5level(struct jme_adapter *jme)
337{ 408{
338 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004); 409 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
339} 410}
340 411
341static inline void 412static inline void
342jme_set_phyfifob(struct jme_adapter *jme) 413jme_set_phyfifo_8level(struct jme_adapter *jme)
343{ 414{
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000); 415 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
345} 416}
@@ -348,7 +419,7 @@ static int
348jme_check_link(struct net_device *netdev, int testonly) 419jme_check_link(struct net_device *netdev, int testonly)
349{ 420{
350 struct jme_adapter *jme = netdev_priv(netdev); 421 struct jme_adapter *jme = netdev_priv(netdev);
351 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1; 422 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
352 char linkmsg[64]; 423 char linkmsg[64];
353 int rc = 0; 424 int rc = 0;
354 425
@@ -397,8 +468,7 @@ jme_check_link(struct net_device *netdev, int testonly)
397 phylink = jread32(jme, JME_PHY_LINK); 468 phylink = jread32(jme, JME_PHY_LINK);
398 } 469 }
399 if (!cnt) 470 if (!cnt)
400 jeprintk(jme->pdev, 471 pr_err("Waiting speed resolve timeout\n");
401 "Waiting speed resolve timeout.\n");
402 472
403 strcat(linkmsg, "ANed: "); 473 strcat(linkmsg, "ANed: ");
404 } 474 }
@@ -412,23 +482,21 @@ jme_check_link(struct net_device *netdev, int testonly)
412 482
413 jme->phylink = phylink; 483 jme->phylink = phylink;
414 484
415 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX | 485 /*
416 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE | 486 * The speed/duplex setting of jme->reg_ghc already cleared
417 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY); 487 * by jme_reset_mac_processor()
488 */
418 switch (phylink & PHY_LINK_SPEED_MASK) { 489 switch (phylink & PHY_LINK_SPEED_MASK) {
419 case PHY_LINK_SPEED_10M: 490 case PHY_LINK_SPEED_10M:
420 ghc |= GHC_SPEED_10M | 491 jme->reg_ghc |= GHC_SPEED_10M;
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
422 strcat(linkmsg, "10 Mbps, "); 492 strcat(linkmsg, "10 Mbps, ");
423 break; 493 break;
424 case PHY_LINK_SPEED_100M: 494 case PHY_LINK_SPEED_100M:
425 ghc |= GHC_SPEED_100M | 495 jme->reg_ghc |= GHC_SPEED_100M;
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
427 strcat(linkmsg, "100 Mbps, "); 496 strcat(linkmsg, "100 Mbps, ");
428 break; 497 break;
429 case PHY_LINK_SPEED_1000M: 498 case PHY_LINK_SPEED_1000M:
430 ghc |= GHC_SPEED_1000M | 499 jme->reg_ghc |= GHC_SPEED_1000M;
431 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
432 strcat(linkmsg, "1000 Mbps, "); 500 strcat(linkmsg, "1000 Mbps, ");
433 break; 501 break;
434 default: 502 default:
@@ -437,42 +505,40 @@ jme_check_link(struct net_device *netdev, int testonly)
437 505
438 if (phylink & PHY_LINK_DUPLEX) { 506 if (phylink & PHY_LINK_DUPLEX) {
439 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT); 507 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
440 ghc |= GHC_DPX; 508 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
509 jme->reg_ghc |= GHC_DPX;
441 } else { 510 } else {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT | 511 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
443 TXMCS_BACKOFF | 512 TXMCS_BACKOFF |
444 TXMCS_CARRIERSENSE | 513 TXMCS_CARRIERSENSE |
445 TXMCS_COLLISION); 514 TXMCS_COLLISION);
446 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN | 515 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
447 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
448 TXTRHD_TXREN |
449 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
450 } 516 }
451 517
452 gpreg1 = GPREG1_DEFAULT; 518 jwrite32(jme, JME_GHC, jme->reg_ghc);
519
453 if (is_buggy250(jme->pdev->device, jme->chiprev)) { 520 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
521 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
522 GPREG1_RSSPATCH);
454 if (!(phylink & PHY_LINK_DUPLEX)) 523 if (!(phylink & PHY_LINK_DUPLEX))
455 gpreg1 |= GPREG1_HALFMODEPATCH; 524 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
456 switch (phylink & PHY_LINK_SPEED_MASK) { 525 switch (phylink & PHY_LINK_SPEED_MASK) {
457 case PHY_LINK_SPEED_10M: 526 case PHY_LINK_SPEED_10M:
458 jme_set_phyfifoa(jme); 527 jme_set_phyfifo_8level(jme);
459 gpreg1 |= GPREG1_RSSPATCH; 528 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
460 break; 529 break;
461 case PHY_LINK_SPEED_100M: 530 case PHY_LINK_SPEED_100M:
462 jme_set_phyfifob(jme); 531 jme_set_phyfifo_5level(jme);
463 gpreg1 |= GPREG1_RSSPATCH; 532 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
464 break; 533 break;
465 case PHY_LINK_SPEED_1000M: 534 case PHY_LINK_SPEED_1000M:
466 jme_set_phyfifoa(jme); 535 jme_set_phyfifo_8level(jme);
467 break; 536 break;
468 default: 537 default:
469 break; 538 break;
470 } 539 }
471 } 540 }
472 541 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
473 jwrite32(jme, JME_GPREG1, gpreg1);
474 jwrite32(jme, JME_GHC, ghc);
475 jme->reg_ghc = ghc;
476 542
477 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ? 543 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
478 "Full-Duplex, " : 544 "Full-Duplex, " :
@@ -480,13 +546,13 @@ jme_check_link(struct net_device *netdev, int testonly)
480 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ? 546 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
481 "MDI-X" : 547 "MDI-X" :
482 "MDI"); 548 "MDI");
483 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg); 549 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
484 netif_carrier_on(netdev); 550 netif_carrier_on(netdev);
485 } else { 551 } else {
486 if (testonly) 552 if (testonly)
487 goto out; 553 goto out;
488 554
489 netif_info(jme, link, jme->dev, "Link is down.\n"); 555 netif_info(jme, link, jme->dev, "Link is down\n");
490 jme->phylink = 0; 556 jme->phylink = 0;
491 netif_carrier_off(netdev); 557 netif_carrier_off(netdev);
492 } 558 }
@@ -611,10 +677,14 @@ jme_enable_tx_engine(struct jme_adapter *jme)
611 * Enable TX Engine 677 * Enable TX Engine
612 */ 678 */
613 wmb(); 679 wmb();
614 jwrite32(jme, JME_TXCS, jme->reg_txcs | 680 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
615 TXCS_SELECT_QUEUE0 | 681 TXCS_SELECT_QUEUE0 |
616 TXCS_ENABLE); 682 TXCS_ENABLE);
617 683
684 /*
685 * Start clock for TX MAC Processor
686 */
687 jme_mac_txclk_on(jme);
618} 688}
619 689
620static inline void 690static inline void
@@ -648,7 +718,12 @@ jme_disable_tx_engine(struct jme_adapter *jme)
648 } 718 }
649 719
650 if (!i) 720 if (!i)
651 jeprintk(jme->pdev, "Disable TX engine timeout.\n"); 721 pr_err("Disable TX engine timeout\n");
722
723 /*
724 * Stop clock for TX MAC Processor
725 */
726 jme_mac_txclk_off(jme);
652} 727}
653 728
654static void 729static void
@@ -823,16 +898,22 @@ jme_enable_rx_engine(struct jme_adapter *jme)
823 /* 898 /*
824 * Setup Unicast Filter 899 * Setup Unicast Filter
825 */ 900 */
901 jme_set_unicastaddr(jme->dev);
826 jme_set_multi(jme->dev); 902 jme_set_multi(jme->dev);
827 903
828 /* 904 /*
829 * Enable RX Engine 905 * Enable RX Engine
830 */ 906 */
831 wmb(); 907 wmb();
832 jwrite32(jme, JME_RXCS, jme->reg_rxcs | 908 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
833 RXCS_QUEUESEL_Q0 | 909 RXCS_QUEUESEL_Q0 |
834 RXCS_ENABLE | 910 RXCS_ENABLE |
835 RXCS_QST); 911 RXCS_QST);
912
913 /*
914 * Start clock for RX MAC Processor
915 */
916 jme_mac_rxclk_on(jme);
836} 917}
837 918
838static inline void 919static inline void
@@ -867,12 +948,42 @@ jme_disable_rx_engine(struct jme_adapter *jme)
867 } 948 }
868 949
869 if (!i) 950 if (!i)
870 jeprintk(jme->pdev, "Disable RX engine timeout.\n"); 951 pr_err("Disable RX engine timeout\n");
871 952
953 /*
954 * Stop clock for RX MAC Processor
955 */
956 jme_mac_rxclk_off(jme);
957}
958
959static u16
960jme_udpsum(struct sk_buff *skb)
961{
962 u16 csum = 0xFFFFu;
963
964 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
965 return csum;
966 if (skb->protocol != htons(ETH_P_IP))
967 return csum;
968 skb_set_network_header(skb, ETH_HLEN);
969 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
970 (skb->len < (ETH_HLEN +
971 (ip_hdr(skb)->ihl << 2) +
972 sizeof(struct udphdr)))) {
973 skb_reset_network_header(skb);
974 return csum;
975 }
976 skb_set_transport_header(skb,
977 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
978 csum = udp_hdr(skb)->check;
979 skb_reset_transport_header(skb);
980 skb_reset_network_header(skb);
981
982 return csum;
872} 983}
873 984
874static int 985static int
875jme_rxsum_ok(struct jme_adapter *jme, u16 flags) 986jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
876{ 987{
877 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4))) 988 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
878 return false; 989 return false;
@@ -885,15 +996,15 @@ jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
885 } 996 }
886 997
887 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS)) 998 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
888 == RXWBFLAG_UDPON)) { 999 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
889 if (flags & RXWBFLAG_IPV4) 1000 if (flags & RXWBFLAG_IPV4)
890 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n"); 1001 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
891 return false; 1002 return false;
892 } 1003 }
893 1004
894 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS)) 1005 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
895 == RXWBFLAG_IPV4)) { 1006 == RXWBFLAG_IPV4)) {
896 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n"); 1007 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
897 return false; 1008 return false;
898 } 1009 }
899 1010
@@ -933,10 +1044,10 @@ jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
933 skb_put(skb, framesize); 1044 skb_put(skb, framesize);
934 skb->protocol = eth_type_trans(skb, jme->dev); 1045 skb->protocol = eth_type_trans(skb, jme->dev);
935 1046
936 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags))) 1047 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
937 skb->ip_summed = CHECKSUM_UNNECESSARY; 1048 skb->ip_summed = CHECKSUM_UNNECESSARY;
938 else 1049 else
939 skb->ip_summed = CHECKSUM_NONE; 1050 skb_checksum_none_assert(skb);
940 1051
941 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) { 1052 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
942 if (jme->vlgrp) { 1053 if (jme->vlgrp) {
@@ -988,6 +1099,7 @@ jme_process_receive(struct jme_adapter *jme, int limit)
988 goto out; 1099 goto out;
989 --limit; 1100 --limit;
990 1101
1102 rmb();
991 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT; 1103 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
992 1104
993 if (unlikely(desccnt > 1 || 1105 if (unlikely(desccnt > 1 ||
@@ -1185,9 +1297,9 @@ jme_link_change_tasklet(unsigned long arg)
1185 1297
1186 while (!atomic_dec_and_test(&jme->link_changing)) { 1298 while (!atomic_dec_and_test(&jme->link_changing)) {
1187 atomic_inc(&jme->link_changing); 1299 atomic_inc(&jme->link_changing);
1188 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n"); 1300 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1189 while (atomic_read(&jme->link_changing) != 1) 1301 while (atomic_read(&jme->link_changing) != 1)
1190 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n"); 1302 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1191 } 1303 }
1192 1304
1193 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu) 1305 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
@@ -1204,7 +1316,6 @@ jme_link_change_tasklet(unsigned long arg)
1204 tasklet_disable(&jme->rxempty_task); 1316 tasklet_disable(&jme->rxempty_task);
1205 1317
1206 if (netif_carrier_ok(netdev)) { 1318 if (netif_carrier_ok(netdev)) {
1207 jme_reset_ghc_speed(jme);
1208 jme_disable_rx_engine(jme); 1319 jme_disable_rx_engine(jme);
1209 jme_disable_tx_engine(jme); 1320 jme_disable_tx_engine(jme);
1210 jme_reset_mac_processor(jme); 1321 jme_reset_mac_processor(jme);
@@ -1221,15 +1332,13 @@ jme_link_change_tasklet(unsigned long arg)
1221 if (netif_carrier_ok(netdev)) { 1332 if (netif_carrier_ok(netdev)) {
1222 rc = jme_setup_rx_resources(jme); 1333 rc = jme_setup_rx_resources(jme);
1223 if (rc) { 1334 if (rc) {
1224 jeprintk(jme->pdev, "Allocating resources for RX error" 1335 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1225 ", Device STOPPED!\n");
1226 goto out_enable_tasklet; 1336 goto out_enable_tasklet;
1227 } 1337 }
1228 1338
1229 rc = jme_setup_tx_resources(jme); 1339 rc = jme_setup_tx_resources(jme);
1230 if (rc) { 1340 if (rc) {
1231 jeprintk(jme->pdev, "Allocating resources for TX error" 1341 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1232 ", Device STOPPED!\n");
1233 goto err_out_free_rx_resources; 1342 goto err_out_free_rx_resources;
1234 } 1343 }
1235 1344
@@ -1324,7 +1433,7 @@ jme_wake_queue_if_stopped(struct jme_adapter *jme)
1324 smp_wmb(); 1433 smp_wmb();
1325 if (unlikely(netif_queue_stopped(jme->dev) && 1434 if (unlikely(netif_queue_stopped(jme->dev) &&
1326 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) { 1435 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1327 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n"); 1436 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1328 netif_wake_queue(jme->dev); 1437 netif_wake_queue(jme->dev);
1329 } 1438 }
1330 1439
@@ -1339,7 +1448,7 @@ jme_tx_clean_tasklet(unsigned long arg)
1339 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi; 1448 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1340 int i, j, cnt = 0, max, err, mask; 1449 int i, j, cnt = 0, max, err, mask;
1341 1450
1342 tx_dbg(jme, "Into txclean.\n"); 1451 tx_dbg(jme, "Into txclean\n");
1343 1452
1344 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning))) 1453 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1345 goto out; 1454 goto out;
@@ -1361,7 +1470,7 @@ jme_tx_clean_tasklet(unsigned long arg)
1361 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) { 1470 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1362 1471
1363 tx_dbg(jme, "txclean: %d+%d@%lu\n", 1472 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1364 i, ctxbi->nr_desc, jiffies); 1473 i, ctxbi->nr_desc, jiffies);
1365 1474
1366 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR; 1475 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1367 1476
@@ -1402,7 +1511,7 @@ jme_tx_clean_tasklet(unsigned long arg)
1402 ctxbi->nr_desc = 0; 1511 ctxbi->nr_desc = 0;
1403 } 1512 }
1404 1513
1405 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies); 1514 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1406 atomic_set(&txring->next_to_clean, i); 1515 atomic_set(&txring->next_to_clean, i);
1407 atomic_add(cnt, &txring->nr_free); 1516 atomic_add(cnt, &txring->nr_free);
1408 1517
@@ -1548,10 +1657,10 @@ jme_request_irq(struct jme_adapter *jme)
1548 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name, 1657 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1549 netdev); 1658 netdev);
1550 if (rc) { 1659 if (rc) {
1551 jeprintk(jme->pdev, 1660 netdev_err(netdev,
1552 "Unable to request %s interrupt (return: %d)\n", 1661 "Unable to request %s interrupt (return: %d)\n",
1553 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx", 1662 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1554 rc); 1663 rc);
1555 1664
1556 if (test_bit(JME_FLAG_MSI, &jme->flags)) { 1665 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1557 pci_disable_msi(jme->pdev); 1666 pci_disable_msi(jme->pdev);
@@ -1575,6 +1684,64 @@ jme_free_irq(struct jme_adapter *jme)
1575 } 1684 }
1576} 1685}
1577 1686
1687static inline void
1688jme_new_phy_on(struct jme_adapter *jme)
1689{
1690 u32 reg;
1691
1692 reg = jread32(jme, JME_PHY_PWR);
1693 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1694 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1695 jwrite32(jme, JME_PHY_PWR, reg);
1696
1697 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1698 reg &= ~PE1_GPREG0_PBG;
1699 reg |= PE1_GPREG0_ENBG;
1700 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1701}
1702
1703static inline void
1704jme_new_phy_off(struct jme_adapter *jme)
1705{
1706 u32 reg;
1707
1708 reg = jread32(jme, JME_PHY_PWR);
1709 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1710 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1711 jwrite32(jme, JME_PHY_PWR, reg);
1712
1713 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1714 reg &= ~PE1_GPREG0_PBG;
1715 reg |= PE1_GPREG0_PDD3COLD;
1716 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1717}
1718
1719static inline void
1720jme_phy_on(struct jme_adapter *jme)
1721{
1722 u32 bmcr;
1723
1724 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1725 bmcr &= ~BMCR_PDOWN;
1726 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1727
1728 if (new_phy_power_ctrl(jme->chip_main_rev))
1729 jme_new_phy_on(jme);
1730}
1731
1732static inline void
1733jme_phy_off(struct jme_adapter *jme)
1734{
1735 u32 bmcr;
1736
1737 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1738 bmcr |= BMCR_PDOWN;
1739 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1740
1741 if (new_phy_power_ctrl(jme->chip_main_rev))
1742 jme_new_phy_off(jme);
1743}
1744
1578static int 1745static int
1579jme_open(struct net_device *netdev) 1746jme_open(struct net_device *netdev)
1580{ 1747{
@@ -1595,6 +1762,7 @@ jme_open(struct net_device *netdev)
1595 1762
1596 jme_start_irq(jme); 1763 jme_start_irq(jme);
1597 1764
1765 jme_phy_on(jme);
1598 if (test_bit(JME_FLAG_SSET, &jme->flags)) 1766 if (test_bit(JME_FLAG_SSET, &jme->flags))
1599 jme_set_settings(netdev, &jme->old_ecmd); 1767 jme_set_settings(netdev, &jme->old_ecmd);
1600 else 1768 else
@@ -1610,12 +1778,12 @@ err_out:
1610 return rc; 1778 return rc;
1611} 1779}
1612 1780
1613#ifdef CONFIG_PM
1614static void 1781static void
1615jme_set_100m_half(struct jme_adapter *jme) 1782jme_set_100m_half(struct jme_adapter *jme)
1616{ 1783{
1617 u32 bmcr, tmp; 1784 u32 bmcr, tmp;
1618 1785
1786 jme_phy_on(jme);
1619 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1787 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1620 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | 1788 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1621 BMCR_SPEED1000 | BMCR_FULLDPLX); 1789 BMCR_SPEED1000 | BMCR_FULLDPLX);
@@ -1643,12 +1811,20 @@ jme_wait_link(struct jme_adapter *jme)
1643 phylink = jme_linkstat_from_phy(jme); 1811 phylink = jme_linkstat_from_phy(jme);
1644 } 1812 }
1645} 1813}
1646#endif
1647 1814
1648static inline void 1815static void
1649jme_phy_off(struct jme_adapter *jme) 1816jme_powersave_phy(struct jme_adapter *jme)
1650{ 1817{
1651 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN); 1818 if (jme->reg_pmcs) {
1819 jme_set_100m_half(jme);
1820
1821 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1822 jme_wait_link(jme);
1823
1824 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1825 } else {
1826 jme_phy_off(jme);
1827 }
1652} 1828}
1653 1829
1654static int 1830static int
@@ -1669,7 +1845,6 @@ jme_close(struct net_device *netdev)
1669 tasklet_disable(&jme->rxclean_task); 1845 tasklet_disable(&jme->rxclean_task);
1670 tasklet_disable(&jme->rxempty_task); 1846 tasklet_disable(&jme->rxempty_task);
1671 1847
1672 jme_reset_ghc_speed(jme);
1673 jme_disable_rx_engine(jme); 1848 jme_disable_rx_engine(jme);
1674 jme_disable_tx_engine(jme); 1849 jme_disable_tx_engine(jme);
1675 jme_reset_mac_processor(jme); 1850 jme_reset_mac_processor(jme);
@@ -1834,7 +2009,7 @@ jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1834 *flags |= TXFLAG_UDPCS; 2009 *flags |= TXFLAG_UDPCS;
1835 break; 2010 break;
1836 default: 2011 default:
1837 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n"); 2012 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1838 break; 2013 break;
1839 } 2014 }
1840 } 2015 }
@@ -1909,12 +2084,12 @@ jme_stop_queue_if_full(struct jme_adapter *jme)
1909 smp_wmb(); 2084 smp_wmb();
1910 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) { 2085 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1911 netif_stop_queue(jme->dev); 2086 netif_stop_queue(jme->dev);
1912 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n"); 2087 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1913 smp_wmb(); 2088 smp_wmb();
1914 if (atomic_read(&txring->nr_free) 2089 if (atomic_read(&txring->nr_free)
1915 >= (jme->tx_wake_threshold)) { 2090 >= (jme->tx_wake_threshold)) {
1916 netif_wake_queue(jme->dev); 2091 netif_wake_queue(jme->dev);
1917 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n"); 2092 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1918 } 2093 }
1919 } 2094 }
1920 2095
@@ -1922,7 +2097,8 @@ jme_stop_queue_if_full(struct jme_adapter *jme)
1922 (jiffies - txbi->start_xmit) >= TX_TIMEOUT && 2097 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1923 txbi->skb)) { 2098 txbi->skb)) {
1924 netif_stop_queue(jme->dev); 2099 netif_stop_queue(jme->dev);
1925 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies); 2100 netif_info(jme, tx_queued, jme->dev,
2101 "TX Queue Stopped %d@%lu\n", idx, jiffies);
1926 } 2102 }
1927} 2103}
1928 2104
@@ -1945,7 +2121,8 @@ jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1945 2121
1946 if (unlikely(idx < 0)) { 2122 if (unlikely(idx < 0)) {
1947 netif_stop_queue(netdev); 2123 netif_stop_queue(netdev);
1948 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n"); 2124 netif_err(jme, tx_err, jme->dev,
2125 "BUG! Tx ring full when queue awake!\n");
1949 2126
1950 return NETDEV_TX_BUSY; 2127 return NETDEV_TX_BUSY;
1951 } 2128 }
@@ -1957,35 +2134,41 @@ jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1957 TXCS_QUEUE0S | 2134 TXCS_QUEUE0S |
1958 TXCS_ENABLE); 2135 TXCS_ENABLE);
1959 2136
1960 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx, 2137 tx_dbg(jme, "xmit: %d+%d@%lu\n",
1961 skb_shinfo(skb)->nr_frags + 2, 2138 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
1962 jiffies);
1963 jme_stop_queue_if_full(jme); 2139 jme_stop_queue_if_full(jme);
1964 2140
1965 return NETDEV_TX_OK; 2141 return NETDEV_TX_OK;
1966} 2142}
1967 2143
2144static void
2145jme_set_unicastaddr(struct net_device *netdev)
2146{
2147 struct jme_adapter *jme = netdev_priv(netdev);
2148 u32 val;
2149
2150 val = (netdev->dev_addr[3] & 0xff) << 24 |
2151 (netdev->dev_addr[2] & 0xff) << 16 |
2152 (netdev->dev_addr[1] & 0xff) << 8 |
2153 (netdev->dev_addr[0] & 0xff);
2154 jwrite32(jme, JME_RXUMA_LO, val);
2155 val = (netdev->dev_addr[5] & 0xff) << 8 |
2156 (netdev->dev_addr[4] & 0xff);
2157 jwrite32(jme, JME_RXUMA_HI, val);
2158}
2159
1968static int 2160static int
1969jme_set_macaddr(struct net_device *netdev, void *p) 2161jme_set_macaddr(struct net_device *netdev, void *p)
1970{ 2162{
1971 struct jme_adapter *jme = netdev_priv(netdev); 2163 struct jme_adapter *jme = netdev_priv(netdev);
1972 struct sockaddr *addr = p; 2164 struct sockaddr *addr = p;
1973 u32 val;
1974 2165
1975 if (netif_running(netdev)) 2166 if (netif_running(netdev))
1976 return -EBUSY; 2167 return -EBUSY;
1977 2168
1978 spin_lock_bh(&jme->macaddr_lock); 2169 spin_lock_bh(&jme->macaddr_lock);
1979 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2170 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1980 2171 jme_set_unicastaddr(netdev);
1981 val = (addr->sa_data[3] & 0xff) << 24 |
1982 (addr->sa_data[2] & 0xff) << 16 |
1983 (addr->sa_data[1] & 0xff) << 8 |
1984 (addr->sa_data[0] & 0xff);
1985 jwrite32(jme, JME_RXUMA_LO, val);
1986 val = (addr->sa_data[5] & 0xff) << 8 |
1987 (addr->sa_data[4] & 0xff);
1988 jwrite32(jme, JME_RXUMA_HI, val);
1989 spin_unlock_bh(&jme->macaddr_lock); 2172 spin_unlock_bh(&jme->macaddr_lock);
1990 2173
1991 return 0; 2174 return 0;
@@ -2047,18 +2230,9 @@ jme_change_mtu(struct net_device *netdev, int new_mtu)
2047 jme_restart_rx_engine(jme); 2230 jme_restart_rx_engine(jme);
2048 } 2231 }
2049 2232
2050 if (new_mtu > 1900) {
2051 netdev->features &= ~(NETIF_F_HW_CSUM |
2052 NETIF_F_TSO |
2053 NETIF_F_TSO6);
2054 } else {
2055 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2056 netdev->features |= NETIF_F_HW_CSUM;
2057 if (test_bit(JME_FLAG_TSO, &jme->flags))
2058 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2059 }
2060
2061 netdev->mtu = new_mtu; 2233 netdev->mtu = new_mtu;
2234 netdev_update_features(netdev);
2235
2062 jme_reset_link(jme); 2236 jme_reset_link(jme);
2063 2237
2064 return 0; 2238 return 0;
@@ -2356,6 +2530,8 @@ jme_set_wol(struct net_device *netdev,
2356 2530
2357 jwrite32(jme, JME_PMCS, jme->reg_pmcs); 2531 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2358 2532
2533 device_set_wakeup_enable(&jme->pdev->dev, jme->reg_pmcs);
2534
2359 return 0; 2535 return 0;
2360} 2536}
2361 2537
@@ -2379,9 +2555,14 @@ jme_set_settings(struct net_device *netdev,
2379 struct jme_adapter *jme = netdev_priv(netdev); 2555 struct jme_adapter *jme = netdev_priv(netdev);
2380 int rc, fdc = 0; 2556 int rc, fdc = 0;
2381 2557
2382 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE) 2558 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2559 && ecmd->autoneg != AUTONEG_ENABLE)
2383 return -EINVAL; 2560 return -EINVAL;
2384 2561
2562 /*
2563 * Check If user changed duplex only while force_media.
2564 * Hardware would not generate link change interrupt.
2565 */
2385 if (jme->mii_if.force_media && 2566 if (jme->mii_if.force_media &&
2386 ecmd->autoneg != AUTONEG_ENABLE && 2567 ecmd->autoneg != AUTONEG_ENABLE &&
2387 (jme->mii_if.full_duplex != ecmd->duplex)) 2568 (jme->mii_if.full_duplex != ecmd->duplex))
@@ -2391,12 +2572,40 @@ jme_set_settings(struct net_device *netdev,
2391 rc = mii_ethtool_sset(&(jme->mii_if), ecmd); 2572 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2392 spin_unlock_bh(&jme->phy_lock); 2573 spin_unlock_bh(&jme->phy_lock);
2393 2574
2394 if (!rc && fdc)
2395 jme_reset_link(jme);
2396
2397 if (!rc) { 2575 if (!rc) {
2398 set_bit(JME_FLAG_SSET, &jme->flags); 2576 if (fdc)
2577 jme_reset_link(jme);
2399 jme->old_ecmd = *ecmd; 2578 jme->old_ecmd = *ecmd;
2579 set_bit(JME_FLAG_SSET, &jme->flags);
2580 }
2581
2582 return rc;
2583}
2584
2585static int
2586jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2587{
2588 int rc;
2589 struct jme_adapter *jme = netdev_priv(netdev);
2590 struct mii_ioctl_data *mii_data = if_mii(rq);
2591 unsigned int duplex_chg;
2592
2593 if (cmd == SIOCSMIIREG) {
2594 u16 val = mii_data->val_in;
2595 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2596 (val & BMCR_SPEED1000))
2597 return -EINVAL;
2598 }
2599
2600 spin_lock_bh(&jme->phy_lock);
2601 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2602 spin_unlock_bh(&jme->phy_lock);
2603
2604 if (!rc && (cmd == SIOCSMIIREG)) {
2605 if (duplex_chg)
2606 jme_reset_link(jme);
2607 jme_get_settings(netdev, &jme->old_ecmd);
2608 set_bit(JME_FLAG_SSET, &jme->flags);
2400 } 2609 }
2401 2610
2402 return rc; 2611 return rc;
@@ -2424,19 +2633,20 @@ jme_set_msglevel(struct net_device *netdev, u32 value)
2424} 2633}
2425 2634
2426static u32 2635static u32
2427jme_get_rx_csum(struct net_device *netdev) 2636jme_fix_features(struct net_device *netdev, u32 features)
2428{ 2637{
2429 struct jme_adapter *jme = netdev_priv(netdev); 2638 if (netdev->mtu > 1900)
2430 return jme->reg_rxmcs & RXMCS_CHECKSUM; 2639 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2640 return features;
2431} 2641}
2432 2642
2433static int 2643static int
2434jme_set_rx_csum(struct net_device *netdev, u32 on) 2644jme_set_features(struct net_device *netdev, u32 features)
2435{ 2645{
2436 struct jme_adapter *jme = netdev_priv(netdev); 2646 struct jme_adapter *jme = netdev_priv(netdev);
2437 2647
2438 spin_lock_bh(&jme->rxmcs_lock); 2648 spin_lock_bh(&jme->rxmcs_lock);
2439 if (on) 2649 if (features & NETIF_F_RXCSUM)
2440 jme->reg_rxmcs |= RXMCS_CHECKSUM; 2650 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2441 else 2651 else
2442 jme->reg_rxmcs &= ~RXMCS_CHECKSUM; 2652 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
@@ -2447,40 +2657,6 @@ jme_set_rx_csum(struct net_device *netdev, u32 on)
2447} 2657}
2448 2658
2449static int 2659static int
2450jme_set_tx_csum(struct net_device *netdev, u32 on)
2451{
2452 struct jme_adapter *jme = netdev_priv(netdev);
2453
2454 if (on) {
2455 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2456 if (netdev->mtu <= 1900)
2457 netdev->features |= NETIF_F_HW_CSUM;
2458 } else {
2459 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2460 netdev->features &= ~NETIF_F_HW_CSUM;
2461 }
2462
2463 return 0;
2464}
2465
2466static int
2467jme_set_tso(struct net_device *netdev, u32 on)
2468{
2469 struct jme_adapter *jme = netdev_priv(netdev);
2470
2471 if (on) {
2472 set_bit(JME_FLAG_TSO, &jme->flags);
2473 if (netdev->mtu <= 1900)
2474 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2475 } else {
2476 clear_bit(JME_FLAG_TSO, &jme->flags);
2477 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2478 }
2479
2480 return 0;
2481}
2482
2483static int
2484jme_nway_reset(struct net_device *netdev) 2660jme_nway_reset(struct net_device *netdev)
2485{ 2661{
2486 struct jme_adapter *jme = netdev_priv(netdev); 2662 struct jme_adapter *jme = netdev_priv(netdev);
@@ -2501,7 +2677,7 @@ jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2501 val = jread32(jme, JME_SMBCSR); 2677 val = jread32(jme, JME_SMBCSR);
2502 } 2678 }
2503 if (!to) { 2679 if (!to) {
2504 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n"); 2680 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2505 return 0xFF; 2681 return 0xFF;
2506 } 2682 }
2507 2683
@@ -2517,7 +2693,7 @@ jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2517 val = jread32(jme, JME_SMBINTF); 2693 val = jread32(jme, JME_SMBINTF);
2518 } 2694 }
2519 if (!to) { 2695 if (!to) {
2520 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n"); 2696 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2521 return 0xFF; 2697 return 0xFF;
2522 } 2698 }
2523 2699
@@ -2537,7 +2713,7 @@ jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2537 val = jread32(jme, JME_SMBCSR); 2713 val = jread32(jme, JME_SMBCSR);
2538 } 2714 }
2539 if (!to) { 2715 if (!to) {
2540 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n"); 2716 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2541 return; 2717 return;
2542 } 2718 }
2543 2719
@@ -2554,7 +2730,7 @@ jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2554 val = jread32(jme, JME_SMBINTF); 2730 val = jread32(jme, JME_SMBINTF);
2555 } 2731 }
2556 if (!to) { 2732 if (!to) {
2557 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n"); 2733 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2558 return; 2734 return;
2559 } 2735 }
2560 2736
@@ -2621,11 +2797,6 @@ static const struct ethtool_ops jme_ethtool_ops = {
2621 .get_link = jme_get_link, 2797 .get_link = jme_get_link,
2622 .get_msglevel = jme_get_msglevel, 2798 .get_msglevel = jme_get_msglevel,
2623 .set_msglevel = jme_set_msglevel, 2799 .set_msglevel = jme_set_msglevel,
2624 .get_rx_csum = jme_get_rx_csum,
2625 .set_rx_csum = jme_set_rx_csum,
2626 .set_tx_csum = jme_set_tx_csum,
2627 .set_tso = jme_set_tso,
2628 .set_sg = ethtool_op_set_sg,
2629 .nway_reset = jme_nway_reset, 2800 .nway_reset = jme_nway_reset,
2630 .get_eeprom_len = jme_get_eeprom_len, 2801 .get_eeprom_len = jme_get_eeprom_len,
2631 .get_eeprom = jme_get_eeprom, 2802 .get_eeprom = jme_get_eeprom,
@@ -2670,18 +2841,23 @@ jme_check_hw_ver(struct jme_adapter *jme)
2670 2841
2671 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT; 2842 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2672 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT; 2843 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2844 jme->chip_main_rev = jme->chiprev & 0xF;
2845 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2673} 2846}
2674 2847
2675static const struct net_device_ops jme_netdev_ops = { 2848static const struct net_device_ops jme_netdev_ops = {
2676 .ndo_open = jme_open, 2849 .ndo_open = jme_open,
2677 .ndo_stop = jme_close, 2850 .ndo_stop = jme_close,
2678 .ndo_validate_addr = eth_validate_addr, 2851 .ndo_validate_addr = eth_validate_addr,
2852 .ndo_do_ioctl = jme_ioctl,
2679 .ndo_start_xmit = jme_start_xmit, 2853 .ndo_start_xmit = jme_start_xmit,
2680 .ndo_set_mac_address = jme_set_macaddr, 2854 .ndo_set_mac_address = jme_set_macaddr,
2681 .ndo_set_multicast_list = jme_set_multi, 2855 .ndo_set_multicast_list = jme_set_multi,
2682 .ndo_change_mtu = jme_change_mtu, 2856 .ndo_change_mtu = jme_change_mtu,
2683 .ndo_tx_timeout = jme_tx_timeout, 2857 .ndo_tx_timeout = jme_tx_timeout,
2684 .ndo_vlan_rx_register = jme_vlan_rx_register, 2858 .ndo_vlan_rx_register = jme_vlan_rx_register,
2859 .ndo_fix_features = jme_fix_features,
2860 .ndo_set_features = jme_set_features,
2685}; 2861};
2686 2862
2687static int __devinit 2863static int __devinit
@@ -2699,26 +2875,26 @@ jme_init_one(struct pci_dev *pdev,
2699 */ 2875 */
2700 rc = pci_enable_device(pdev); 2876 rc = pci_enable_device(pdev);
2701 if (rc) { 2877 if (rc) {
2702 jeprintk(pdev, "Cannot enable PCI device.\n"); 2878 pr_err("Cannot enable PCI device\n");
2703 goto err_out; 2879 goto err_out;
2704 } 2880 }
2705 2881
2706 using_dac = jme_pci_dma64(pdev); 2882 using_dac = jme_pci_dma64(pdev);
2707 if (using_dac < 0) { 2883 if (using_dac < 0) {
2708 jeprintk(pdev, "Cannot set PCI DMA Mask.\n"); 2884 pr_err("Cannot set PCI DMA Mask\n");
2709 rc = -EIO; 2885 rc = -EIO;
2710 goto err_out_disable_pdev; 2886 goto err_out_disable_pdev;
2711 } 2887 }
2712 2888
2713 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2889 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2714 jeprintk(pdev, "No PCI resource region found.\n"); 2890 pr_err("No PCI resource region found\n");
2715 rc = -ENOMEM; 2891 rc = -ENOMEM;
2716 goto err_out_disable_pdev; 2892 goto err_out_disable_pdev;
2717 } 2893 }
2718 2894
2719 rc = pci_request_regions(pdev, DRV_NAME); 2895 rc = pci_request_regions(pdev, DRV_NAME);
2720 if (rc) { 2896 if (rc) {
2721 jeprintk(pdev, "Cannot obtain PCI resource region.\n"); 2897 pr_err("Cannot obtain PCI resource region\n");
2722 goto err_out_disable_pdev; 2898 goto err_out_disable_pdev;
2723 } 2899 }
2724 2900
@@ -2729,14 +2905,21 @@ jme_init_one(struct pci_dev *pdev,
2729 */ 2905 */
2730 netdev = alloc_etherdev(sizeof(*jme)); 2906 netdev = alloc_etherdev(sizeof(*jme));
2731 if (!netdev) { 2907 if (!netdev) {
2732 jeprintk(pdev, "Cannot allocate netdev structure.\n"); 2908 pr_err("Cannot allocate netdev structure\n");
2733 rc = -ENOMEM; 2909 rc = -ENOMEM;
2734 goto err_out_release_regions; 2910 goto err_out_release_regions;
2735 } 2911 }
2736 netdev->netdev_ops = &jme_netdev_ops; 2912 netdev->netdev_ops = &jme_netdev_ops;
2737 netdev->ethtool_ops = &jme_ethtool_ops; 2913 netdev->ethtool_ops = &jme_ethtool_ops;
2738 netdev->watchdog_timeo = TX_TIMEOUT; 2914 netdev->watchdog_timeo = TX_TIMEOUT;
2739 netdev->features = NETIF_F_HW_CSUM | 2915 netdev->hw_features = NETIF_F_IP_CSUM |
2916 NETIF_F_IPV6_CSUM |
2917 NETIF_F_SG |
2918 NETIF_F_TSO |
2919 NETIF_F_TSO6 |
2920 NETIF_F_RXCSUM;
2921 netdev->features = NETIF_F_IP_CSUM |
2922 NETIF_F_IPV6_CSUM |
2740 NETIF_F_SG | 2923 NETIF_F_SG |
2741 NETIF_F_TSO | 2924 NETIF_F_TSO |
2742 NETIF_F_TSO6 | 2925 NETIF_F_TSO6 |
@@ -2767,7 +2950,7 @@ jme_init_one(struct pci_dev *pdev,
2767 jme->regs = ioremap(pci_resource_start(pdev, 0), 2950 jme->regs = ioremap(pci_resource_start(pdev, 0),
2768 pci_resource_len(pdev, 0)); 2951 pci_resource_len(pdev, 0));
2769 if (!(jme->regs)) { 2952 if (!(jme->regs)) {
2770 jeprintk(pdev, "Mapping PCI resource region error.\n"); 2953 pr_err("Mapping PCI resource region error\n");
2771 rc = -ENOMEM; 2954 rc = -ENOMEM;
2772 goto err_out_free_netdev; 2955 goto err_out_free_netdev;
2773 } 2956 }
@@ -2817,8 +3000,10 @@ jme_init_one(struct pci_dev *pdev,
2817 jme->reg_rxmcs = RXMCS_DEFAULT; 3000 jme->reg_rxmcs = RXMCS_DEFAULT;
2818 jme->reg_txpfc = 0; 3001 jme->reg_txpfc = 0;
2819 jme->reg_pmcs = PMCS_MFEN; 3002 jme->reg_pmcs = PMCS_MFEN;
2820 set_bit(JME_FLAG_TXCSUM, &jme->flags); 3003 jme->reg_gpreg1 = GPREG1_DEFAULT;
2821 set_bit(JME_FLAG_TSO, &jme->flags); 3004
3005 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3006 netdev->features |= NETIF_F_RXCSUM;
2822 3007
2823 /* 3008 /*
2824 * Get Max Read Req Size from PCI Config Space 3009 * Get Max Read Req Size from PCI Config Space
@@ -2855,8 +3040,8 @@ jme_init_one(struct pci_dev *pdev,
2855 3040
2856 if (!jme->mii_if.phy_id) { 3041 if (!jme->mii_if.phy_id) {
2857 rc = -EIO; 3042 rc = -EIO;
2858 jeprintk(pdev, "Can not find phy_id.\n"); 3043 pr_err("Can not find phy_id\n");
2859 goto err_out_unmap; 3044 goto err_out_unmap;
2860 } 3045 }
2861 3046
2862 jme->reg_ghc |= GHC_LINK_POLL; 3047 jme->reg_ghc |= GHC_LINK_POLL;
@@ -2867,12 +3052,14 @@ jme_init_one(struct pci_dev *pdev,
2867 jme->mii_if.supports_gmii = true; 3052 jme->mii_if.supports_gmii = true;
2868 else 3053 else
2869 jme->mii_if.supports_gmii = false; 3054 jme->mii_if.supports_gmii = false;
3055 jme->mii_if.phy_id_mask = 0x1F;
3056 jme->mii_if.reg_num_mask = 0x1F;
2870 jme->mii_if.mdio_read = jme_mdio_read; 3057 jme->mii_if.mdio_read = jme_mdio_read;
2871 jme->mii_if.mdio_write = jme_mdio_write; 3058 jme->mii_if.mdio_write = jme_mdio_write;
2872 3059
2873 jme_clear_pm(jme); 3060 jme_clear_pm(jme);
2874 jme_set_phyfifoa(jme); 3061 jme_set_phyfifo_5level(jme);
2875 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev); 3062 jme->pcirev = pdev->revision;
2876 if (!jme->fpgaver) 3063 if (!jme->fpgaver)
2877 jme_phy_init(jme); 3064 jme_phy_init(jme);
2878 jme_phy_off(jme); 3065 jme_phy_off(jme);
@@ -2883,8 +3070,7 @@ jme_init_one(struct pci_dev *pdev,
2883 jme_reset_mac_processor(jme); 3070 jme_reset_mac_processor(jme);
2884 rc = jme_reload_eeprom(jme); 3071 rc = jme_reload_eeprom(jme);
2885 if (rc) { 3072 if (rc) {
2886 jeprintk(pdev, 3073 pr_err("Reload eeprom for reading MAC Address error\n");
2887 "Reload eeprom for reading MAC Address error.\n");
2888 goto err_out_unmap; 3074 goto err_out_unmap;
2889 } 3075 }
2890 jme_load_macaddr(netdev); 3076 jme_load_macaddr(netdev);
@@ -2893,25 +3079,21 @@ jme_init_one(struct pci_dev *pdev,
2893 * Tell stack that we are not ready to work until open() 3079 * Tell stack that we are not ready to work until open()
2894 */ 3080 */
2895 netif_carrier_off(netdev); 3081 netif_carrier_off(netdev);
2896 netif_stop_queue(netdev);
2897 3082
2898 /*
2899 * Register netdev
2900 */
2901 rc = register_netdev(netdev); 3083 rc = register_netdev(netdev);
2902 if (rc) { 3084 if (rc) {
2903 jeprintk(pdev, "Cannot register net device.\n"); 3085 pr_err("Cannot register net device\n");
2904 goto err_out_unmap; 3086 goto err_out_unmap;
2905 } 3087 }
2906 3088
2907 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n", 3089 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
2908 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ? 3090 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2909 "JMC250 Gigabit Ethernet" : 3091 "JMC250 Gigabit Ethernet" :
2910 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ? 3092 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2911 "JMC260 Fast Ethernet" : "Unknown", 3093 "JMC260 Fast Ethernet" : "Unknown",
2912 (jme->fpgaver != 0) ? " (FPGA)" : "", 3094 (jme->fpgaver != 0) ? " (FPGA)" : "",
2913 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev, 3095 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2914 jme->rev, netdev->dev_addr); 3096 jme->pcirev, netdev->dev_addr);
2915 3097
2916 return 0; 3098 return 0;
2917 3099
@@ -2943,10 +3125,20 @@ jme_remove_one(struct pci_dev *pdev)
2943 3125
2944} 3126}
2945 3127
3128static void
3129jme_shutdown(struct pci_dev *pdev)
3130{
3131 struct net_device *netdev = pci_get_drvdata(pdev);
3132 struct jme_adapter *jme = netdev_priv(netdev);
3133
3134 jme_powersave_phy(jme);
3135 pci_pme_active(pdev, true);
3136}
3137
2946#ifdef CONFIG_PM 3138#ifdef CONFIG_PM
2947static int 3139static int jme_suspend(struct device *dev)
2948jme_suspend(struct pci_dev *pdev, pm_message_t state)
2949{ 3140{
3141 struct pci_dev *pdev = to_pci_dev(dev);
2950 struct net_device *netdev = pci_get_drvdata(pdev); 3142 struct net_device *netdev = pci_get_drvdata(pdev);
2951 struct jme_adapter *jme = netdev_priv(netdev); 3143 struct jme_adapter *jme = netdev_priv(netdev);
2952 3144
@@ -2965,7 +3157,6 @@ jme_suspend(struct pci_dev *pdev, pm_message_t state)
2965 jme_polling_mode(jme); 3157 jme_polling_mode(jme);
2966 3158
2967 jme_stop_pcc_timer(jme); 3159 jme_stop_pcc_timer(jme);
2968 jme_reset_ghc_speed(jme);
2969 jme_disable_rx_engine(jme); 3160 jme_disable_rx_engine(jme);
2970 jme_disable_tx_engine(jme); 3161 jme_disable_tx_engine(jme);
2971 jme_reset_mac_processor(jme); 3162 jme_reset_mac_processor(jme);
@@ -2979,33 +3170,20 @@ jme_suspend(struct pci_dev *pdev, pm_message_t state)
2979 tasklet_hi_enable(&jme->rxclean_task); 3170 tasklet_hi_enable(&jme->rxclean_task);
2980 tasklet_hi_enable(&jme->rxempty_task); 3171 tasklet_hi_enable(&jme->rxempty_task);
2981 3172
2982 pci_save_state(pdev); 3173 jme_powersave_phy(jme);
2983 if (jme->reg_pmcs) {
2984 jme_set_100m_half(jme);
2985
2986 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2987 jme_wait_link(jme);
2988
2989 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2990
2991 pci_enable_wake(pdev, PCI_D3cold, true);
2992 } else {
2993 jme_phy_off(jme);
2994 }
2995 pci_set_power_state(pdev, PCI_D3cold);
2996 3174
2997 return 0; 3175 return 0;
2998} 3176}
2999 3177
3000static int 3178static int jme_resume(struct device *dev)
3001jme_resume(struct pci_dev *pdev)
3002{ 3179{
3180 struct pci_dev *pdev = to_pci_dev(dev);
3003 struct net_device *netdev = pci_get_drvdata(pdev); 3181 struct net_device *netdev = pci_get_drvdata(pdev);
3004 struct jme_adapter *jme = netdev_priv(netdev); 3182 struct jme_adapter *jme = netdev_priv(netdev);
3005 3183
3006 jme_clear_pm(jme); 3184 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
3007 pci_restore_state(pdev);
3008 3185
3186 jme_phy_on(jme);
3009 if (test_bit(JME_FLAG_SSET, &jme->flags)) 3187 if (test_bit(JME_FLAG_SSET, &jme->flags))
3010 jme_set_settings(netdev, &jme->old_ecmd); 3188 jme_set_settings(netdev, &jme->old_ecmd);
3011 else 3189 else
@@ -3020,6 +3198,13 @@ jme_resume(struct pci_dev *pdev)
3020 3198
3021 return 0; 3199 return 0;
3022} 3200}
3201
3202static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3203#define JME_PM_OPS (&jme_pm_ops)
3204
3205#else
3206
3207#define JME_PM_OPS NULL
3023#endif 3208#endif
3024 3209
3025static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = { 3210static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
@@ -3033,17 +3218,14 @@ static struct pci_driver jme_driver = {
3033 .id_table = jme_pci_tbl, 3218 .id_table = jme_pci_tbl,
3034 .probe = jme_init_one, 3219 .probe = jme_init_one,
3035 .remove = __devexit_p(jme_remove_one), 3220 .remove = __devexit_p(jme_remove_one),
3036#ifdef CONFIG_PM 3221 .shutdown = jme_shutdown,
3037 .suspend = jme_suspend, 3222 .driver.pm = JME_PM_OPS,
3038 .resume = jme_resume,
3039#endif /* CONFIG_PM */
3040}; 3223};
3041 3224
3042static int __init 3225static int __init
3043jme_init_module(void) 3226jme_init_module(void)
3044{ 3227{
3045 printk(KERN_INFO PFX "JMicron JMC2XX ethernet " 3228 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3046 "driver version %s\n", DRV_VERSION);
3047 return pci_register_driver(&jme_driver); 3229 return pci_register_driver(&jme_driver);
3048} 3230}
3049 3231
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-02 20:29:58 -0400