diff options
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_phy.c')
-rw-r--r-- | drivers/net/ixgbe/ixgbe_phy.c | 622 |
1 files changed, 470 insertions, 152 deletions
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c index 6c0d42e33f21..735f686c3b36 100644 --- a/drivers/net/ixgbe/ixgbe_phy.c +++ b/drivers/net/ixgbe/ixgbe_phy.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | 3 | Intel 10 Gigabit PCI Express Linux driver |
4 | Copyright(c) 1999 - 2010 Intel Corporation. | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms and conditions of the GNU General Public License, | 7 | under the terms and conditions of the GNU General Public License, |
@@ -57,6 +57,7 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) | |||
57 | { | 57 | { |
58 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; | 58 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
59 | u32 phy_addr; | 59 | u32 phy_addr; |
60 | u16 ext_ability = 0; | ||
60 | 61 | ||
61 | if (hw->phy.type == ixgbe_phy_unknown) { | 62 | if (hw->phy.type == ixgbe_phy_unknown) { |
62 | for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { | 63 | for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { |
@@ -65,12 +66,29 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) | |||
65 | ixgbe_get_phy_id(hw); | 66 | ixgbe_get_phy_id(hw); |
66 | hw->phy.type = | 67 | hw->phy.type = |
67 | ixgbe_get_phy_type_from_id(hw->phy.id); | 68 | ixgbe_get_phy_type_from_id(hw->phy.id); |
69 | |||
70 | if (hw->phy.type == ixgbe_phy_unknown) { | ||
71 | hw->phy.ops.read_reg(hw, | ||
72 | MDIO_PMA_EXTABLE, | ||
73 | MDIO_MMD_PMAPMD, | ||
74 | &ext_ability); | ||
75 | if (ext_ability & | ||
76 | (MDIO_PMA_EXTABLE_10GBT | | ||
77 | MDIO_PMA_EXTABLE_1000BT)) | ||
78 | hw->phy.type = | ||
79 | ixgbe_phy_cu_unknown; | ||
80 | else | ||
81 | hw->phy.type = | ||
82 | ixgbe_phy_generic; | ||
83 | } | ||
84 | |||
68 | status = 0; | 85 | status = 0; |
69 | break; | 86 | break; |
70 | } | 87 | } |
71 | } | 88 | } |
72 | /* clear value if nothing found */ | 89 | /* clear value if nothing found */ |
73 | hw->phy.mdio.prtad = 0; | 90 | if (status != 0) |
91 | hw->phy.mdio.prtad = 0; | ||
74 | } else { | 92 | } else { |
75 | status = 0; | 93 | status = 0; |
76 | } | 94 | } |
@@ -115,6 +133,9 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) | |||
115 | case TN1010_PHY_ID: | 133 | case TN1010_PHY_ID: |
116 | phy_type = ixgbe_phy_tn; | 134 | phy_type = ixgbe_phy_tn; |
117 | break; | 135 | break; |
136 | case X540_PHY_ID: | ||
137 | phy_type = ixgbe_phy_aq; | ||
138 | break; | ||
118 | case QT2022_PHY_ID: | 139 | case QT2022_PHY_ID: |
119 | phy_type = ixgbe_phy_qt; | 140 | phy_type = ixgbe_phy_qt; |
120 | break; | 141 | break; |
@@ -135,17 +156,51 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) | |||
135 | **/ | 156 | **/ |
136 | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) | 157 | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) |
137 | { | 158 | { |
159 | u32 i; | ||
160 | u16 ctrl = 0; | ||
161 | s32 status = 0; | ||
162 | |||
163 | if (hw->phy.type == ixgbe_phy_unknown) | ||
164 | status = ixgbe_identify_phy_generic(hw); | ||
165 | |||
166 | if (status != 0 || hw->phy.type == ixgbe_phy_none) | ||
167 | goto out; | ||
168 | |||
138 | /* Don't reset PHY if it's shut down due to overtemp. */ | 169 | /* Don't reset PHY if it's shut down due to overtemp. */ |
139 | if (!hw->phy.reset_if_overtemp && | 170 | if (!hw->phy.reset_if_overtemp && |
140 | (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) | 171 | (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) |
141 | return 0; | 172 | goto out; |
142 | 173 | ||
143 | /* | 174 | /* |
144 | * Perform soft PHY reset to the PHY_XS. | 175 | * Perform soft PHY reset to the PHY_XS. |
145 | * This will cause a soft reset to the PHY | 176 | * This will cause a soft reset to the PHY |
146 | */ | 177 | */ |
147 | return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, | 178 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, |
148 | MDIO_CTRL1_RESET); | 179 | MDIO_MMD_PHYXS, |
180 | MDIO_CTRL1_RESET); | ||
181 | |||
182 | /* | ||
183 | * Poll for reset bit to self-clear indicating reset is complete. | ||
184 | * Some PHYs could take up to 3 seconds to complete and need about | ||
185 | * 1.7 usec delay after the reset is complete. | ||
186 | */ | ||
187 | for (i = 0; i < 30; i++) { | ||
188 | msleep(100); | ||
189 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, | ||
190 | MDIO_MMD_PHYXS, &ctrl); | ||
191 | if (!(ctrl & MDIO_CTRL1_RESET)) { | ||
192 | udelay(2); | ||
193 | break; | ||
194 | } | ||
195 | } | ||
196 | |||
197 | if (ctrl & MDIO_CTRL1_RESET) { | ||
198 | status = IXGBE_ERR_RESET_FAILED; | ||
199 | hw_dbg(hw, "PHY reset polling failed to complete.\n"); | ||
200 | } | ||
201 | |||
202 | out: | ||
203 | return status; | ||
149 | } | 204 | } |
150 | 205 | ||
151 | /** | 206 | /** |
@@ -168,7 +223,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | |||
168 | else | 223 | else |
169 | gssr = IXGBE_GSSR_PHY0_SM; | 224 | gssr = IXGBE_GSSR_PHY0_SM; |
170 | 225 | ||
171 | if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) | 226 | if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) |
172 | status = IXGBE_ERR_SWFW_SYNC; | 227 | status = IXGBE_ERR_SWFW_SYNC; |
173 | 228 | ||
174 | if (status == 0) { | 229 | if (status == 0) { |
@@ -240,7 +295,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | |||
240 | } | 295 | } |
241 | } | 296 | } |
242 | 297 | ||
243 | ixgbe_release_swfw_sync(hw, gssr); | 298 | hw->mac.ops.release_swfw_sync(hw, gssr); |
244 | } | 299 | } |
245 | 300 | ||
246 | return status; | 301 | return status; |
@@ -266,7 +321,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | |||
266 | else | 321 | else |
267 | gssr = IXGBE_GSSR_PHY0_SM; | 322 | gssr = IXGBE_GSSR_PHY0_SM; |
268 | 323 | ||
269 | if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) | 324 | if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) |
270 | status = IXGBE_ERR_SWFW_SYNC; | 325 | status = IXGBE_ERR_SWFW_SYNC; |
271 | 326 | ||
272 | if (status == 0) { | 327 | if (status == 0) { |
@@ -333,7 +388,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | |||
333 | } | 388 | } |
334 | } | 389 | } |
335 | 390 | ||
336 | ixgbe_release_swfw_sync(hw, gssr); | 391 | hw->mac.ops.release_swfw_sync(hw, gssr); |
337 | } | 392 | } |
338 | 393 | ||
339 | return status; | 394 | return status; |
@@ -347,49 +402,90 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, | |||
347 | **/ | 402 | **/ |
348 | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) | 403 | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) |
349 | { | 404 | { |
350 | s32 status = IXGBE_NOT_IMPLEMENTED; | 405 | s32 status = 0; |
351 | u32 time_out; | 406 | u32 time_out; |
352 | u32 max_time_out = 10; | 407 | u32 max_time_out = 10; |
353 | u16 autoneg_reg; | 408 | u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; |
409 | bool autoneg = false; | ||
410 | ixgbe_link_speed speed; | ||
354 | 411 | ||
355 | /* | 412 | ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); |
356 | * Set advertisement settings in PHY based on autoneg_advertised | 413 | |
357 | * settings. If autoneg_advertised = 0, then advertise default values | 414 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
358 | * tnx devices cannot be "forced" to a autoneg 10G and fail. But can | 415 | /* Set or unset auto-negotiation 10G advertisement */ |
359 | * for a 1G. | 416 | hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, |
360 | */ | 417 | MDIO_MMD_AN, |
361 | hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); | 418 | &autoneg_reg); |
362 | 419 | ||
363 | if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL) | ||
364 | autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; | 420 | autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; |
365 | else | 421 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) |
366 | autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; | 422 | autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; |
423 | |||
424 | hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, | ||
425 | MDIO_MMD_AN, | ||
426 | autoneg_reg); | ||
427 | } | ||
428 | |||
429 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { | ||
430 | /* Set or unset auto-negotiation 1G advertisement */ | ||
431 | hw->phy.ops.read_reg(hw, | ||
432 | IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, | ||
433 | MDIO_MMD_AN, | ||
434 | &autoneg_reg); | ||
435 | |||
436 | autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; | ||
437 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) | ||
438 | autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; | ||
439 | |||
440 | hw->phy.ops.write_reg(hw, | ||
441 | IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, | ||
442 | MDIO_MMD_AN, | ||
443 | autoneg_reg); | ||
444 | } | ||
367 | 445 | ||
368 | hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); | 446 | if (speed & IXGBE_LINK_SPEED_100_FULL) { |
447 | /* Set or unset auto-negotiation 100M advertisement */ | ||
448 | hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, | ||
449 | MDIO_MMD_AN, | ||
450 | &autoneg_reg); | ||
451 | |||
452 | autoneg_reg &= ~(ADVERTISE_100FULL | | ||
453 | ADVERTISE_100HALF); | ||
454 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) | ||
455 | autoneg_reg |= ADVERTISE_100FULL; | ||
456 | |||
457 | hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, | ||
458 | MDIO_MMD_AN, | ||
459 | autoneg_reg); | ||
460 | } | ||
369 | 461 | ||
370 | /* Restart PHY autonegotiation and wait for completion */ | 462 | /* Restart PHY autonegotiation and wait for completion */ |
371 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg); | 463 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, |
464 | MDIO_MMD_AN, &autoneg_reg); | ||
372 | 465 | ||
373 | autoneg_reg |= MDIO_AN_CTRL1_RESTART; | 466 | autoneg_reg |= MDIO_AN_CTRL1_RESTART; |
374 | 467 | ||
375 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg); | 468 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, |
469 | MDIO_MMD_AN, autoneg_reg); | ||
376 | 470 | ||
377 | /* Wait for autonegotiation to finish */ | 471 | /* Wait for autonegotiation to finish */ |
378 | for (time_out = 0; time_out < max_time_out; time_out++) { | 472 | for (time_out = 0; time_out < max_time_out; time_out++) { |
379 | udelay(10); | 473 | udelay(10); |
380 | /* Restart PHY autonegotiation and wait for completion */ | 474 | /* Restart PHY autonegotiation and wait for completion */ |
381 | status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, | 475 | status = hw->phy.ops.read_reg(hw, MDIO_STAT1, |
382 | &autoneg_reg); | 476 | MDIO_MMD_AN, |
477 | &autoneg_reg); | ||
383 | 478 | ||
384 | autoneg_reg &= MDIO_AN_STAT1_COMPLETE; | 479 | autoneg_reg &= MDIO_AN_STAT1_COMPLETE; |
385 | if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { | 480 | if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { |
386 | status = 0; | ||
387 | break; | 481 | break; |
388 | } | 482 | } |
389 | } | 483 | } |
390 | 484 | ||
391 | if (time_out == max_time_out) | 485 | if (time_out == max_time_out) { |
392 | status = IXGBE_ERR_LINK_SETUP; | 486 | status = IXGBE_ERR_LINK_SETUP; |
487 | hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out"); | ||
488 | } | ||
393 | 489 | ||
394 | return status; | 490 | return status; |
395 | } | 491 | } |
@@ -418,6 +514,9 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, | |||
418 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | 514 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
419 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; | 515 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
420 | 516 | ||
517 | if (speed & IXGBE_LINK_SPEED_100_FULL) | ||
518 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; | ||
519 | |||
421 | /* Setup link based on the new speed settings */ | 520 | /* Setup link based on the new speed settings */ |
422 | hw->phy.ops.setup_link(hw); | 521 | hw->phy.ops.setup_link(hw); |
423 | 522 | ||
@@ -425,6 +524,214 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, | |||
425 | } | 524 | } |
426 | 525 | ||
427 | /** | 526 | /** |
527 | * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities | ||
528 | * @hw: pointer to hardware structure | ||
529 | * @speed: pointer to link speed | ||
530 | * @autoneg: boolean auto-negotiation value | ||
531 | * | ||
532 | * Determines the link capabilities by reading the AUTOC register. | ||
533 | */ | ||
534 | s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, | ||
535 | ixgbe_link_speed *speed, | ||
536 | bool *autoneg) | ||
537 | { | ||
538 | s32 status = IXGBE_ERR_LINK_SETUP; | ||
539 | u16 speed_ability; | ||
540 | |||
541 | *speed = 0; | ||
542 | *autoneg = true; | ||
543 | |||
544 | status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, | ||
545 | &speed_ability); | ||
546 | |||
547 | if (status == 0) { | ||
548 | if (speed_ability & MDIO_SPEED_10G) | ||
549 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; | ||
550 | if (speed_ability & MDIO_PMA_SPEED_1000) | ||
551 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; | ||
552 | if (speed_ability & MDIO_PMA_SPEED_100) | ||
553 | *speed |= IXGBE_LINK_SPEED_100_FULL; | ||
554 | } | ||
555 | |||
556 | return status; | ||
557 | } | ||
558 | |||
559 | /** | ||
560 | * ixgbe_check_phy_link_tnx - Determine link and speed status | ||
561 | * @hw: pointer to hardware structure | ||
562 | * | ||
563 | * Reads the VS1 register to determine if link is up and the current speed for | ||
564 | * the PHY. | ||
565 | **/ | ||
566 | s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, | ||
567 | bool *link_up) | ||
568 | { | ||
569 | s32 status = 0; | ||
570 | u32 time_out; | ||
571 | u32 max_time_out = 10; | ||
572 | u16 phy_link = 0; | ||
573 | u16 phy_speed = 0; | ||
574 | u16 phy_data = 0; | ||
575 | |||
576 | /* Initialize speed and link to default case */ | ||
577 | *link_up = false; | ||
578 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | ||
579 | |||
580 | /* | ||
581 | * Check current speed and link status of the PHY register. | ||
582 | * This is a vendor specific register and may have to | ||
583 | * be changed for other copper PHYs. | ||
584 | */ | ||
585 | for (time_out = 0; time_out < max_time_out; time_out++) { | ||
586 | udelay(10); | ||
587 | status = hw->phy.ops.read_reg(hw, | ||
588 | MDIO_STAT1, | ||
589 | MDIO_MMD_VEND1, | ||
590 | &phy_data); | ||
591 | phy_link = phy_data & | ||
592 | IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; | ||
593 | phy_speed = phy_data & | ||
594 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; | ||
595 | if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { | ||
596 | *link_up = true; | ||
597 | if (phy_speed == | ||
598 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) | ||
599 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | ||
600 | break; | ||
601 | } | ||
602 | } | ||
603 | |||
604 | return status; | ||
605 | } | ||
606 | |||
607 | /** | ||
608 | * ixgbe_setup_phy_link_tnx - Set and restart autoneg | ||
609 | * @hw: pointer to hardware structure | ||
610 | * | ||
611 | * Restart autonegotiation and PHY and waits for completion. | ||
612 | **/ | ||
613 | s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) | ||
614 | { | ||
615 | s32 status = 0; | ||
616 | u32 time_out; | ||
617 | u32 max_time_out = 10; | ||
618 | u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; | ||
619 | bool autoneg = false; | ||
620 | ixgbe_link_speed speed; | ||
621 | |||
622 | ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); | ||
623 | |||
624 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { | ||
625 | /* Set or unset auto-negotiation 10G advertisement */ | ||
626 | hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, | ||
627 | MDIO_MMD_AN, | ||
628 | &autoneg_reg); | ||
629 | |||
630 | autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; | ||
631 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) | ||
632 | autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; | ||
633 | |||
634 | hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, | ||
635 | MDIO_MMD_AN, | ||
636 | autoneg_reg); | ||
637 | } | ||
638 | |||
639 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { | ||
640 | /* Set or unset auto-negotiation 1G advertisement */ | ||
641 | hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, | ||
642 | MDIO_MMD_AN, | ||
643 | &autoneg_reg); | ||
644 | |||
645 | autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; | ||
646 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) | ||
647 | autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; | ||
648 | |||
649 | hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, | ||
650 | MDIO_MMD_AN, | ||
651 | autoneg_reg); | ||
652 | } | ||
653 | |||
654 | if (speed & IXGBE_LINK_SPEED_100_FULL) { | ||
655 | /* Set or unset auto-negotiation 100M advertisement */ | ||
656 | hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, | ||
657 | MDIO_MMD_AN, | ||
658 | &autoneg_reg); | ||
659 | |||
660 | autoneg_reg &= ~(ADVERTISE_100FULL | | ||
661 | ADVERTISE_100HALF); | ||
662 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) | ||
663 | autoneg_reg |= ADVERTISE_100FULL; | ||
664 | |||
665 | hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, | ||
666 | MDIO_MMD_AN, | ||
667 | autoneg_reg); | ||
668 | } | ||
669 | |||
670 | /* Restart PHY autonegotiation and wait for completion */ | ||
671 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, | ||
672 | MDIO_MMD_AN, &autoneg_reg); | ||
673 | |||
674 | autoneg_reg |= MDIO_AN_CTRL1_RESTART; | ||
675 | |||
676 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, | ||
677 | MDIO_MMD_AN, autoneg_reg); | ||
678 | |||
679 | /* Wait for autonegotiation to finish */ | ||
680 | for (time_out = 0; time_out < max_time_out; time_out++) { | ||
681 | udelay(10); | ||
682 | /* Restart PHY autonegotiation and wait for completion */ | ||
683 | status = hw->phy.ops.read_reg(hw, MDIO_STAT1, | ||
684 | MDIO_MMD_AN, | ||
685 | &autoneg_reg); | ||
686 | |||
687 | autoneg_reg &= MDIO_AN_STAT1_COMPLETE; | ||
688 | if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) | ||
689 | break; | ||
690 | } | ||
691 | |||
692 | if (time_out == max_time_out) { | ||
693 | status = IXGBE_ERR_LINK_SETUP; | ||
694 | hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out"); | ||
695 | } | ||
696 | |||
697 | return status; | ||
698 | } | ||
699 | |||
700 | /** | ||
701 | * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version | ||
702 | * @hw: pointer to hardware structure | ||
703 | * @firmware_version: pointer to the PHY Firmware Version | ||
704 | **/ | ||
705 | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, | ||
706 | u16 *firmware_version) | ||
707 | { | ||
708 | s32 status = 0; | ||
709 | |||
710 | status = hw->phy.ops.read_reg(hw, TNX_FW_REV, | ||
711 | MDIO_MMD_VEND1, | ||
712 | firmware_version); | ||
713 | |||
714 | return status; | ||
715 | } | ||
716 | |||
717 | /** | ||
718 | * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version | ||
719 | * @hw: pointer to hardware structure | ||
720 | * @firmware_version: pointer to the PHY Firmware Version | ||
721 | **/ | ||
722 | s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, | ||
723 | u16 *firmware_version) | ||
724 | { | ||
725 | s32 status = 0; | ||
726 | |||
727 | status = hw->phy.ops.read_reg(hw, AQ_FW_REV, | ||
728 | MDIO_MMD_VEND1, | ||
729 | firmware_version); | ||
730 | |||
731 | return status; | ||
732 | } | ||
733 | |||
734 | /** | ||
428 | * ixgbe_reset_phy_nl - Performs a PHY reset | 735 | * ixgbe_reset_phy_nl - Performs a PHY reset |
429 | * @hw: pointer to hardware structure | 736 | * @hw: pointer to hardware structure |
430 | **/ | 737 | **/ |
@@ -448,7 +755,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) | |||
448 | &phy_data); | 755 | &phy_data); |
449 | if ((phy_data & MDIO_CTRL1_RESET) == 0) | 756 | if ((phy_data & MDIO_CTRL1_RESET) == 0) |
450 | break; | 757 | break; |
451 | msleep(10); | 758 | usleep_range(10000, 20000); |
452 | } | 759 | } |
453 | 760 | ||
454 | if ((phy_data & MDIO_CTRL1_RESET) != 0) { | 761 | if ((phy_data & MDIO_CTRL1_RESET) != 0) { |
@@ -477,7 +784,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) | |||
477 | case IXGBE_DELAY_NL: | 784 | case IXGBE_DELAY_NL: |
478 | data_offset++; | 785 | data_offset++; |
479 | hw_dbg(hw, "DELAY: %d MS\n", edata); | 786 | hw_dbg(hw, "DELAY: %d MS\n", edata); |
480 | msleep(edata); | 787 | usleep_range(edata * 1000, edata * 2000); |
481 | break; | 788 | break; |
482 | case IXGBE_DATA_NL: | 789 | case IXGBE_DATA_NL: |
483 | hw_dbg(hw, "DATA:\n"); | 790 | hw_dbg(hw, "DATA:\n"); |
@@ -520,11 +827,10 @@ out: | |||
520 | } | 827 | } |
521 | 828 | ||
522 | /** | 829 | /** |
523 | * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns | 830 | * ixgbe_identify_sfp_module_generic - Identifies SFP modules |
524 | * the PHY type. | ||
525 | * @hw: pointer to hardware structure | 831 | * @hw: pointer to hardware structure |
526 | * | 832 | * |
527 | * Searches for and indentifies the SFP module. Assings appropriate PHY type. | 833 | * Searches for and identifies the SFP module and assigns appropriate PHY type. |
528 | **/ | 834 | **/ |
529 | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | 835 | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) |
530 | { | 836 | { |
@@ -545,41 +851,62 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |||
545 | goto out; | 851 | goto out; |
546 | } | 852 | } |
547 | 853 | ||
548 | status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, | 854 | status = hw->phy.ops.read_i2c_eeprom(hw, |
855 | IXGBE_SFF_IDENTIFIER, | ||
549 | &identifier); | 856 | &identifier); |
550 | 857 | ||
551 | if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { | 858 | if (status == IXGBE_ERR_SWFW_SYNC || |
552 | status = IXGBE_ERR_SFP_NOT_PRESENT; | 859 | status == IXGBE_ERR_I2C || |
553 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; | 860 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
554 | if (hw->phy.type != ixgbe_phy_nl) { | 861 | goto err_read_i2c_eeprom; |
555 | hw->phy.id = 0; | ||
556 | hw->phy.type = ixgbe_phy_unknown; | ||
557 | } | ||
558 | goto out; | ||
559 | } | ||
560 | 862 | ||
561 | if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { | 863 | /* LAN ID is needed for sfp_type determination */ |
562 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, | 864 | hw->mac.ops.set_lan_id(hw); |
563 | &comp_codes_1g); | 865 | |
564 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, | 866 | if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { |
565 | &comp_codes_10g); | 867 | hw->phy.type = ixgbe_phy_sfp_unsupported; |
566 | hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, | 868 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
567 | &cable_tech); | 869 | } else { |
568 | 870 | status = hw->phy.ops.read_i2c_eeprom(hw, | |
569 | /* ID Module | 871 | IXGBE_SFF_1GBE_COMP_CODES, |
570 | * ========= | 872 | &comp_codes_1g); |
571 | * 0 SFP_DA_CU | 873 | |
572 | * 1 SFP_SR | 874 | if (status == IXGBE_ERR_SWFW_SYNC || |
573 | * 2 SFP_LR | 875 | status == IXGBE_ERR_I2C || |
574 | * 3 SFP_DA_CORE0 - 82599-specific | 876 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
575 | * 4 SFP_DA_CORE1 - 82599-specific | 877 | goto err_read_i2c_eeprom; |
576 | * 5 SFP_SR/LR_CORE0 - 82599-specific | 878 | |
577 | * 6 SFP_SR/LR_CORE1 - 82599-specific | 879 | status = hw->phy.ops.read_i2c_eeprom(hw, |
578 | * 7 SFP_act_lmt_DA_CORE0 - 82599-specific | 880 | IXGBE_SFF_10GBE_COMP_CODES, |
579 | * 8 SFP_act_lmt_DA_CORE1 - 82599-specific | 881 | &comp_codes_10g); |
580 | * 9 SFP_1g_cu_CORE0 - 82599-specific | 882 | |
581 | * 10 SFP_1g_cu_CORE1 - 82599-specific | 883 | if (status == IXGBE_ERR_SWFW_SYNC || |
582 | */ | 884 | status == IXGBE_ERR_I2C || |
885 | status == IXGBE_ERR_SFP_NOT_PRESENT) | ||
886 | goto err_read_i2c_eeprom; | ||
887 | status = hw->phy.ops.read_i2c_eeprom(hw, | ||
888 | IXGBE_SFF_CABLE_TECHNOLOGY, | ||
889 | &cable_tech); | ||
890 | |||
891 | if (status == IXGBE_ERR_SWFW_SYNC || | ||
892 | status == IXGBE_ERR_I2C || | ||
893 | status == IXGBE_ERR_SFP_NOT_PRESENT) | ||
894 | goto err_read_i2c_eeprom; | ||
895 | |||
896 | /* ID Module | ||
897 | * ========= | ||
898 | * 0 SFP_DA_CU | ||
899 | * 1 SFP_SR | ||
900 | * 2 SFP_LR | ||
901 | * 3 SFP_DA_CORE0 - 82599-specific | ||
902 | * 4 SFP_DA_CORE1 - 82599-specific | ||
903 | * 5 SFP_SR/LR_CORE0 - 82599-specific | ||
904 | * 6 SFP_SR/LR_CORE1 - 82599-specific | ||
905 | * 7 SFP_act_lmt_DA_CORE0 - 82599-specific | ||
906 | * 8 SFP_act_lmt_DA_CORE1 - 82599-specific | ||
907 | * 9 SFP_1g_cu_CORE0 - 82599-specific | ||
908 | * 10 SFP_1g_cu_CORE1 - 82599-specific | ||
909 | */ | ||
583 | if (hw->mac.type == ixgbe_mac_82598EB) { | 910 | if (hw->mac.type == ixgbe_mac_82598EB) { |
584 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) | 911 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
585 | hw->phy.sfp_type = ixgbe_sfp_type_da_cu; | 912 | hw->phy.sfp_type = ixgbe_sfp_type_da_cu; |
@@ -611,31 +938,27 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |||
611 | ixgbe_sfp_type_da_act_lmt_core1; | 938 | ixgbe_sfp_type_da_act_lmt_core1; |
612 | } else { | 939 | } else { |
613 | hw->phy.sfp_type = | 940 | hw->phy.sfp_type = |
614 | ixgbe_sfp_type_unknown; | 941 | ixgbe_sfp_type_unknown; |
615 | } | 942 | } |
616 | } else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) | 943 | } else if (comp_codes_10g & |
617 | if (hw->bus.lan_id == 0) | 944 | (IXGBE_SFF_10GBASESR_CAPABLE | |
618 | hw->phy.sfp_type = | 945 | IXGBE_SFF_10GBASELR_CAPABLE)) { |
619 | ixgbe_sfp_type_srlr_core0; | ||
620 | else | ||
621 | hw->phy.sfp_type = | ||
622 | ixgbe_sfp_type_srlr_core1; | ||
623 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) | ||
624 | if (hw->bus.lan_id == 0) | 946 | if (hw->bus.lan_id == 0) |
625 | hw->phy.sfp_type = | 947 | hw->phy.sfp_type = |
626 | ixgbe_sfp_type_srlr_core0; | 948 | ixgbe_sfp_type_srlr_core0; |
627 | else | 949 | else |
628 | hw->phy.sfp_type = | 950 | hw->phy.sfp_type = |
629 | ixgbe_sfp_type_srlr_core1; | 951 | ixgbe_sfp_type_srlr_core1; |
630 | else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) | 952 | } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { |
631 | if (hw->bus.lan_id == 0) | 953 | if (hw->bus.lan_id == 0) |
632 | hw->phy.sfp_type = | 954 | hw->phy.sfp_type = |
633 | ixgbe_sfp_type_1g_cu_core0; | 955 | ixgbe_sfp_type_1g_cu_core0; |
634 | else | 956 | else |
635 | hw->phy.sfp_type = | 957 | hw->phy.sfp_type = |
636 | ixgbe_sfp_type_1g_cu_core1; | 958 | ixgbe_sfp_type_1g_cu_core1; |
637 | else | 959 | } else { |
638 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; | 960 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
961 | } | ||
639 | } | 962 | } |
640 | 963 | ||
641 | if (hw->phy.sfp_type != stored_sfp_type) | 964 | if (hw->phy.sfp_type != stored_sfp_type) |
@@ -652,16 +975,33 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |||
652 | /* Determine PHY vendor */ | 975 | /* Determine PHY vendor */ |
653 | if (hw->phy.type != ixgbe_phy_nl) { | 976 | if (hw->phy.type != ixgbe_phy_nl) { |
654 | hw->phy.id = identifier; | 977 | hw->phy.id = identifier; |
655 | hw->phy.ops.read_i2c_eeprom(hw, | 978 | status = hw->phy.ops.read_i2c_eeprom(hw, |
656 | IXGBE_SFF_VENDOR_OUI_BYTE0, | 979 | IXGBE_SFF_VENDOR_OUI_BYTE0, |
657 | &oui_bytes[0]); | 980 | &oui_bytes[0]); |
658 | hw->phy.ops.read_i2c_eeprom(hw, | 981 | |
982 | if (status == IXGBE_ERR_SWFW_SYNC || | ||
983 | status == IXGBE_ERR_I2C || | ||
984 | status == IXGBE_ERR_SFP_NOT_PRESENT) | ||
985 | goto err_read_i2c_eeprom; | ||
986 | |||
987 | status = hw->phy.ops.read_i2c_eeprom(hw, | ||
659 | IXGBE_SFF_VENDOR_OUI_BYTE1, | 988 | IXGBE_SFF_VENDOR_OUI_BYTE1, |
660 | &oui_bytes[1]); | 989 | &oui_bytes[1]); |
661 | hw->phy.ops.read_i2c_eeprom(hw, | 990 | |
991 | if (status == IXGBE_ERR_SWFW_SYNC || | ||
992 | status == IXGBE_ERR_I2C || | ||
993 | status == IXGBE_ERR_SFP_NOT_PRESENT) | ||
994 | goto err_read_i2c_eeprom; | ||
995 | |||
996 | status = hw->phy.ops.read_i2c_eeprom(hw, | ||
662 | IXGBE_SFF_VENDOR_OUI_BYTE2, | 997 | IXGBE_SFF_VENDOR_OUI_BYTE2, |
663 | &oui_bytes[2]); | 998 | &oui_bytes[2]); |
664 | 999 | ||
1000 | if (status == IXGBE_ERR_SWFW_SYNC || | ||
1001 | status == IXGBE_ERR_I2C || | ||
1002 | status == IXGBE_ERR_SFP_NOT_PRESENT) | ||
1003 | goto err_read_i2c_eeprom; | ||
1004 | |||
665 | vendor_oui = | 1005 | vendor_oui = |
666 | ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | | 1006 | ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | |
667 | (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | | 1007 | (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | |
@@ -671,7 +1011,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |||
671 | case IXGBE_SFF_VENDOR_OUI_TYCO: | 1011 | case IXGBE_SFF_VENDOR_OUI_TYCO: |
672 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) | 1012 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
673 | hw->phy.type = | 1013 | hw->phy.type = |
674 | ixgbe_phy_sfp_passive_tyco; | 1014 | ixgbe_phy_sfp_passive_tyco; |
675 | break; | 1015 | break; |
676 | case IXGBE_SFF_VENDOR_OUI_FTL: | 1016 | case IXGBE_SFF_VENDOR_OUI_FTL: |
677 | if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) | 1017 | if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) |
@@ -688,7 +1028,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |||
688 | default: | 1028 | default: |
689 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) | 1029 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
690 | hw->phy.type = | 1030 | hw->phy.type = |
691 | ixgbe_phy_sfp_passive_unknown; | 1031 | ixgbe_phy_sfp_passive_unknown; |
692 | else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) | 1032 | else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) |
693 | hw->phy.type = | 1033 | hw->phy.type = |
694 | ixgbe_phy_sfp_active_unknown; | 1034 | ixgbe_phy_sfp_active_unknown; |
@@ -698,7 +1038,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |||
698 | } | 1038 | } |
699 | } | 1039 | } |
700 | 1040 | ||
701 | /* All passive DA cables are supported */ | 1041 | /* Allow any DA cable vendor */ |
702 | if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | | 1042 | if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | |
703 | IXGBE_SFF_DA_ACTIVE_CABLE)) { | 1043 | IXGBE_SFF_DA_ACTIVE_CABLE)) { |
704 | status = 0; | 1044 | status = 0; |
@@ -720,7 +1060,6 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |||
720 | goto out; | 1060 | goto out; |
721 | } | 1061 | } |
722 | 1062 | ||
723 | /* This is guaranteed to be 82599, no need to check for NULL */ | ||
724 | hw->mac.ops.get_device_caps(hw, &enforce_sfp); | 1063 | hw->mac.ops.get_device_caps(hw, &enforce_sfp); |
725 | if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && | 1064 | if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && |
726 | !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || | 1065 | !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || |
@@ -740,15 +1079,24 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) | |||
740 | 1079 | ||
741 | out: | 1080 | out: |
742 | return status; | 1081 | return status; |
1082 | |||
1083 | err_read_i2c_eeprom: | ||
1084 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; | ||
1085 | if (hw->phy.type != ixgbe_phy_nl) { | ||
1086 | hw->phy.id = 0; | ||
1087 | hw->phy.type = ixgbe_phy_unknown; | ||
1088 | } | ||
1089 | return IXGBE_ERR_SFP_NOT_PRESENT; | ||
743 | } | 1090 | } |
744 | 1091 | ||
745 | /** | 1092 | /** |
746 | * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see | 1093 | * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence |
747 | * if it supports a given SFP+ module type, if so it returns the offsets to the | ||
748 | * phy init sequence block. | ||
749 | * @hw: pointer to hardware structure | 1094 | * @hw: pointer to hardware structure |
750 | * @list_offset: offset to the SFP ID list | 1095 | * @list_offset: offset to the SFP ID list |
751 | * @data_offset: offset to the SFP data block | 1096 | * @data_offset: offset to the SFP data block |
1097 | * | ||
1098 | * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if | ||
1099 | * so it returns the offsets to the phy init sequence block. | ||
752 | **/ | 1100 | **/ |
753 | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, | 1101 | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, |
754 | u16 *list_offset, | 1102 | u16 *list_offset, |
@@ -863,11 +1211,22 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | |||
863 | u8 dev_addr, u8 *data) | 1211 | u8 dev_addr, u8 *data) |
864 | { | 1212 | { |
865 | s32 status = 0; | 1213 | s32 status = 0; |
866 | u32 max_retry = 1; | 1214 | u32 max_retry = 10; |
867 | u32 retry = 0; | 1215 | u32 retry = 0; |
1216 | u16 swfw_mask = 0; | ||
868 | bool nack = 1; | 1217 | bool nack = 1; |
869 | 1218 | ||
1219 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) | ||
1220 | swfw_mask = IXGBE_GSSR_PHY1_SM; | ||
1221 | else | ||
1222 | swfw_mask = IXGBE_GSSR_PHY0_SM; | ||
1223 | |||
870 | do { | 1224 | do { |
1225 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { | ||
1226 | status = IXGBE_ERR_SWFW_SYNC; | ||
1227 | goto read_byte_out; | ||
1228 | } | ||
1229 | |||
871 | ixgbe_i2c_start(hw); | 1230 | ixgbe_i2c_start(hw); |
872 | 1231 | ||
873 | /* Device Address and write indication */ | 1232 | /* Device Address and write indication */ |
@@ -910,6 +1269,8 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | |||
910 | break; | 1269 | break; |
911 | 1270 | ||
912 | fail: | 1271 | fail: |
1272 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | ||
1273 | msleep(100); | ||
913 | ixgbe_i2c_bus_clear(hw); | 1274 | ixgbe_i2c_bus_clear(hw); |
914 | retry++; | 1275 | retry++; |
915 | if (retry < max_retry) | 1276 | if (retry < max_retry) |
@@ -919,6 +1280,9 @@ fail: | |||
919 | 1280 | ||
920 | } while (retry < max_retry); | 1281 | } while (retry < max_retry); |
921 | 1282 | ||
1283 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | ||
1284 | |||
1285 | read_byte_out: | ||
922 | return status; | 1286 | return status; |
923 | } | 1287 | } |
924 | 1288 | ||
@@ -937,6 +1301,17 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, | |||
937 | s32 status = 0; | 1301 | s32 status = 0; |
938 | u32 max_retry = 1; | 1302 | u32 max_retry = 1; |
939 | u32 retry = 0; | 1303 | u32 retry = 0; |
1304 | u16 swfw_mask = 0; | ||
1305 | |||
1306 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) | ||
1307 | swfw_mask = IXGBE_GSSR_PHY1_SM; | ||
1308 | else | ||
1309 | swfw_mask = IXGBE_GSSR_PHY0_SM; | ||
1310 | |||
1311 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { | ||
1312 | status = IXGBE_ERR_SWFW_SYNC; | ||
1313 | goto write_byte_out; | ||
1314 | } | ||
940 | 1315 | ||
941 | do { | 1316 | do { |
942 | ixgbe_i2c_start(hw); | 1317 | ixgbe_i2c_start(hw); |
@@ -977,6 +1352,9 @@ fail: | |||
977 | hw_dbg(hw, "I2C byte write error.\n"); | 1352 | hw_dbg(hw, "I2C byte write error.\n"); |
978 | } while (retry < max_retry); | 1353 | } while (retry < max_retry); |
979 | 1354 | ||
1355 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | ||
1356 | |||
1357 | write_byte_out: | ||
980 | return status; | 1358 | return status; |
981 | } | 1359 | } |
982 | 1360 | ||
@@ -1295,6 +1673,8 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) | |||
1295 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); | 1673 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
1296 | u32 i; | 1674 | u32 i; |
1297 | 1675 | ||
1676 | ixgbe_i2c_start(hw); | ||
1677 | |||
1298 | ixgbe_set_i2c_data(hw, &i2cctl, 1); | 1678 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
1299 | 1679 | ||
1300 | for (i = 0; i < 9; i++) { | 1680 | for (i = 0; i < 9; i++) { |
@@ -1309,76 +1689,14 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) | |||
1309 | udelay(IXGBE_I2C_T_LOW); | 1689 | udelay(IXGBE_I2C_T_LOW); |
1310 | } | 1690 | } |
1311 | 1691 | ||
1692 | ixgbe_i2c_start(hw); | ||
1693 | |||
1312 | /* Put the i2c bus back to default state */ | 1694 | /* Put the i2c bus back to default state */ |
1313 | ixgbe_i2c_stop(hw); | 1695 | ixgbe_i2c_stop(hw); |
1314 | } | 1696 | } |
1315 | 1697 | ||
1316 | /** | 1698 | /** |
1317 | * ixgbe_check_phy_link_tnx - Determine link and speed status | 1699 | * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. |
1318 | * @hw: pointer to hardware structure | ||
1319 | * | ||
1320 | * Reads the VS1 register to determine if link is up and the current speed for | ||
1321 | * the PHY. | ||
1322 | **/ | ||
1323 | s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, | ||
1324 | bool *link_up) | ||
1325 | { | ||
1326 | s32 status = 0; | ||
1327 | u32 time_out; | ||
1328 | u32 max_time_out = 10; | ||
1329 | u16 phy_link = 0; | ||
1330 | u16 phy_speed = 0; | ||
1331 | u16 phy_data = 0; | ||
1332 | |||
1333 | /* Initialize speed and link to default case */ | ||
1334 | *link_up = false; | ||
1335 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | ||
1336 | |||
1337 | /* | ||
1338 | * Check current speed and link status of the PHY register. | ||
1339 | * This is a vendor specific register and may have to | ||
1340 | * be changed for other copper PHYs. | ||
1341 | */ | ||
1342 | for (time_out = 0; time_out < max_time_out; time_out++) { | ||
1343 | udelay(10); | ||
1344 | status = hw->phy.ops.read_reg(hw, | ||
1345 | IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, | ||
1346 | MDIO_MMD_VEND1, | ||
1347 | &phy_data); | ||
1348 | phy_link = phy_data & | ||
1349 | IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; | ||
1350 | phy_speed = phy_data & | ||
1351 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; | ||
1352 | if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { | ||
1353 | *link_up = true; | ||
1354 | if (phy_speed == | ||
1355 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) | ||
1356 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | ||
1357 | break; | ||
1358 | } | ||
1359 | } | ||
1360 | |||
1361 | return status; | ||
1362 | } | ||
1363 | |||
1364 | /** | ||
1365 | * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version | ||
1366 | * @hw: pointer to hardware structure | ||
1367 | * @firmware_version: pointer to the PHY Firmware Version | ||
1368 | **/ | ||
1369 | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, | ||
1370 | u16 *firmware_version) | ||
1371 | { | ||
1372 | s32 status = 0; | ||
1373 | |||
1374 | status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1, | ||
1375 | firmware_version); | ||
1376 | |||
1377 | return status; | ||
1378 | } | ||
1379 | |||
1380 | /** | ||
1381 | * ixgbe_tn_check_overtemp - Checks if an overtemp occured. | ||
1382 | * @hw: pointer to hardware structure | 1700 | * @hw: pointer to hardware structure |
1383 | * | 1701 | * |
1384 | * Checks if the LASI temp alarm status was triggered due to overtemp | 1702 | * Checks if the LASI temp alarm status was triggered due to overtemp |