1 files changed, 148 insertions, 165 deletions

diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 25b02fb425ac..d50cf78c234d 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 10 Gigabit PCI Express Linux driver
-  Copyright(c) 1999 - 2010 Intel Corporation.
+  Copyright(c) 1999 - 2011 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -31,115 +31,79 @@
 #include "ixgbe_dcb_82599.h"
 
 /**
- * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
+ * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers
  * @hw: pointer to hardware structure
- * @stats: pointer to statistics structure
- * @tc_count:  Number of elements in bwg_array.
+ * @rx_pba: method to distribute packet buffer
  *
- * This function returns the status data for each of the Traffic Classes in use.
+ * Configure packet buffers for DCB mode.
  */
-s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
-                                 struct ixgbe_hw_stats *stats,
-                                 u8 tc_count)
+static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, u8 rx_pba)
 {
-        int tc;
-
-        if (tc_count > MAX_TRAFFIC_CLASS)
-                return DCB_ERR_PARAM;
-        /* Statistics pertaining to each traffic class */
-        for (tc = 0; tc < tc_count; tc++) {
-                /* Transmitted Packets */
-                stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
-                /* Transmitted Bytes */
-                stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
-                /* Received Packets */
-                stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
-                /* Received Bytes */
-                stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
-        }
-
-        return 0;
-}
+        int num_tcs = IXGBE_MAX_PACKET_BUFFERS;
+        u32 rx_pb_size = hw->mac.rx_pb_size << IXGBE_RXPBSIZE_SHIFT;
+        u32 rxpktsize;
+        u32 txpktsize;
+        u32 txpbthresh;
+        u8  i = 0;
 
-/**
- * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data
- * @hw: pointer to hardware structure
- * @stats: pointer to statistics structure
- * @tc_count:  Number of elements in bwg_array.
- *
- * This function returns the CBFC status data for each of the Traffic Classes.
- */
-s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
-                                  struct ixgbe_hw_stats *stats,
-                                  u8 tc_count)
-{
-        int tc;
-
-        if (tc_count > MAX_TRAFFIC_CLASS)
-                return DCB_ERR_PARAM;
-        for (tc = 0; tc < tc_count; tc++) {
-                /* Priority XOFF Transmitted */
-                stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
-                /* Priority XOFF Received */
-                stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
+        /*
+         * This really means configure the first half of the TCs
+         * (Traffic Classes) to use 5/8 of the Rx packet buffer
+         * space.  To determine the size of the buffer for each TC,
+         * we are multiplying the average size by 5/4 and applying
+         * it to half of the traffic classes.
+         */
+        if (rx_pba == pba_80_48) {
+                rxpktsize = (rx_pb_size * 5) / (num_tcs * 4);
+                rx_pb_size -= rxpktsize * (num_tcs / 2);
+                for (; i < (num_tcs / 2); i++)
+                        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
         }
 
-        return 0;
-}
+        /* Divide the remaining Rx packet buffer evenly among the TCs */
+        rxpktsize = rx_pb_size / (num_tcs - i);
+        for (; i < num_tcs; i++)
+                IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
 
-/**
- * ixgbe_dcb_config_packet_buffers_82599 - Configure DCB packet buffers
- * @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
- *
- * Configure packet buffers for DCB mode.
- */
-s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw,
-                                          struct ixgbe_dcb_config *dcb_config)
-{
-        s32 ret_val = 0;
-        u32 value = IXGBE_RXPBSIZE_64KB;
-        u8  i = 0;
+        /*
+         * Setup Tx packet buffer and threshold equally for all TCs
+         * TXPBTHRESH register is set in K so divide by 1024 and subtract
+         * 10 since the largest packet we support is just over 9K.
+         */
+        txpktsize = IXGBE_TXPBSIZE_MAX / num_tcs;
+        txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
+        for (i = 0; i < num_tcs; i++) {
+                IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
+                IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
+        }
 
-        /* Setup Rx packet buffer sizes */
-        switch (dcb_config->rx_pba_cfg) {
-        case pba_80_48:
-                /* Setup the first four at 80KB */
-                value = IXGBE_RXPBSIZE_80KB;
-                for (; i < 4; i++)
-                        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
-                /* Setup the last four at 48KB...don't re-init i */
-                value = IXGBE_RXPBSIZE_48KB;
-                /* Fall Through */
-        case pba_equal:
-        default:
-                for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
-                        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
-
-                /* Setup Tx packet buffer sizes */
-                for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
-                        IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
-                                        IXGBE_TXPBSIZE_20KB);
-                        IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i),
-                                        IXGBE_TXPBTHRESH_DCB);
-                }
-                break;
+        /* Clear unused TCs, if any, to zero buffer size*/
+        for (; i < MAX_TRAFFIC_CLASS; i++) {
+                IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
+                IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
+                IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
         }
 
-        return ret_val;
+        return 0;
 }
 
 /**
  * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
  * @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @prio_type: priority type indexed by traffic class
  *
  * Configure Rx Packet Arbiter and credits for each traffic class.
  */
 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
-                                      struct ixgbe_dcb_config *dcb_config)
+                                      u16 *refill,
+                                      u16 *max,
+                                      u8 *bwg_id,
+                                      u8 *prio_type,
+                                      u8 *prio_tc)
 {
-        struct tc_bw_alloc    *p;
         u32    reg           = 0;
         u32    credit_refill = 0;
         u32    credit_max    = 0;
@@ -155,20 +119,18 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
         /* Map all traffic classes to their UP, 1 to 1 */
         reg = 0;
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
-                reg |= (i << (i * IXGBE_RTRUP2TC_UP_SHIFT));
+                reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
         IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
-
-                credit_refill = p->data_credits_refill;
-                credit_max    = p->data_credits_max;
+                credit_refill = refill[i];
+                credit_max    = max[i];
                 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
 
-                reg |= (u32)(p->bwg_id) << IXGBE_RTRPT4C_BWG_SHIFT;
+                reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_RTRPT4C_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
@@ -187,14 +149,19 @@ s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
 /**
  * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
  * @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @prio_type: priority type indexed by traffic class
  *
  * Configure Tx Descriptor Arbiter and credits for each traffic class.
  */
 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
-                                           struct ixgbe_dcb_config *dcb_config)
+                                           u16 *refill,
+                                           u16 *max,
+                                           u8 *bwg_id,
+                                           u8 *prio_type)
 {
-        struct tc_bw_alloc *p;
         u32    reg, max_credits;
         u8     i;
 
@@ -206,16 +173,15 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
-                max_credits = dcb_config->tc_config[i].desc_credits_max;
+                max_credits = max[i];
                 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
-                reg |= p->data_credits_refill;
-                reg |= (u32)(p->bwg_id) << IXGBE_RTTDT2C_BWG_SHIFT;
+                reg |= refill[i];
+                reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
 
-                if (p->prio_type == prio_group)
+                if (prio_type[i] == prio_group)
                         reg |= IXGBE_RTTDT2C_GSP;
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_RTTDT2C_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
@@ -234,14 +200,20 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
 /**
  * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
  * @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @prio_type: priority type indexed by traffic class
  *
  * Configure Tx Packet Arbiter and credits for each traffic class.
  */
 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
-                                           struct ixgbe_dcb_config *dcb_config)
+                                           u16 *refill,
+                                           u16 *max,
+                                           u8 *bwg_id,
+                                           u8 *prio_type,
+                                           u8 *prio_tc)
 {
-        struct tc_bw_alloc *p;
         u32 reg;
         u8 i;
 
@@ -257,20 +229,19 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
         /* Map all traffic classes to their UP, 1 to 1 */
         reg = 0;
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
-                reg |= (i << (i * IXGBE_RTTUP2TC_UP_SHIFT));
+                reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
         IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
-                reg = p->data_credits_refill;
-                reg |= (u32)(p->data_credits_max) << IXGBE_RTTPT2C_MCL_SHIFT;
-                reg |= (u32)(p->bwg_id) << IXGBE_RTTPT2C_BWG_SHIFT;
+                reg = refill[i];
+                reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
+                reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
 
-                if (p->prio_type == prio_group)
+                if (prio_type[i] == prio_group)
                         reg |= IXGBE_RTTPT2C_GSP;
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_RTTPT2C_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
@@ -290,65 +261,64 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
 /**
  * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
  * @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @pfc_en: enabled pfc bitmask
  *
  * Configure Priority Flow Control (PFC) for each traffic class.
  */
-s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw,
-                               struct ixgbe_dcb_config *dcb_config)
+s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
 {
         u32 i, reg, rx_pba_size;
 
-        /* If PFC is disabled globally then fall back to LFC. */
-        if (!dcb_config->pfc_mode_enable) {
-                for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
-                        hw->mac.ops.fc_enable(hw, i);
-                goto out;
-        }
-
         /* Configure PFC Tx thresholds per TC */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                if (dcb_config->rx_pba_cfg == pba_equal)
-                        rx_pba_size = IXGBE_RXPBSIZE_64KB;
-                else
-                        rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB
-                                              : IXGBE_RXPBSIZE_48KB;
+                int enabled = pfc_en & (1 << i);
+                rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
+                rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
 
-                reg = ((rx_pba_size >> 5) & 0xFFE0);
-                if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full ||
-                    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx)
+                reg = (rx_pba_size - hw->fc.low_water) << 10;
+
+                if (enabled)
                         reg |= IXGBE_FCRTL_XONE;
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
 
-                reg = ((rx_pba_size >> 2) & 0xFFE0);
-                if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full ||
-                    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx)
+                reg = (rx_pba_size - hw->fc.high_water) << 10;
+                if (enabled)
                         reg |= IXGBE_FCRTH_FCEN;
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
         }
 
-        /* Configure pause time (2 TCs per register) */
-        reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
-        for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
-                IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
+        if (pfc_en) {
+                /* Configure pause time (2 TCs per register) */
+                reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
+                for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
+                        IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
 
-        /* Configure flow control refresh threshold value */
-        IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
+                /* Configure flow control refresh threshold value */
+                IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
 
-        /* Enable Transmit PFC */
-        reg = IXGBE_FCCFG_TFCE_PRIORITY;
-        IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
 
-        /*
-         * Enable Receive PFC
-         * We will always honor XOFF frames we receive when
-         * we are in PFC mode.
-         */
-        reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
-        reg &= ~IXGBE_MFLCN_RFCE;
-        reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
-        IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
-out:
+                reg = IXGBE_FCCFG_TFCE_PRIORITY;
+                IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
+                /*
+                 * Enable Receive PFC
+                 * 82599 will always honor XOFF frames we receive when
+                 * we are in PFC mode however X540 only honors enabled
+                 * traffic classes.
+                 */
+                reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
+                reg &= ~IXGBE_MFLCN_RFCE;
+                reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
+
+                if (hw->mac.type == ixgbe_mac_X540)
+                        reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
+
+                IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
+
+        } else {
+                for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
+                        hw->mac.ops.fc_enable(hw, i);
+        }
+
         return 0;
 }
 
@@ -359,7 +329,7 @@ out:
  * Configure queue statistics registers, all queues belonging to same traffic
  * class uses a single set of queue statistics counters.
  */
-s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
+static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
 {
         u32 reg = 0;
         u8  i   = 0;
@@ -408,11 +378,10 @@ s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
 /**
  * ixgbe_dcb_config_82599 - Configure general DCB parameters
  * @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
  *
  * Configure general DCB parameters.
  */
-s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw)
+static s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw)
 {
         u32 reg;
         u32 q;
@@ -454,25 +423,39 @@ s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw)
         reg &= ~IXGBE_RTTDCS_ARBDIS;
         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
 
+        /* Enable Security TX Buffer IFG for DCB */
+        reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
+        reg |= IXGBE_SECTX_DCB;
+        IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
+
         return 0;
 }
 
 /**
  * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
  * @hw: pointer to hardware structure
- * @dcb_config: pointer to ixgbe_dcb_config structure
+ * @rx_pba: method to distribute packet buffer
+ * @refill: refill credits index by traffic class
+ * @max: max credits index by traffic class
+ * @bwg_id: bandwidth grouping indexed by traffic class
+ * @prio_type: priority type indexed by traffic class
+ * @pfc_en: enabled pfc bitmask
  *
  * Configure dcb settings and enable dcb mode.
  */
 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
-                              struct ixgbe_dcb_config *dcb_config)
+                              u8 rx_pba, u8 pfc_en, u16 *refill,
+                              u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
 {
-        ixgbe_dcb_config_packet_buffers_82599(hw, dcb_config);
+        ixgbe_dcb_config_packet_buffers_82599(hw, rx_pba);
         ixgbe_dcb_config_82599(hw);
-        ixgbe_dcb_config_rx_arbiter_82599(hw, dcb_config);
-        ixgbe_dcb_config_tx_desc_arbiter_82599(hw, dcb_config);
-        ixgbe_dcb_config_tx_data_arbiter_82599(hw, dcb_config);
-        ixgbe_dcb_config_pfc_82599(hw, dcb_config);
+        ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
+                                          prio_type, prio_tc);
+        ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
+                                               bwg_id, prio_type);
+        ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
+                                               bwg_id, prio_type, prio_tc);
+        ixgbe_dcb_config_pfc_82599(hw, pfc_en);
         ixgbe_dcb_config_tc_stats_82599(hw);
 
         return 0;