1 files changed, 70 insertions, 133 deletions

diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ixgbe/ixgbe_dcb_82598.c
index f0e9279d4669..771d01a60d06 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 10 Gigabit PCI Express Linux driver
-  Copyright(c) 1999 - 2010 Intel Corporation.
+  Copyright(c) 1999 - 2011 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -32,80 +32,20 @@
 #include "ixgbe_dcb_82598.h"
 
 /**
- * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
- * @hw: pointer to hardware structure
- * @stats: pointer to statistics structure
- * @tc_count:  Number of elements in bwg_array.
- *
- * This function returns the status data for each of the Traffic Classes in use.
- */
-s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
-                                 struct ixgbe_hw_stats *stats,
-                                 u8 tc_count)
-{
-        int tc;
-
-        if (tc_count > MAX_TRAFFIC_CLASS)
-                return DCB_ERR_PARAM;
-
-        /* Statistics pertaining to each traffic class */
-        for (tc = 0; tc < tc_count; tc++) {
-                /* Transmitted Packets */
-                stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
-                /* Transmitted Bytes */
-                stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
-                /* Received Packets */
-                stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
-                /* Received Bytes */
-                stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
-        }
-
-        return 0;
-}
-
-/**
- * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
- * @hw: pointer to hardware structure
- * @stats: pointer to statistics structure
- * @tc_count:  Number of elements in bwg_array.
- *
- * This function returns the CBFC status data for each of the Traffic Classes.
- */
-s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
-                                  struct ixgbe_hw_stats *stats,
-                                  u8 tc_count)
-{
-        int tc;
-
-        if (tc_count > MAX_TRAFFIC_CLASS)
-                return DCB_ERR_PARAM;
-
-        for (tc = 0; tc < tc_count; tc++) {
-                /* Priority XOFF Transmitted */
-                stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
-                /* Priority XOFF Received */
-                stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
-        }
-
-        return 0;
-}
-
-/**
  * ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers
  * @hw: pointer to hardware structure
  * @dcb_config: pointer to ixgbe_dcb_config structure
  *
  * Configure packet buffers for DCB mode.
  */
-static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
-                                                 struct ixgbe_dcb_config *dcb_config)
+static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw, u8 rx_pba)
 {
         s32 ret_val = 0;
         u32 value = IXGBE_RXPBSIZE_64KB;
         u8  i = 0;
 
         /* Setup Rx packet buffer sizes */
-        switch (dcb_config->rx_pba_cfg) {
+        switch (rx_pba) {
         case pba_80_48:
                 /* Setup the first four at 80KB */
                 value = IXGBE_RXPBSIZE_80KB;
@@ -138,9 +78,10 @@ static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
  * Configure Rx Data Arbiter and credits for each traffic class.
  */
 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
-                                      struct ixgbe_dcb_config *dcb_config)
+                                        u16 *refill,
+                                        u16 *max,
+                                        u8 *prio_type)
 {
-        struct tc_bw_alloc    *p;
         u32    reg           = 0;
         u32    credit_refill = 0;
         u32    credit_max    = 0;
@@ -161,13 +102,12 @@ s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
-                credit_refill = p->data_credits_refill;
-                credit_max    = p->data_credits_max;
+                credit_refill = refill[i];
+                credit_max    = max[i];
 
                 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_RT2CR_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
@@ -195,9 +135,11 @@ s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
  * Configure Tx Descriptor Arbiter and credits for each traffic class.
  */
 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
-                                           struct ixgbe_dcb_config *dcb_config)
+                                                u16 *refill,
+                                                u16 *max,
+                                                u8 *bwg_id,
+                                                u8 *prio_type)
 {
-        struct tc_bw_alloc *p;
         u32    reg, max_credits;
         u8     i;
 
@@ -205,10 +147,8 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
 
         /* Enable arbiter */
         reg &= ~IXGBE_DPMCS_ARBDIS;
-        if (!(dcb_config->round_robin_enable)) {
-                /* Enable DFP and Recycle mode */
-                reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
-        }
+        /* Enable DFP and Recycle mode */
+        reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
         reg |= IXGBE_DPMCS_TSOEF;
         /* Configure Max TSO packet size 34KB including payload and headers */
         reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
@@ -217,16 +157,15 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
-                max_credits = dcb_config->tc_config[i].desc_credits_max;
+                max_credits = max[i];
                 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
-                reg |= p->data_credits_refill;
-                reg |= (u32)(p->bwg_id) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
+                reg |= refill[i];
+                reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
 
-                if (p->prio_type == prio_group)
+                if (prio_type[i] == prio_group)
                         reg |= IXGBE_TDTQ2TCCR_GSP;
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_TDTQ2TCCR_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
@@ -243,9 +182,11 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
  * Configure Tx Data Arbiter and credits for each traffic class.
  */
 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
-                                           struct ixgbe_dcb_config *dcb_config)
+                                                u16 *refill,
+                                                u16 *max,
+                                                u8 *bwg_id,
+                                                u8 *prio_type)
 {
-        struct tc_bw_alloc *p;
         u32 reg;
         u8 i;
 
@@ -259,15 +200,14 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
 
         /* Configure traffic class credits and priority */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
-                reg = p->data_credits_refill;
-                reg |= (u32)(p->data_credits_max) << IXGBE_TDPT2TCCR_MCL_SHIFT;
-                reg |= (u32)(p->bwg_id) << IXGBE_TDPT2TCCR_BWG_SHIFT;
+                reg = refill[i];
+                reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
+                reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
 
-                if (p->prio_type == prio_group)
+                if (prio_type[i] == prio_group)
                         reg |= IXGBE_TDPT2TCCR_GSP;
 
-                if (p->prio_type == prio_link)
+                if (prio_type[i] == prio_link)
                         reg |= IXGBE_TDPT2TCCR_LSP;
 
                 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
@@ -288,63 +228,57 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
  *
  * Configure Priority Flow Control for each traffic class.
  */
-s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
-                               struct ixgbe_dcb_config *dcb_config)
+s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
 {
         u32 reg, rx_pba_size;
         u8  i;
 
-        if (!dcb_config->pfc_mode_enable)
-                goto out;
-
-        /* Enable Transmit Priority Flow Control */
-        reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
-        reg &= ~IXGBE_RMCS_TFCE_802_3X;
-        /* correct the reporting of our flow control status */
-        reg |= IXGBE_RMCS_TFCE_PRIORITY;
-        IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
-
-        /* Enable Receive Priority Flow Control */
-        reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
-        reg &= ~IXGBE_FCTRL_RFCE;
-        reg |= IXGBE_FCTRL_RPFCE;
-        IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
+        if (pfc_en) {
+                /* Enable Transmit Priority Flow Control */
+                reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
+                reg &= ~IXGBE_RMCS_TFCE_802_3X;
+                /* correct the reporting of our flow control status */
+                reg |= IXGBE_RMCS_TFCE_PRIORITY;
+                IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
+
+                /* Enable Receive Priority Flow Control */
+                reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
+                reg &= ~IXGBE_FCTRL_RFCE;
+                reg |= IXGBE_FCTRL_RPFCE;
+                IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
+
+                /* Configure pause time */
+                for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
+                        IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
+
+                /* Configure flow control refresh threshold value */
+                IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
+        }
 
         /*
          * Configure flow control thresholds and enable priority flow control
          * for each traffic class.
          */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                if (dcb_config->rx_pba_cfg == pba_equal) {
-                        rx_pba_size = IXGBE_RXPBSIZE_64KB;
-                } else {
-                        rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB
-                                              : IXGBE_RXPBSIZE_48KB;
-                }
+                int enabled = pfc_en & (1 << i);
+                rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
+                rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
+                reg = (rx_pba_size - hw->fc.low_water) << 10;
 
-                reg = ((rx_pba_size >> 5) &  0xFFF0);
-                if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
-                    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
+                if (enabled == pfc_enabled_tx ||
+                    enabled == pfc_enabled_full)
                         reg |= IXGBE_FCRTL_XONE;
 
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
 
-                reg = ((rx_pba_size >> 2) & 0xFFF0);
-                if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
-                    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
+                reg = (rx_pba_size - hw->fc.high_water) << 10;
+                if (enabled == pfc_enabled_tx ||
+                    enabled == pfc_enabled_full)
                         reg |= IXGBE_FCRTH_FCEN;
 
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
         }
 
-        /* Configure pause time */
-        for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
-                IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
-
-        /* Configure flow control refresh threshold value */
-        IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
-
-out:
         return 0;
 }
 
@@ -355,7 +289,7 @@ out:
  * Configure queue statistics registers, all queues belonging to same traffic
  * class uses a single set of queue statistics counters.
  */
-s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
+static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
 {
         u32 reg = 0;
         u8  i   = 0;
@@ -388,13 +322,16 @@ s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
  * Configure dcb settings and enable dcb mode.
  */
 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
-                              struct ixgbe_dcb_config *dcb_config)
+                              u8 rx_pba, u8 pfc_en, u16 *refill,
+                              u16 *max, u8 *bwg_id, u8 *prio_type)
 {
-        ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config);
-        ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
-        ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
-        ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
-        ixgbe_dcb_config_pfc_82598(hw, dcb_config);
+        ixgbe_dcb_config_packet_buffers_82598(hw, rx_pba);
+        ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
+        ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
+                                               bwg_id, prio_type);
+        ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
+                                               bwg_id, prio_type);
+        ixgbe_dcb_config_pfc_82598(hw, pfc_en);
         ixgbe_dcb_config_tc_stats_82598(hw);
 
         return 0;