diff options
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_common.c')
-rw-r--r-- | drivers/net/ixgbe/ixgbe_common.c | 232 |
1 files changed, 178 insertions, 54 deletions
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c index 6621e172df3d..40ff120a9ad4 100644 --- a/drivers/net/ixgbe/ixgbe_common.c +++ b/drivers/net/ixgbe/ixgbe_common.c | |||
@@ -1355,9 +1355,7 @@ static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) | |||
1355 | /** | 1355 | /** |
1356 | * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses | 1356 | * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses |
1357 | * @hw: pointer to hardware structure | 1357 | * @hw: pointer to hardware structure |
1358 | * @addr_list: the list of new addresses | 1358 | * @uc_list: the list of new addresses |
1359 | * @addr_count: number of addresses | ||
1360 | * @next: iterator function to walk the address list | ||
1361 | * | 1359 | * |
1362 | * The given list replaces any existing list. Clears the secondary addrs from | 1360 | * The given list replaces any existing list. Clears the secondary addrs from |
1363 | * receive address registers. Uses unused receive address registers for the | 1361 | * receive address registers. Uses unused receive address registers for the |
@@ -1663,7 +1661,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1663 | #endif /* CONFIG_DCB */ | 1661 | #endif /* CONFIG_DCB */ |
1664 | default: | 1662 | default: |
1665 | hw_dbg(hw, "Flow control param set incorrectly\n"); | 1663 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
1666 | ret_val = -IXGBE_ERR_CONFIG; | 1664 | ret_val = IXGBE_ERR_CONFIG; |
1667 | goto out; | 1665 | goto out; |
1668 | break; | 1666 | break; |
1669 | } | 1667 | } |
@@ -1734,75 +1732,140 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) | |||
1734 | s32 ret_val = 0; | 1732 | s32 ret_val = 0; |
1735 | ixgbe_link_speed speed; | 1733 | ixgbe_link_speed speed; |
1736 | u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; | 1734 | u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; |
1735 | u32 links2, anlp1_reg, autoc_reg, links; | ||
1737 | bool link_up; | 1736 | bool link_up; |
1738 | 1737 | ||
1739 | /* | 1738 | /* |
1740 | * AN should have completed when the cable was plugged in. | 1739 | * AN should have completed when the cable was plugged in. |
1741 | * Look for reasons to bail out. Bail out if: | 1740 | * Look for reasons to bail out. Bail out if: |
1742 | * - FC autoneg is disabled, or if | 1741 | * - FC autoneg is disabled, or if |
1743 | * - we don't have multispeed fiber, or if | 1742 | * - link is not up. |
1744 | * - we're not running at 1G, or if | ||
1745 | * - link is not up, or if | ||
1746 | * - link is up but AN did not complete, or if | ||
1747 | * - link is up and AN completed but timed out | ||
1748 | * | 1743 | * |
1749 | * Since we're being called from an LSC, link is already know to be up. | 1744 | * Since we're being called from an LSC, link is already known to be up. |
1750 | * So use link_up_wait_to_complete=false. | 1745 | * So use link_up_wait_to_complete=false. |
1751 | */ | 1746 | */ |
1752 | hw->mac.ops.check_link(hw, &speed, &link_up, false); | 1747 | hw->mac.ops.check_link(hw, &speed, &link_up, false); |
1753 | linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | 1748 | |
1754 | 1749 | if (hw->fc.disable_fc_autoneg || (!link_up)) { | |
1755 | if (hw->fc.disable_fc_autoneg || | ||
1756 | !hw->phy.multispeed_fiber || | ||
1757 | (speed != IXGBE_LINK_SPEED_1GB_FULL) || | ||
1758 | !link_up || | ||
1759 | ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || | ||
1760 | ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { | ||
1761 | hw->fc.fc_was_autonegged = false; | 1750 | hw->fc.fc_was_autonegged = false; |
1762 | hw->fc.current_mode = hw->fc.requested_mode; | 1751 | hw->fc.current_mode = hw->fc.requested_mode; |
1763 | hw_dbg(hw, "Autoneg FC was skipped.\n"); | ||
1764 | goto out; | 1752 | goto out; |
1765 | } | 1753 | } |
1766 | 1754 | ||
1767 | /* | 1755 | /* |
1756 | * On backplane, bail out if | ||
1757 | * - backplane autoneg was not completed, or if | ||
1758 | * - link partner is not AN enabled | ||
1759 | */ | ||
1760 | if (hw->phy.media_type == ixgbe_media_type_backplane) { | ||
1761 | links = IXGBE_READ_REG(hw, IXGBE_LINKS); | ||
1762 | links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); | ||
1763 | if (((links & IXGBE_LINKS_KX_AN_COMP) == 0) || | ||
1764 | ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)) { | ||
1765 | hw->fc.fc_was_autonegged = false; | ||
1766 | hw->fc.current_mode = hw->fc.requested_mode; | ||
1767 | goto out; | ||
1768 | } | ||
1769 | } | ||
1770 | |||
1771 | /* | ||
1772 | * On multispeed fiber at 1g, bail out if | ||
1773 | * - link is up but AN did not complete, or if | ||
1774 | * - link is up and AN completed but timed out | ||
1775 | */ | ||
1776 | if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) { | ||
1777 | linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | ||
1778 | if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || | ||
1779 | ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { | ||
1780 | hw->fc.fc_was_autonegged = false; | ||
1781 | hw->fc.current_mode = hw->fc.requested_mode; | ||
1782 | goto out; | ||
1783 | } | ||
1784 | } | ||
1785 | |||
1786 | /* | ||
1768 | * Read the AN advertisement and LP ability registers and resolve | 1787 | * Read the AN advertisement and LP ability registers and resolve |
1769 | * local flow control settings accordingly | 1788 | * local flow control settings accordingly |
1770 | */ | 1789 | */ |
1771 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | 1790 | if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && |
1772 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); | 1791 | (hw->phy.media_type != ixgbe_media_type_backplane)) { |
1773 | if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | 1792 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); |
1774 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { | 1793 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); |
1794 | if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1795 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { | ||
1796 | /* | ||
1797 | * Now we need to check if the user selected Rx ONLY | ||
1798 | * of pause frames. In this case, we had to advertise | ||
1799 | * FULL flow control because we could not advertise RX | ||
1800 | * ONLY. Hence, we must now check to see if we need to | ||
1801 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1802 | */ | ||
1803 | if (hw->fc.requested_mode == ixgbe_fc_full) { | ||
1804 | hw->fc.current_mode = ixgbe_fc_full; | ||
1805 | hw_dbg(hw, "Flow Control = FULL.\n"); | ||
1806 | } else { | ||
1807 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1808 | hw_dbg(hw, "Flow Control=RX PAUSE only\n"); | ||
1809 | } | ||
1810 | } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1811 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1812 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1813 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1814 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1815 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1816 | } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1817 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1818 | !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1819 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1820 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1821 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | ||
1822 | } else { | ||
1823 | hw->fc.current_mode = ixgbe_fc_none; | ||
1824 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1825 | } | ||
1826 | } | ||
1827 | |||
1828 | if (hw->phy.media_type == ixgbe_media_type_backplane) { | ||
1775 | /* | 1829 | /* |
1776 | * Now we need to check if the user selected Rx ONLY | 1830 | * Read the 10g AN autoc and LP ability registers and resolve |
1777 | * of pause frames. In this case, we had to advertise | 1831 | * local flow control settings accordingly |
1778 | * FULL flow control because we could not advertise RX | ||
1779 | * ONLY. Hence, we must now check to see if we need to | ||
1780 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1781 | */ | 1832 | */ |
1782 | if (hw->fc.requested_mode == ixgbe_fc_full) { | 1833 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1783 | hw->fc.current_mode = ixgbe_fc_full; | 1834 | anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); |
1784 | hw_dbg(hw, "Flow Control = FULL.\n"); | 1835 | |
1785 | } else { | 1836 | if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && |
1837 | (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) { | ||
1838 | /* | ||
1839 | * Now we need to check if the user selected Rx ONLY | ||
1840 | * of pause frames. In this case, we had to advertise | ||
1841 | * FULL flow control because we could not advertise RX | ||
1842 | * ONLY. Hence, we must now check to see if we need to | ||
1843 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1844 | */ | ||
1845 | if (hw->fc.requested_mode == ixgbe_fc_full) { | ||
1846 | hw->fc.current_mode = ixgbe_fc_full; | ||
1847 | hw_dbg(hw, "Flow Control = FULL.\n"); | ||
1848 | } else { | ||
1849 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1850 | hw_dbg(hw, "Flow Control=RX PAUSE only\n"); | ||
1851 | } | ||
1852 | } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && | ||
1853 | (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && | ||
1854 | (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && | ||
1855 | (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { | ||
1856 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1857 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1858 | } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && | ||
1859 | (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && | ||
1860 | !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && | ||
1861 | (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { | ||
1786 | hw->fc.current_mode = ixgbe_fc_rx_pause; | 1862 | hw->fc.current_mode = ixgbe_fc_rx_pause; |
1787 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | 1863 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); |
1864 | } else { | ||
1865 | hw->fc.current_mode = ixgbe_fc_none; | ||
1866 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1788 | } | 1867 | } |
1789 | } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1790 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1791 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1792 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1793 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1794 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1795 | } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1796 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1797 | !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1798 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1799 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1800 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | ||
1801 | } else { | ||
1802 | hw->fc.current_mode = ixgbe_fc_none; | ||
1803 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1804 | } | 1868 | } |
1805 | |||
1806 | /* Record that current_mode is the result of a successful autoneg */ | 1869 | /* Record that current_mode is the result of a successful autoneg */ |
1807 | hw->fc.fc_was_autonegged = true; | 1870 | hw->fc.fc_was_autonegged = true; |
1808 | 1871 | ||
@@ -1919,7 +1982,7 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1919 | #endif /* CONFIG_DCB */ | 1982 | #endif /* CONFIG_DCB */ |
1920 | default: | 1983 | default: |
1921 | hw_dbg(hw, "Flow control param set incorrectly\n"); | 1984 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
1922 | ret_val = -IXGBE_ERR_CONFIG; | 1985 | ret_val = IXGBE_ERR_CONFIG; |
1923 | goto out; | 1986 | goto out; |
1924 | break; | 1987 | break; |
1925 | } | 1988 | } |
@@ -1927,9 +1990,6 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1927 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); | 1990 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); |
1928 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); | 1991 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); |
1929 | 1992 | ||
1930 | /* Enable and restart autoneg to inform the link partner */ | ||
1931 | reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; | ||
1932 | |||
1933 | /* Disable AN timeout */ | 1993 | /* Disable AN timeout */ |
1934 | if (hw->fc.strict_ieee) | 1994 | if (hw->fc.strict_ieee) |
1935 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; | 1995 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; |
@@ -1937,6 +1997,70 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1937 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); | 1997 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); |
1938 | hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); | 1998 | hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); |
1939 | 1999 | ||
2000 | /* | ||
2001 | * Set up the 10G flow control advertisement registers so the HW | ||
2002 | * can do fc autoneg once the cable is plugged in. If we end up | ||
2003 | * using 1g instead, this is harmless. | ||
2004 | */ | ||
2005 | reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); | ||
2006 | |||
2007 | /* | ||
2008 | * The possible values of fc.requested_mode are: | ||
2009 | * 0: Flow control is completely disabled | ||
2010 | * 1: Rx flow control is enabled (we can receive pause frames, | ||
2011 | * but not send pause frames). | ||
2012 | * 2: Tx flow control is enabled (we can send pause frames but | ||
2013 | * we do not support receiving pause frames). | ||
2014 | * 3: Both Rx and Tx flow control (symmetric) are enabled. | ||
2015 | * other: Invalid. | ||
2016 | */ | ||
2017 | switch (hw->fc.requested_mode) { | ||
2018 | case ixgbe_fc_none: | ||
2019 | /* Flow control completely disabled by software override. */ | ||
2020 | reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2021 | break; | ||
2022 | case ixgbe_fc_rx_pause: | ||
2023 | /* | ||
2024 | * Rx Flow control is enabled and Tx Flow control is | ||
2025 | * disabled by software override. Since there really | ||
2026 | * isn't a way to advertise that we are capable of RX | ||
2027 | * Pause ONLY, we will advertise that we support both | ||
2028 | * symmetric and asymmetric Rx PAUSE. Later, we will | ||
2029 | * disable the adapter's ability to send PAUSE frames. | ||
2030 | */ | ||
2031 | reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2032 | break; | ||
2033 | case ixgbe_fc_tx_pause: | ||
2034 | /* | ||
2035 | * Tx Flow control is enabled, and Rx Flow control is | ||
2036 | * disabled by software override. | ||
2037 | */ | ||
2038 | reg |= (IXGBE_AUTOC_ASM_PAUSE); | ||
2039 | reg &= ~(IXGBE_AUTOC_SYM_PAUSE); | ||
2040 | break; | ||
2041 | case ixgbe_fc_full: | ||
2042 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | ||
2043 | reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2044 | break; | ||
2045 | #ifdef CONFIG_DCB | ||
2046 | case ixgbe_fc_pfc: | ||
2047 | goto out; | ||
2048 | break; | ||
2049 | #endif /* CONFIG_DCB */ | ||
2050 | default: | ||
2051 | hw_dbg(hw, "Flow control param set incorrectly\n"); | ||
2052 | ret_val = IXGBE_ERR_CONFIG; | ||
2053 | goto out; | ||
2054 | break; | ||
2055 | } | ||
2056 | /* | ||
2057 | * AUTOC restart handles negotiation of 1G and 10G. There is | ||
2058 | * no need to set the PCS1GCTL register. | ||
2059 | */ | ||
2060 | reg |= IXGBE_AUTOC_AN_RESTART; | ||
2061 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg); | ||
2062 | hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); | ||
2063 | |||
1940 | out: | 2064 | out: |
1941 | return ret_val; | 2065 | return ret_val; |
1942 | } | 2066 | } |
@@ -2000,7 +2124,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |||
2000 | 2124 | ||
2001 | while (timeout) { | 2125 | while (timeout) { |
2002 | if (ixgbe_get_eeprom_semaphore(hw)) | 2126 | if (ixgbe_get_eeprom_semaphore(hw)) |
2003 | return -IXGBE_ERR_SWFW_SYNC; | 2127 | return IXGBE_ERR_SWFW_SYNC; |
2004 | 2128 | ||
2005 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | 2129 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); |
2006 | if (!(gssr & (fwmask | swmask))) | 2130 | if (!(gssr & (fwmask | swmask))) |
@@ -2017,7 +2141,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |||
2017 | 2141 | ||
2018 | if (!timeout) { | 2142 | if (!timeout) { |
2019 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); | 2143 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); |
2020 | return -IXGBE_ERR_SWFW_SYNC; | 2144 | return IXGBE_ERR_SWFW_SYNC; |
2021 | } | 2145 | } |
2022 | 2146 | ||
2023 | gssr |= swmask; | 2147 | gssr |= swmask; |