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Diffstat (limited to 'drivers/net/ixgbe/ixgbe_82599.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c1449
1 files changed, 619 insertions, 830 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index 3e06a61da921..8ee661245af3 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -38,39 +38,38 @@
38#define IXGBE_82599_RAR_ENTRIES 128 38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128 39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128 40#define IXGBE_82599_VFT_TBL_SIZE 128
41 41#define IXGBE_82599_RX_PB_SIZE 512
42void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 42
43void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 43static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 44static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 45static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 ixgbe_link_speed speed, 46static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 bool autoneg, 47 ixgbe_link_speed speed,
48 bool autoneg_wait_to_complete); 48 bool autoneg,
49 bool autoneg_wait_to_complete);
49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 50static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed, 51 ixgbe_link_speed speed,
51 bool autoneg, 52 bool autoneg,
52 bool autoneg_wait_to_complete); 53 bool autoneg_wait_to_complete);
53s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 54static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete); 55 bool autoneg_wait_to_complete);
55s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 56static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed, 57 ixgbe_link_speed speed,
57 bool autoneg, 58 bool autoneg,
58 bool autoneg_wait_to_complete); 59 bool autoneg_wait_to_complete);
59static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed *speed,
61 bool *autoneg);
62static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
63 ixgbe_link_speed speed, 61 ixgbe_link_speed speed,
64 bool autoneg, 62 bool autoneg,
65 bool autoneg_wait_to_complete); 63 bool autoneg_wait_to_complete);
66static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 64static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
65static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
67 66
68static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 67static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
69{ 68{
70 struct ixgbe_mac_info *mac = &hw->mac; 69 struct ixgbe_mac_info *mac = &hw->mac;
71 if (hw->phy.multispeed_fiber) { 70
72 /* Set up dual speed SFP+ support */ 71 /* enable the laser control functions for SFP+ fiber */
73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
74 mac->ops.disable_tx_laser = 73 mac->ops.disable_tx_laser =
75 &ixgbe_disable_tx_laser_multispeed_fiber; 74 &ixgbe_disable_tx_laser_multispeed_fiber;
76 mac->ops.enable_tx_laser = 75 mac->ops.enable_tx_laser =
@@ -80,10 +79,17 @@ static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
80 mac->ops.disable_tx_laser = NULL; 79 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL; 80 mac->ops.enable_tx_laser = NULL;
82 mac->ops.flap_tx_laser = NULL; 81 mac->ops.flap_tx_laser = NULL;
82 }
83
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
87 } else {
83 if ((mac->ops.get_media_type(hw) == 88 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) && 89 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on)) 91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw))
87 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 else 94 else
89 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
@@ -93,6 +99,8 @@ static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
93static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 99static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
94{ 100{
95 s32 ret_val = 0; 101 s32 ret_val = 0;
102 u32 reg_anlp1 = 0;
103 u32 i = 0;
96 u16 list_offset, data_offset, data_value; 104 u16 list_offset, data_offset, data_value;
97 105
98 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
@@ -102,12 +110,12 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
102 110
103 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104 &data_offset); 112 &data_offset);
105
106 if (ret_val != 0) 113 if (ret_val != 0)
107 goto setup_sfp_out; 114 goto setup_sfp_out;
108 115
109 /* PHY config will finish before releasing the semaphore */ 116 /* PHY config will finish before releasing the semaphore */
110 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
111 if (ret_val != 0) { 119 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SWFW_SYNC; 120 ret_val = IXGBE_ERR_SWFW_SYNC;
113 goto setup_sfp_out; 121 goto setup_sfp_out;
@@ -119,14 +127,38 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
119 IXGBE_WRITE_FLUSH(hw); 127 IXGBE_WRITE_FLUSH(hw);
120 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
121 } 129 }
122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
124 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
125 130
126 /* Release the semaphore */ 131 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
128 /* Delay obtaining semaphore again to allow FW access */ 133 /*
129 msleep(hw->eeprom.semaphore_delay); 134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
136 */
137 usleep_range(hw->eeprom.semaphore_delay * 1000,
138 hw->eeprom.semaphore_delay * 2000);
139
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143 IXGBE_AUTOC_AN_RESTART));
144
145 /* Wait for AN to leave state 0 */
146 for (i = 0; i < 10; i++) {
147 usleep_range(4000, 8000);
148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
150 break;
151 }
152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153 hw_dbg(hw, "sfp module setup not complete\n");
154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
155 goto setup_sfp_out;
156 }
157
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161 IXGBE_AUTOC_AN_RESTART));
130 } 162 }
131 163
132setup_sfp_out: 164setup_sfp_out:
@@ -174,7 +206,7 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
174 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
175 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
176 mac->ops.get_link_capabilities = 208 mac->ops.get_link_capabilities =
177 &ixgbe_get_copper_link_capabilities_82599; 209 &ixgbe_get_copper_link_capabilities_generic;
178 } 210 }
179 211
180 /* Set necessary function pointers based on phy type */ 212 /* Set necessary function pointers based on phy type */
@@ -184,6 +216,10 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
184 phy->ops.get_firmware_version = 216 phy->ops.get_firmware_version =
185 &ixgbe_get_phy_firmware_version_tnx; 217 &ixgbe_get_phy_firmware_version_tnx;
186 break; 218 break;
219 case ixgbe_phy_aq:
220 phy->ops.get_firmware_version =
221 &ixgbe_get_phy_firmware_version_generic;
222 break;
187 default: 223 default:
188 break; 224 break;
189 } 225 }
@@ -290,37 +326,6 @@ out:
290} 326}
291 327
292/** 328/**
293 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
294 * @hw: pointer to hardware structure
295 * @speed: pointer to link speed
296 * @autoneg: boolean auto-negotiation value
297 *
298 * Determines the link capabilities by reading the AUTOC register.
299 **/
300static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
301 ixgbe_link_speed *speed,
302 bool *autoneg)
303{
304 s32 status = IXGBE_ERR_LINK_SETUP;
305 u16 speed_ability;
306
307 *speed = 0;
308 *autoneg = true;
309
310 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
311 &speed_ability);
312
313 if (status == 0) {
314 if (speed_ability & MDIO_SPEED_10G)
315 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
316 if (speed_ability & MDIO_PMA_SPEED_1000)
317 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
318 }
319
320 return status;
321}
322
323/**
324 * ixgbe_get_media_type_82599 - Get media type 329 * ixgbe_get_media_type_82599 - Get media type
325 * @hw: pointer to hardware structure 330 * @hw: pointer to hardware structure
326 * 331 *
@@ -331,10 +336,14 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
331 enum ixgbe_media_type media_type; 336 enum ixgbe_media_type media_type;
332 337
333 /* Detect if there is a copper PHY attached. */ 338 /* Detect if there is a copper PHY attached. */
334 if (hw->phy.type == ixgbe_phy_cu_unknown || 339 switch (hw->phy.type) {
335 hw->phy.type == ixgbe_phy_tn) { 340 case ixgbe_phy_cu_unknown:
341 case ixgbe_phy_tn:
342 case ixgbe_phy_aq:
336 media_type = ixgbe_media_type_copper; 343 media_type = ixgbe_media_type_copper;
337 goto out; 344 goto out;
345 default:
346 break;
338 } 347 }
339 348
340 switch (hw->device_id) { 349 switch (hw->device_id) {
@@ -342,17 +351,26 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
342 case IXGBE_DEV_ID_82599_KX4_MEZZ: 351 case IXGBE_DEV_ID_82599_KX4_MEZZ:
343 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
344 case IXGBE_DEV_ID_82599_KR: 353 case IXGBE_DEV_ID_82599_KR:
354 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
345 case IXGBE_DEV_ID_82599_XAUI_LOM: 355 case IXGBE_DEV_ID_82599_XAUI_LOM:
346 /* Default device ID is mezzanine card KX/KX4 */ 356 /* Default device ID is mezzanine card KX/KX4 */
347 media_type = ixgbe_media_type_backplane; 357 media_type = ixgbe_media_type_backplane;
348 break; 358 break;
349 case IXGBE_DEV_ID_82599_SFP: 359 case IXGBE_DEV_ID_82599_SFP:
360 case IXGBE_DEV_ID_82599_SFP_FCOE:
350 case IXGBE_DEV_ID_82599_SFP_EM: 361 case IXGBE_DEV_ID_82599_SFP_EM:
362 case IXGBE_DEV_ID_82599_SFP_SF2:
351 media_type = ixgbe_media_type_fiber; 363 media_type = ixgbe_media_type_fiber;
352 break; 364 break;
353 case IXGBE_DEV_ID_82599_CX4: 365 case IXGBE_DEV_ID_82599_CX4:
354 media_type = ixgbe_media_type_cx4; 366 media_type = ixgbe_media_type_cx4;
355 break; 367 break;
368 case IXGBE_DEV_ID_82599_T3_LOM:
369 media_type = ixgbe_media_type_copper;
370 break;
371 case IXGBE_DEV_ID_82599_LS:
372 media_type = ixgbe_media_type_fiber_lco;
373 break;
356 default: 374 default:
357 media_type = ixgbe_media_type_unknown; 375 media_type = ixgbe_media_type_unknown;
358 break; 376 break;
@@ -369,7 +387,7 @@ out:
369 * Configures link settings based on values in the ixgbe_hw struct. 387 * Configures link settings based on values in the ixgbe_hw struct.
370 * Restarts the link. Performs autonegotiation if needed. 388 * Restarts the link. Performs autonegotiation if needed.
371 **/ 389 **/
372s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 390static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
373 bool autoneg_wait_to_complete) 391 bool autoneg_wait_to_complete)
374{ 392{
375 u32 autoc_reg; 393 u32 autoc_reg;
@@ -410,15 +428,15 @@ s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
410 return status; 428 return status;
411} 429}
412 430
413 /** 431/**
414 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 432 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
415 * @hw: pointer to hardware structure 433 * @hw: pointer to hardware structure
416 * 434 *
417 * The base drivers may require better control over SFP+ module 435 * The base drivers may require better control over SFP+ module
418 * PHY states. This includes selectively shutting down the Tx 436 * PHY states. This includes selectively shutting down the Tx
419 * laser on the PHY, effectively halting physical link. 437 * laser on the PHY, effectively halting physical link.
420 **/ 438 **/
421void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 439static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
422{ 440{
423 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 441 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
424 442
@@ -437,7 +455,7 @@ void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
437 * PHY states. This includes selectively turning on the Tx 455 * PHY states. This includes selectively turning on the Tx
438 * laser on the PHY, effectively starting physical link. 456 * laser on the PHY, effectively starting physical link.
439 **/ 457 **/
440void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 458static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
441{ 459{
442 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 460 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
443 461
@@ -460,10 +478,8 @@ void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
460 * end. This is consistent with true clause 37 autoneg, which also 478 * end. This is consistent with true clause 37 autoneg, which also
461 * involves a loss of signal. 479 * involves a loss of signal.
462 **/ 480 **/
463void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 481static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
464{ 482{
465 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
466
467 if (hw->mac.autotry_restart) { 483 if (hw->mac.autotry_restart) {
468 ixgbe_disable_tx_laser_multispeed_fiber(hw); 484 ixgbe_disable_tx_laser_multispeed_fiber(hw);
469 ixgbe_enable_tx_laser_multispeed_fiber(hw); 485 ixgbe_enable_tx_laser_multispeed_fiber(hw);
@@ -480,23 +496,27 @@ void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
480 * 496 *
481 * Set the link speed in the AUTOC register and restarts link. 497 * Set the link speed in the AUTOC register and restarts link.
482 **/ 498 **/
483s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 499static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
484 ixgbe_link_speed speed, 500 ixgbe_link_speed speed,
485 bool autoneg, 501 bool autoneg,
486 bool autoneg_wait_to_complete) 502 bool autoneg_wait_to_complete)
487{ 503{
488 s32 status = 0; 504 s32 status = 0;
489 ixgbe_link_speed phy_link_speed; 505 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
490 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 506 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
491 u32 speedcnt = 0; 507 u32 speedcnt = 0;
492 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 508 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
509 u32 i = 0;
493 bool link_up = false; 510 bool link_up = false;
494 bool negotiation; 511 bool negotiation;
495 int i;
496 512
497 /* Mask off requested but non-supported speeds */ 513 /* Mask off requested but non-supported speeds */
498 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation); 514 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
499 speed &= phy_link_speed; 515 &negotiation);
516 if (status != 0)
517 return status;
518
519 speed &= link_speed;
500 520
501 /* 521 /*
502 * Try each speed one by one, highest priority first. We do this in 522 * Try each speed one by one, highest priority first. We do this in
@@ -507,9 +527,12 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
507 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 527 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
508 528
509 /* If we already have link at this speed, just jump out */ 529 /* If we already have link at this speed, just jump out */
510 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); 530 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
531 false);
532 if (status != 0)
533 return status;
511 534
512 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 535 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
513 goto out; 536 goto out;
514 537
515 /* Set the module link speed */ 538 /* Set the module link speed */
@@ -521,9 +544,9 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
521 msleep(40); 544 msleep(40);
522 545
523 status = ixgbe_setup_mac_link_82599(hw, 546 status = ixgbe_setup_mac_link_82599(hw,
524 IXGBE_LINK_SPEED_10GB_FULL, 547 IXGBE_LINK_SPEED_10GB_FULL,
525 autoneg, 548 autoneg,
526 autoneg_wait_to_complete); 549 autoneg_wait_to_complete);
527 if (status != 0) 550 if (status != 0)
528 return status; 551 return status;
529 552
@@ -535,14 +558,16 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
535 * Section 73.10.2, we may have to wait up to 500ms if KR is 558 * Section 73.10.2, we may have to wait up to 500ms if KR is
536 * attempted. 82599 uses the same timing for 10g SFI. 559 * attempted. 82599 uses the same timing for 10g SFI.
537 */ 560 */
538
539 for (i = 0; i < 5; i++) { 561 for (i = 0; i < 5; i++) {
540 /* Wait for the link partner to also set speed */ 562 /* Wait for the link partner to also set speed */
541 msleep(100); 563 msleep(100);
542 564
543 /* If we have link, just jump out */ 565 /* If we have link, just jump out */
544 hw->mac.ops.check_link(hw, &phy_link_speed, 566 status = hw->mac.ops.check_link(hw, &link_speed,
545 &link_up, false); 567 &link_up, false);
568 if (status != 0)
569 return status;
570
546 if (link_up) 571 if (link_up)
547 goto out; 572 goto out;
548 } 573 }
@@ -554,9 +579,12 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
554 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 579 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
555 580
556 /* If we already have link at this speed, just jump out */ 581 /* If we already have link at this speed, just jump out */
557 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); 582 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
583 false);
584 if (status != 0)
585 return status;
558 586
559 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 587 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
560 goto out; 588 goto out;
561 589
562 /* Set the module link speed */ 590 /* Set the module link speed */
@@ -569,9 +597,9 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
569 msleep(40); 597 msleep(40);
570 598
571 status = ixgbe_setup_mac_link_82599(hw, 599 status = ixgbe_setup_mac_link_82599(hw,
572 IXGBE_LINK_SPEED_1GB_FULL, 600 IXGBE_LINK_SPEED_1GB_FULL,
573 autoneg, 601 autoneg,
574 autoneg_wait_to_complete); 602 autoneg_wait_to_complete);
575 if (status != 0) 603 if (status != 0)
576 return status; 604 return status;
577 605
@@ -582,7 +610,11 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
582 msleep(100); 610 msleep(100);
583 611
584 /* If we have link, just jump out */ 612 /* If we have link, just jump out */
585 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); 613 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
614 false);
615 if (status != 0)
616 return status;
617
586 if (link_up) 618 if (link_up)
587 goto out; 619 goto out;
588 } 620 }
@@ -625,13 +657,10 @@ static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
625 bool autoneg_wait_to_complete) 657 bool autoneg_wait_to_complete)
626{ 658{
627 s32 status = 0; 659 s32 status = 0;
628 ixgbe_link_speed link_speed; 660 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
629 s32 i, j; 661 s32 i, j;
630 bool link_up = false; 662 bool link_up = false;
631 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 663 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
632 struct ixgbe_adapter *adapter = hw->back;
633
634 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
635 664
636 /* Set autoneg_advertised value based on input link speed */ 665 /* Set autoneg_advertised value based on input link speed */
637 hw->phy.autoneg_advertised = 0; 666 hw->phy.autoneg_advertised = 0;
@@ -657,7 +686,7 @@ static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
657 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 686 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
658 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 687 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
659 autoneg_wait_to_complete); 688 autoneg_wait_to_complete);
660 if (status) 689 if (status != 0)
661 goto out; 690 goto out;
662 691
663 /* 692 /*
@@ -670,8 +699,11 @@ static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
670 mdelay(100); 699 mdelay(100);
671 700
672 /* If we have link, just jump out */ 701 /* If we have link, just jump out */
673 hw->mac.ops.check_link(hw, &link_speed, 702 status = hw->mac.ops.check_link(hw, &link_speed,
674 &link_up, false); 703 &link_up, false);
704 if (status != 0)
705 goto out;
706
675 if (link_up) 707 if (link_up)
676 goto out; 708 goto out;
677 } 709 }
@@ -689,7 +721,7 @@ static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
689 hw->phy.smart_speed_active = true; 721 hw->phy.smart_speed_active = true;
690 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 722 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
691 autoneg_wait_to_complete); 723 autoneg_wait_to_complete);
692 if (status) 724 if (status != 0)
693 goto out; 725 goto out;
694 726
695 /* 727 /*
@@ -702,8 +734,11 @@ static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
702 mdelay(100); 734 mdelay(100);
703 735
704 /* If we have link, just jump out */ 736 /* If we have link, just jump out */
705 hw->mac.ops.check_link(hw, &link_speed, 737 status = hw->mac.ops.check_link(hw, &link_speed,
706 &link_up, false); 738 &link_up, false);
739 if (status != 0)
740 goto out;
741
707 if (link_up) 742 if (link_up)
708 goto out; 743 goto out;
709 } 744 }
@@ -715,7 +750,7 @@ static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
715 750
716out: 751out:
717 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 752 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
718 e_info(hw, "Smartspeed has downgraded the link speed from " 753 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
719 "the maximum advertised\n"); 754 "the maximum advertised\n");
720 return status; 755 return status;
721} 756}
@@ -729,7 +764,7 @@ out:
729 * 764 *
730 * Set the link speed in the AUTOC register and restarts link. 765 * Set the link speed in the AUTOC register and restarts link.
731 **/ 766 **/
732s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 767static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
733 ixgbe_link_speed speed, bool autoneg, 768 ixgbe_link_speed speed, bool autoneg,
734 bool autoneg_wait_to_complete) 769 bool autoneg_wait_to_complete)
735{ 770{
@@ -747,6 +782,9 @@ s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
747 782
748 /* Check to see if speed passed in is supported. */ 783 /* Check to see if speed passed in is supported. */
749 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg); 784 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
785 if (status != 0)
786 goto out;
787
750 speed &= link_capabilities; 788 speed &= link_capabilities;
751 789
752 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 790 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
@@ -760,7 +798,6 @@ s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
760 else 798 else
761 orig_autoc = autoc; 799 orig_autoc = autoc;
762 800
763
764 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 801 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
765 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 802 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
766 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 803 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
@@ -877,7 +914,7 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
877 914
878 /* PHY ops must be identified and initialized prior to reset */ 915 /* PHY ops must be identified and initialized prior to reset */
879 916
880 /* Init PHY and function pointers, perform SFP setup */ 917 /* Identify PHY and related function pointers */
881 status = hw->phy.ops.init(hw); 918 status = hw->phy.ops.init(hw);
882 919
883 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 920 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
@@ -889,6 +926,9 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
889 hw->phy.sfp_setup_needed = false; 926 hw->phy.sfp_setup_needed = false;
890 } 927 }
891 928
929 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
930 goto reset_hw_out;
931
892 /* Reset PHY */ 932 /* Reset PHY */
893 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 933 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
894 hw->phy.ops.reset(hw); 934 hw->phy.ops.reset(hw);
@@ -897,12 +937,9 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
897 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 937 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
898 * access and verify no pending requests before reset 938 * access and verify no pending requests before reset
899 */ 939 */
900 status = ixgbe_disable_pcie_master(hw); 940 ixgbe_disable_pcie_master(hw);
901 if (status != 0) {
902 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
903 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
904 }
905 941
942mac_reset_top:
906 /* 943 /*
907 * Issue global reset to the MAC. This needs to be a SW reset. 944 * Issue global reset to the MAC. This needs to be a SW reset.
908 * If link reset is used, it might reset the MAC when mng is using it 945 * If link reset is used, it might reset the MAC when mng is using it
@@ -923,6 +960,19 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
923 hw_dbg(hw, "Reset polling failed to complete.\n"); 960 hw_dbg(hw, "Reset polling failed to complete.\n");
924 } 961 }
925 962
963 /*
964 * Double resets are required for recovery from certain error
965 * conditions. Between resets, it is necessary to stall to allow time
966 * for any pending HW events to complete. We use 1usec since that is
967 * what is needed for ixgbe_disable_pcie_master(). The second reset
968 * then clears out any effects of those events.
969 */
970 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
971 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
972 udelay(1);
973 goto mac_reset_top;
974 }
975
926 msleep(50); 976 msleep(50);
927 977
928 /* 978 /*
@@ -950,6 +1000,9 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
950 } 1000 }
951 } 1001 }
952 1002
1003 /* Store the permanent mac address */
1004 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1005
953 /* 1006 /*
954 * Store MAC address from RAR0, clear receive address registers, and 1007 * Store MAC address from RAR0, clear receive address registers, and
955 * clear the multicast table. Also reset num_rar_entries to 128, 1008 * clear the multicast table. Also reset num_rar_entries to 128,
@@ -958,9 +1011,6 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
958 hw->mac.num_rar_entries = 128; 1011 hw->mac.num_rar_entries = 128;
959 hw->mac.ops.init_rx_addrs(hw); 1012 hw->mac.ops.init_rx_addrs(hw);
960 1013
961 /* Store the permanent mac address */
962 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
963
964 /* Store the permanent SAN mac address */ 1014 /* Store the permanent SAN mac address */
965 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1015 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
966 1016
@@ -1002,7 +1052,7 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1002 udelay(10); 1052 udelay(10);
1003 } 1053 }
1004 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1054 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1005 hw_dbg(hw ,"Flow Director previous command isn't complete, " 1055 hw_dbg(hw, "Flow Director previous command isn't complete, "
1006 "aborting table re-initialization.\n"); 1056 "aborting table re-initialization.\n");
1007 return IXGBE_ERR_FDIR_REINIT_FAILED; 1057 return IXGBE_ERR_FDIR_REINIT_FAILED;
1008 } 1058 }
@@ -1078,7 +1128,7 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1078 1128
1079 /* 1129 /*
1080 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1130 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1081 * intialized to zero for non DCB mode otherwise actual total RX PB 1131 * initialized to zero for non DCB mode otherwise actual total RX PB
1082 * would be bigger than programmed and filter space would run into 1132 * would be bigger than programmed and filter space would run into
1083 * the PB 0 region. 1133 * the PB 0 region.
1084 */ 1134 */
@@ -1112,13 +1162,10 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1112 /* Move the flexible bytes to use the ethertype - shift 6 words */ 1162 /* Move the flexible bytes to use the ethertype - shift 6 words */
1113 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1163 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1114 1164
1115 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1116 1165
1117 /* Prime the keys for hashing */ 1166 /* Prime the keys for hashing */
1118 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, 1167 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1119 htonl(IXGBE_ATR_BUCKET_HASH_KEY)); 1168 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1120 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1121 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1122 1169
1123 /* 1170 /*
1124 * Poll init-done after we write the register. Estimated times: 1171 * Poll init-done after we write the register. Estimated times:
@@ -1139,7 +1186,7 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1139 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1186 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1140 IXGBE_FDIRCTRL_INIT_DONE) 1187 IXGBE_FDIRCTRL_INIT_DONE)
1141 break; 1188 break;
1142 msleep(1); 1189 usleep_range(1000, 2000);
1143 } 1190 }
1144 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1191 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1145 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1192 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
@@ -1169,7 +1216,7 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1169 1216
1170 /* 1217 /*
1171 * The defaults in the HW for RX PB 1-7 are not zero and so should be 1218 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1172 * intialized to zero for non DCB mode otherwise actual total RX PB 1219 * initialized to zero for non DCB mode otherwise actual total RX PB
1173 * would be bigger than programmed and filter space would run into 1220 * would be bigger than programmed and filter space would run into
1174 * the PB 0 region. 1221 * the PB 0 region.
1175 */ 1222 */
@@ -1208,10 +1255,8 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1208 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); 1255 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1209 1256
1210 /* Prime the keys for hashing */ 1257 /* Prime the keys for hashing */
1211 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, 1258 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1212 htonl(IXGBE_ATR_BUCKET_HASH_KEY)); 1259 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1213 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1214 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1215 1260
1216 /* 1261 /*
1217 * Poll init-done after we write the register. Estimated times: 1262 * Poll init-done after we write the register. Estimated times:
@@ -1236,7 +1281,7 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1236 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1281 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1237 IXGBE_FDIRCTRL_INIT_DONE) 1282 IXGBE_FDIRCTRL_INIT_DONE)
1238 break; 1283 break;
1239 msleep(1); 1284 usleep_range(1000, 2000);
1240 } 1285 }
1241 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1286 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1242 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n"); 1287 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
@@ -1250,8 +1295,8 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1250 * @stream: input bitstream to compute the hash on 1295 * @stream: input bitstream to compute the hash on
1251 * @key: 32-bit hash key 1296 * @key: 32-bit hash key
1252 **/ 1297 **/
1253static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, 1298static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1254 u32 key) 1299 u32 key)
1255{ 1300{
1256 /* 1301 /*
1257 * The algorithm is as follows: 1302 * The algorithm is as follows:
@@ -1271,557 +1316,250 @@ static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1271 * To simplify for programming, the algorithm is implemented 1316 * To simplify for programming, the algorithm is implemented
1272 * in software this way: 1317 * in software this way:
1273 * 1318 *
1274 * Key[31:0], Stream[335:0] 1319 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1320 *
1321 * for (i = 0; i < 352; i+=32)
1322 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1323 *
1324 * lo_hash_dword[15:0] ^= Stream[15:0];
1325 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1326 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1327 *
1328 * hi_hash_dword[31:0] ^= Stream[351:320];
1275 * 1329 *
1276 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times 1330 * if(key[0])
1277 * int_key[350:0] = tmp_key[351:1] 1331 * hash[15:0] ^= Stream[15:0];
1278 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1279 * 1332 *
1280 * hash[15:0] = 0; 1333 * for (i = 0; i < 16; i++) {
1281 * for (i = 0; i < 351; i++) { 1334 * if (key[i])
1282 * if (int_key[i]) 1335 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1283 * hash ^= int_stream[(i + 15):i]; 1336 * if (key[i + 16])
1337 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1284 * } 1338 * }
1339 *
1285 */ 1340 */
1341 __be32 common_hash_dword = 0;
1342 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1343 u32 hash_result = 0;
1344 u8 i;
1286 1345
1287 union { 1346 /* record the flow_vm_vlan bits as they are a key part to the hash */
1288 u64 fill[6]; 1347 flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
1289 u32 key[11];
1290 u8 key_stream[44];
1291 } tmp_key;
1292 1348
1293 u8 *stream = (u8 *)atr_input; 1349 /* generate common hash dword */
1294 u8 int_key[44]; /* upper-most bit unused */ 1350 for (i = 10; i; i -= 2)
1295 u8 hash_str[46]; /* upper-most 2 bits unused */ 1351 common_hash_dword ^= atr_input->dword_stream[i] ^
1296 u16 hash_result = 0; 1352 atr_input->dword_stream[i - 1];
1297 int i, j, k, h;
1298 1353
1299 /* 1354 hi_hash_dword = ntohl(common_hash_dword);
1300 * Initialize the fill member to prevent warnings
1301 * on some compilers
1302 */
1303 tmp_key.fill[0] = 0;
1304 1355
1305 /* First load the temporary key stream */ 1356 /* low dword is word swapped version of common */
1306 for (i = 0; i < 6; i++) { 1357 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1307 u64 fillkey = ((u64)key << 32) | key;
1308 tmp_key.fill[i] = fillkey;
1309 }
1310 1358
1311 /* 1359 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1312 * Set the interim key for the hashing. Bit 352 is unused, so we must 1360 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1313 * shift and compensate when building the key.
1314 */
1315
1316 int_key[0] = tmp_key.key_stream[0] >> 1;
1317 for (i = 1, j = 0; i < 44; i++) {
1318 unsigned int this_key = tmp_key.key_stream[j] << 7;
1319 j++;
1320 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1321 }
1322 1361
1323 /* 1362 /* Process bits 0 and 16 */
1324 * Set the interim bit string for the hashing. Bits 368 and 367 are 1363 if (key & 0x0001) hash_result ^= lo_hash_dword;
1325 * unused, so shift and compensate when building the string. 1364 if (key & 0x00010000) hash_result ^= hi_hash_dword;
1326 */
1327 hash_str[0] = (stream[40] & 0x7f) >> 1;
1328 for (i = 1, j = 40; i < 46; i++) {
1329 unsigned int this_str = stream[j] << 7;
1330 j++;
1331 if (j > 41)
1332 j = 0;
1333 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1334 }
1335 1365
1336 /* 1366 /*
1337 * Now compute the hash. i is the index into hash_str, j is into our 1367 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1338 * key stream, k is counting the number of bits, and h interates within 1368 * delay this because bit 0 of the stream should not be processed
1339 * each byte. 1369 * so we do not add the vlan until after bit 0 was processed
1340 */ 1370 */
1341 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) { 1371 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1342 for (h = 0; h < 8 && k < 351; h++, k++) {
1343 if (int_key[j] & (1 << h)) {
1344 /*
1345 * Key bit is set, XOR in the current 16-bit
1346 * string. Example of processing:
1347 * h = 0,
1348 * tmp = (hash_str[i - 2] & 0 << 16) |
1349 * (hash_str[i - 1] & 0xff << 8) |
1350 * (hash_str[i] & 0xff >> 0)
1351 * So tmp = hash_str[15 + k:k], since the
1352 * i + 2 clause rolls off the 16-bit value
1353 * h = 7,
1354 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1355 * (hash_str[i - 1] & 0xff << 1) |
1356 * (hash_str[i] & 0x80 >> 7)
1357 */
1358 int tmp = (hash_str[i] >> h);
1359 tmp |= (hash_str[i - 1] << (8 - h));
1360 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1361 << (16 - h);
1362 hash_result ^= (u16)tmp;
1363 }
1364 }
1365 }
1366
1367 return hash_result;
1368}
1369
1370/**
1371 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1372 * @input: input stream to modify
1373 * @vlan: the VLAN id to load
1374 **/
1375s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1376{
1377 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1378 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1379
1380 return 0;
1381}
1382
1383/**
1384 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1385 * @input: input stream to modify
1386 * @src_addr: the IP address to load
1387 **/
1388s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1389{
1390 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1391 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1392 (src_addr >> 16) & 0xff;
1393 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1394 (src_addr >> 8) & 0xff;
1395 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1396
1397 return 0;
1398}
1399
1400/**
1401 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1402 * @input: input stream to modify
1403 * @dst_addr: the IP address to load
1404 **/
1405s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1406{
1407 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1408 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1409 (dst_addr >> 16) & 0xff;
1410 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1411 (dst_addr >> 8) & 0xff;
1412 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1413
1414 return 0;
1415}
1416
1417/**
1418 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1419 * @input: input stream to modify
1420 * @src_addr_1: the first 4 bytes of the IP address to load
1421 * @src_addr_2: the second 4 bytes of the IP address to load
1422 * @src_addr_3: the third 4 bytes of the IP address to load
1423 * @src_addr_4: the fourth 4 bytes of the IP address to load
1424 **/
1425s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
1426 u32 src_addr_1, u32 src_addr_2,
1427 u32 src_addr_3, u32 src_addr_4)
1428{
1429 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1430 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1431 (src_addr_4 >> 8) & 0xff;
1432 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1433 (src_addr_4 >> 16) & 0xff;
1434 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1435
1436 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1437 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1438 (src_addr_3 >> 8) & 0xff;
1439 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1440 (src_addr_3 >> 16) & 0xff;
1441 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1442
1443 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1444 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1445 (src_addr_2 >> 8) & 0xff;
1446 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1447 (src_addr_2 >> 16) & 0xff;
1448 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1449
1450 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1451 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1452 (src_addr_1 >> 8) & 0xff;
1453 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1454 (src_addr_1 >> 16) & 0xff;
1455 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1456
1457 return 0;
1458}
1459
1460/**
1461 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1462 * @input: input stream to modify
1463 * @dst_addr_1: the first 4 bytes of the IP address to load
1464 * @dst_addr_2: the second 4 bytes of the IP address to load
1465 * @dst_addr_3: the third 4 bytes of the IP address to load
1466 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1467 **/
1468s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
1469 u32 dst_addr_1, u32 dst_addr_2,
1470 u32 dst_addr_3, u32 dst_addr_4)
1471{
1472 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1473 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1474 (dst_addr_4 >> 8) & 0xff;
1475 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1476 (dst_addr_4 >> 16) & 0xff;
1477 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1478
1479 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1480 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1481 (dst_addr_3 >> 8) & 0xff;
1482 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1483 (dst_addr_3 >> 16) & 0xff;
1484 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1485
1486 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1487 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1488 (dst_addr_2 >> 8) & 0xff;
1489 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1490 (dst_addr_2 >> 16) & 0xff;
1491 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1492
1493 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1494 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1495 (dst_addr_1 >> 8) & 0xff;
1496 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1497 (dst_addr_1 >> 16) & 0xff;
1498 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1499
1500 return 0;
1501}
1502
1503/**
1504 * ixgbe_atr_set_src_port_82599 - Sets the source port
1505 * @input: input stream to modify
1506 * @src_port: the source port to load
1507 **/
1508s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1509{
1510 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1511 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1512
1513 return 0;
1514}
1515
1516/**
1517 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1518 * @input: input stream to modify
1519 * @dst_port: the destination port to load
1520 **/
1521s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1522{
1523 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1524 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1525
1526 return 0;
1527}
1528
1529/**
1530 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1531 * @input: input stream to modify
1532 * @flex_bytes: the flexible bytes to load
1533 **/
1534s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1535{
1536 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1537 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1538
1539 return 0;
1540}
1541
1542/**
1543 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1544 * @input: input stream to modify
1545 * @vm_pool: the Virtual Machine pool to load
1546 **/
1547s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1548 u8 vm_pool)
1549{
1550 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1551
1552 return 0;
1553}
1554
1555/**
1556 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1557 * @input: input stream to modify
1558 * @l4type: the layer 4 type value to load
1559 **/
1560s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1561{
1562 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1563
1564 return 0;
1565}
1566
1567/**
1568 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1569 * @input: input stream to search
1570 * @vlan: the VLAN id to load
1571 **/
1572static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
1573{
1574 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1575 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1576
1577 return 0;
1578}
1579 1372
1580/**
1581 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1582 * @input: input stream to search
1583 * @src_addr: the IP address to load
1584 **/
1585static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1586 u32 *src_addr)
1587{
1588 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1589 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1590 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1591 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1592 1373
1593 return 0; 1374 /* process the remaining 30 bits in the key 2 bits at a time */
1594} 1375 for (i = 15; i; i-- ) {
1595 1376 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1596/** 1377 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
1597 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address 1378 }
1598 * @input: input stream to search
1599 * @dst_addr: the IP address to load
1600 **/
1601static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1602 u32 *dst_addr)
1603{
1604 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1605 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1606 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1607 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1608
1609 return 0;
1610}
1611
1612/**
1613 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1614 * @input: input stream to search
1615 * @src_addr_1: the first 4 bytes of the IP address to load
1616 * @src_addr_2: the second 4 bytes of the IP address to load
1617 * @src_addr_3: the third 4 bytes of the IP address to load
1618 * @src_addr_4: the fourth 4 bytes of the IP address to load
1619 **/
1620static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1621 u32 *src_addr_1, u32 *src_addr_2,
1622 u32 *src_addr_3, u32 *src_addr_4)
1623{
1624 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1625 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1626 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1627 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1628
1629 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1630 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1631 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1632 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1633
1634 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1635 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1636 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1637 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1638
1639 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1640 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1641 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1642 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1643 1379
1644 return 0; 1380 return hash_result & IXGBE_ATR_HASH_MASK;
1645} 1381}
1646 1382
1647/** 1383/*
1648 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address 1384 * These defines allow us to quickly generate all of the necessary instructions
1649 * @input: input stream to search 1385 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1650 * @dst_addr_1: the first 4 bytes of the IP address to load 1386 * for values 0 through 15
1651 * @dst_addr_2: the second 4 bytes of the IP address to load 1387 */
1652 * @dst_addr_3: the third 4 bytes of the IP address to load 1388#define IXGBE_ATR_COMMON_HASH_KEY \
1653 * @dst_addr_4: the fourth 4 bytes of the IP address to load 1389 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1654 **/ 1390#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1655s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input, 1391do { \
1656 u32 *dst_addr_1, u32 *dst_addr_2, 1392 u32 n = (_n); \
1657 u32 *dst_addr_3, u32 *dst_addr_4) 1393 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1658{ 1394 common_hash ^= lo_hash_dword >> n; \
1659 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12]; 1395 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1660 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8; 1396 bucket_hash ^= lo_hash_dword >> n; \
1661 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16; 1397 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1662 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24; 1398 sig_hash ^= lo_hash_dword << (16 - n); \
1663 1399 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1664 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8]; 1400 common_hash ^= hi_hash_dword >> n; \
1665 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8; 1401 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1666 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16; 1402 bucket_hash ^= hi_hash_dword >> n; \
1667 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24; 1403 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1668 1404 sig_hash ^= hi_hash_dword << (16 - n); \
1669 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4]; 1405} while (0);
1670 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1671 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1672 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1673
1674 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1675 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1676 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1677 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1678
1679 return 0;
1680}
1681 1406
1682/** 1407/**
1683 * ixgbe_atr_get_src_port_82599 - Gets the source port 1408 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1684 * @input: input stream to modify 1409 * @stream: input bitstream to compute the hash on
1685 * @src_port: the source port to load
1686 * 1410 *
1687 * Even though the input is given in big-endian, the FDIRPORT registers 1411 * This function is almost identical to the function above but contains
1688 * expect the ports to be programmed in little-endian. Hence the need to swap 1412 * several optomizations such as unwinding all of the loops, letting the
1689 * endianness when retrieving the data. This can be confusing since the 1413 * compiler work out all of the conditional ifs since the keys are static
1690 * internal hash engine expects it to be big-endian. 1414 * defines, and computing two keys at once since the hashed dword stream
1415 * will be the same for both keys.
1691 **/ 1416 **/
1692static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, 1417static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1693 u16 *src_port) 1418 union ixgbe_atr_hash_dword common)
1694{ 1419{
1695 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8; 1420 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1696 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1]; 1421 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1697 1422
1698 return 0; 1423 /* record the flow_vm_vlan bits as they are a key part to the hash */
1699} 1424 flow_vm_vlan = ntohl(input.dword);
1700 1425
1701/** 1426 /* generate common hash dword */
1702 * ixgbe_atr_get_dst_port_82599 - Gets the destination port 1427 hi_hash_dword = ntohl(common.dword);
1703 * @input: input stream to modify
1704 * @dst_port: the destination port to load
1705 *
1706 * Even though the input is given in big-endian, the FDIRPORT registers
1707 * expect the ports to be programmed in little-endian. Hence the need to swap
1708 * endianness when retrieving the data. This can be confusing since the
1709 * internal hash engine expects it to be big-endian.
1710 **/
1711static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1712 u16 *dst_port)
1713{
1714 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1715 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1716 1428
1717 return 0; 1429 /* low dword is word swapped version of common */
1718} 1430 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1719 1431
1720/** 1432 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1721 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes 1433 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1722 * @input: input stream to modify
1723 * @flex_bytes: the flexible bytes to load
1724 **/
1725static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1726 u16 *flex_byte)
1727{
1728 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1729 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1730
1731 return 0;
1732}
1733 1434
1734/** 1435 /* Process bits 0 and 16 */
1735 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool 1436 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1736 * @input: input stream to modify
1737 * @vm_pool: the Virtual Machine pool to load
1738 **/
1739s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1740 u8 *vm_pool)
1741{
1742 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1743 1437
1744 return 0; 1438 /*
1745} 1439 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1440 * delay this because bit 0 of the stream should not be processed
1441 * so we do not add the vlan until after bit 0 was processed
1442 */
1443 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1444
1445 /* Process remaining 30 bit of the key */
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1453 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1454 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1455 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1456 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1457 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1458 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1459 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1460 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1461
1462 /* combine common_hash result with signature and bucket hashes */
1463 bucket_hash ^= common_hash;
1464 bucket_hash &= IXGBE_ATR_HASH_MASK;
1746 1465
1747/** 1466 sig_hash ^= common_hash << 16;
1748 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type 1467 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1749 * @input: input stream to modify
1750 * @l4type: the layer 4 type value to load
1751 **/
1752static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1753 u8 *l4type)
1754{
1755 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1756 1468
1757 return 0; 1469 /* return completed signature hash */
1470 return sig_hash ^ bucket_hash;
1758} 1471}
1759 1472
1760/** 1473/**
1761 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1474 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1762 * @hw: pointer to hardware structure 1475 * @hw: pointer to hardware structure
1763 * @stream: input bitstream 1476 * @input: unique input dword
1477 * @common: compressed common input dword
1764 * @queue: queue index to direct traffic to 1478 * @queue: queue index to direct traffic to
1765 **/ 1479 **/
1766s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1480s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1767 struct ixgbe_atr_input *input, 1481 union ixgbe_atr_hash_dword input,
1482 union ixgbe_atr_hash_dword common,
1768 u8 queue) 1483 u8 queue)
1769{ 1484{
1770 u64 fdirhashcmd; 1485 u64 fdirhashcmd;
1771 u64 fdircmd; 1486 u32 fdircmd;
1772 u32 fdirhash;
1773 u16 bucket_hash, sig_hash;
1774 u8 l4type;
1775
1776 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1777 IXGBE_ATR_BUCKET_HASH_KEY);
1778
1779 /* bucket_hash is only 15 bits */
1780 bucket_hash &= IXGBE_ATR_HASH_MASK;
1781
1782 sig_hash = ixgbe_atr_compute_hash_82599(input,
1783 IXGBE_ATR_SIGNATURE_HASH_KEY);
1784
1785 /* Get the l4type in order to program FDIRCMD properly */
1786 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1787 ixgbe_atr_get_l4type_82599(input, &l4type);
1788 1487
1789 /* 1488 /*
1790 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1489 * Get the flow_type in order to program FDIRCMD properly
1791 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1490 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1792 */ 1491 */
1793 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; 1492 switch (input.formatted.flow_type) {
1794 1493 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1795 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1494 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1796 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN); 1495 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1797 1496 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1798 switch (l4type & IXGBE_ATR_L4TYPE_MASK) { 1497 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1799 case IXGBE_ATR_L4TYPE_TCP: 1498 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1800 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1801 break;
1802 case IXGBE_ATR_L4TYPE_UDP:
1803 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1804 break;
1805 case IXGBE_ATR_L4TYPE_SCTP:
1806 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1807 break; 1499 break;
1808 default: 1500 default:
1809 hw_dbg(hw, "Error on l4type input\n"); 1501 hw_dbg(hw, " Error on flow type input\n");
1810 return IXGBE_ERR_CONFIG; 1502 return IXGBE_ERR_CONFIG;
1811 } 1503 }
1812 1504
1813 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) 1505 /* configure FDIRCMD register */
1814 fdircmd |= IXGBE_FDIRCMD_IPV6; 1506 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1507 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1508 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1509 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1815 1510
1816 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT); 1511 /*
1817 fdirhashcmd = ((fdircmd << 32) | fdirhash); 1512 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1513 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1514 */
1515 fdirhashcmd = (u64)fdircmd << 32;
1516 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1818 1517
1819 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1518 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1820 1519
1520 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1521
1821 return 0; 1522 return 0;
1822} 1523}
1823 1524
1824/** 1525/**
1526 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1527 * @input_mask: mask to be bit swapped
1528 *
1529 * The source and destination port masks for flow director are bit swapped
1530 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1531 * generate a correctly swapped value we need to bit swap the mask and that
1532 * is what is accomplished by this function.
1533 **/
1534static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1535{
1536 u32 mask = ntohs(input_masks->dst_port_mask);
1537 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1538 mask |= ntohs(input_masks->src_port_mask);
1539 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1540 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1541 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1542 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1543}
1544
1545/*
1546 * These two macros are meant to address the fact that we have registers
1547 * that are either all or in part big-endian. As a result on big-endian
1548 * systems we will end up byte swapping the value to little-endian before
1549 * it is byte swapped again and written to the hardware in the original
1550 * big-endian format.
1551 */
1552#define IXGBE_STORE_AS_BE32(_value) \
1553 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1554 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1555
1556#define IXGBE_WRITE_REG_BE32(a, reg, value) \
1557 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1558
1559#define IXGBE_STORE_AS_BE16(_value) \
1560 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1561
1562/**
1825 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter 1563 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1826 * @hw: pointer to hardware structure 1564 * @hw: pointer to hardware structure
1827 * @input: input bitstream 1565 * @input: input bitstream
@@ -1833,82 +1571,39 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1833 * hardware writes must be protected from one another. 1571 * hardware writes must be protected from one another.
1834 **/ 1572 **/
1835s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 1573s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1836 struct ixgbe_atr_input *input, 1574 union ixgbe_atr_input *input,
1837 struct ixgbe_atr_input_masks *input_masks, 1575 struct ixgbe_atr_input_masks *input_masks,
1838 u16 soft_id, u8 queue) 1576 u16 soft_id, u8 queue)
1839{ 1577{
1840 u32 fdircmd = 0;
1841 u32 fdirhash; 1578 u32 fdirhash;
1842 u32 src_ipv4 = 0, dst_ipv4 = 0; 1579 u32 fdircmd;
1843 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4; 1580 u32 fdirport, fdirtcpm;
1844 u16 src_port, dst_port, vlan_id, flex_bytes; 1581 u32 fdirvlan;
1845 u16 bucket_hash; 1582 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1846 u8 l4type; 1583 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1847 u8 fdirm = 0; 1584 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
1848
1849 /* Get our input values */
1850 ixgbe_atr_get_l4type_82599(input, &l4type);
1851 1585
1852 /* 1586 /*
1853 * Check l4type formatting, and bail out before we touch the hardware 1587 * Check flow_type formatting, and bail out before we touch the hardware
1854 * if there's a configuration issue 1588 * if there's a configuration issue
1855 */ 1589 */
1856 switch (l4type & IXGBE_ATR_L4TYPE_MASK) { 1590 switch (input->formatted.flow_type) {
1857 case IXGBE_ATR_L4TYPE_TCP: 1591 case IXGBE_ATR_FLOW_TYPE_IPV4:
1858 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; 1592 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1859 break; 1593 fdirm |= IXGBE_FDIRM_L4P;
1860 case IXGBE_ATR_L4TYPE_UDP: 1594 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1861 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; 1595 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1862 break; 1596 hw_dbg(hw, " Error on src/dst port mask\n");
1863 case IXGBE_ATR_L4TYPE_SCTP: 1597 return IXGBE_ERR_CONFIG;
1864 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; 1598 }
1599 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1600 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1865 break; 1601 break;
1866 default: 1602 default:
1867 hw_dbg(hw, "Error on l4type input\n"); 1603 hw_dbg(hw, " Error on flow type input\n");
1868 return IXGBE_ERR_CONFIG; 1604 return IXGBE_ERR_CONFIG;
1869 } 1605 }
1870 1606
1871 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1872 IXGBE_ATR_BUCKET_HASH_KEY);
1873
1874 /* bucket_hash is only 15 bits */
1875 bucket_hash &= IXGBE_ATR_HASH_MASK;
1876
1877 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1878 ixgbe_atr_get_src_port_82599(input, &src_port);
1879 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1880 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1881
1882 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1883
1884 /* Now figure out if we're IPv4 or IPv6 */
1885 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1886 /* IPv6 */
1887 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
1888 &src_ipv6_3, &src_ipv6_4);
1889
1890 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
1891 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
1892 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
1893 /* The last 4 bytes is the same register as IPv4 */
1894 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
1895
1896 fdircmd |= IXGBE_FDIRCMD_IPV6;
1897 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
1898 } else {
1899 /* IPv4 */
1900 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
1901 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
1902 }
1903
1904 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
1905 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
1906
1907 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
1908 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
1909 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
1910 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
1911
1912 /* 1607 /*
1913 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1608 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1914 * are zero, then assume a full mask for that field. Also assume that 1609 * are zero, then assume a full mask for that field. Also assume that
@@ -1918,79 +1613,97 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1918 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1613 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1919 * point in time. 1614 * point in time.
1920 */ 1615 */
1921 if (src_ipv4 == 0)
1922 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
1923 else
1924 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
1925 1616
1926 if (dst_ipv4 == 0) 1617 /* Program FDIRM */
1927 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff); 1618 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
1928 else 1619 case 0xEFFF:
1929 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask); 1620 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1930 1621 fdirm &= ~IXGBE_FDIRM_VLANID;
1931 switch (l4type & IXGBE_ATR_L4TYPE_MASK) { 1622 case 0xE000:
1932 case IXGBE_ATR_L4TYPE_TCP: 1623 /* Unmask VLAN prio - bit 1 */
1933 if (src_port == 0) 1624 fdirm &= ~IXGBE_FDIRM_VLANP;
1934 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
1935 else
1936 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1937 input_masks->src_port_mask);
1938
1939 if (dst_port == 0)
1940 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1941 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1942 (0xffff << 16)));
1943 else
1944 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1945 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1946 (input_masks->dst_port_mask << 16)));
1947 break; 1625 break;
1948 case IXGBE_ATR_L4TYPE_UDP: 1626 case 0x0FFF:
1949 if (src_port == 0) 1627 /* Unmask VLAN ID - bit 0 */
1950 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff); 1628 fdirm &= ~IXGBE_FDIRM_VLANID;
1951 else
1952 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1953 input_masks->src_port_mask);
1954
1955 if (dst_port == 0)
1956 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1957 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1958 (0xffff << 16)));
1959 else
1960 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1961 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1962 (input_masks->src_port_mask << 16)));
1963 break; 1629 break;
1964 default: 1630 case 0x0000:
1965 /* this already would have failed above */ 1631 /* do nothing, vlans already masked */
1966 break; 1632 break;
1633 default:
1634 hw_dbg(hw, " Error on VLAN mask\n");
1635 return IXGBE_ERR_CONFIG;
1967 } 1636 }
1968 1637
1969 /* Program the last mask register, FDIRM */ 1638 if (input_masks->flex_mask & 0xFFFF) {
1970 if (input_masks->vlan_id_mask || !vlan_id) 1639 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1971 /* Mask both VLAN and VLANP - bits 0 and 1 */ 1640 hw_dbg(hw, " Error on flexible byte mask\n");
1972 fdirm |= 0x3; 1641 return IXGBE_ERR_CONFIG;
1973 1642 }
1974 if (input_masks->data_mask || !flex_bytes) 1643 /* Unmask Flex Bytes - bit 4 */
1975 /* Flex bytes need masking, so mask the whole thing - bit 4 */ 1644 fdirm &= ~IXGBE_FDIRM_FLEX;
1976 fdirm |= 0x10; 1645 }
1977 1646
1978 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1647 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1979 fdirm |= 0x24;
1980
1981 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1648 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1982 1649
1983 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW; 1650 /* store the TCP/UDP port masks, bit reversed from port layout */
1984 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE; 1651 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1985 fdircmd |= IXGBE_FDIRCMD_LAST; 1652
1986 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN; 1653 /* write both the same so that UDP and TCP use the same mask */
1987 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1654 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1655 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1656
1657 /* store source and destination IP masks (big-enian) */
1658 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1659 ~input_masks->src_ip_mask[0]);
1660 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1661 ~input_masks->dst_ip_mask[0]);
1662
1663 /* Apply masks to input data */
1664 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1665 input->formatted.flex_bytes &= input_masks->flex_mask;
1666 input->formatted.src_port &= input_masks->src_port_mask;
1667 input->formatted.dst_port &= input_masks->dst_port_mask;
1668 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1669 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1670
1671 /* record vlan (little-endian) and flex_bytes(big-endian) */
1672 fdirvlan =
1673 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
1674 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1675 fdirvlan |= ntohs(input->formatted.vlan_id);
1676 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1677
1678 /* record source and destination port (little-endian)*/
1679 fdirport = ntohs(input->formatted.dst_port);
1680 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1681 fdirport |= ntohs(input->formatted.src_port);
1682 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1683
1684 /* record the first 32 bits of the destination address (big-endian) */
1685 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1686
1687 /* record the source address (big-endian) */
1688 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1689
1690 /* configure FDIRCMD register */
1691 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1692 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1693 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1694 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1695
1696 /* we only want the bucket hash so drop the upper 16 bits */
1697 fdirhash = ixgbe_atr_compute_hash_82599(input,
1698 IXGBE_ATR_BUCKET_HASH_KEY);
1699 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1988 1700
1989 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1701 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1990 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1702 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1991 1703
1992 return 0; 1704 return 0;
1993} 1705}
1706
1994/** 1707/**
1995 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1708 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1996 * @hw: pointer to hardware structure 1709 * @hw: pointer to hardware structure
@@ -2037,30 +1750,29 @@ static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2037 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1750 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2038 * @hw: pointer to hardware structure 1751 * @hw: pointer to hardware structure
2039 * 1752 *
2040 * Starts the hardware using the generic start_hw function. 1753 * Starts the hardware using the generic start_hw function
2041 * Then performs device-specific: 1754 * and the generation start_hw function.
2042 * Clears the rate limiter registers. 1755 * Then performs revision-specific operations, if any.
2043 **/ 1756 **/
2044static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1757static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2045{ 1758{
2046 u32 q_num; 1759 s32 ret_val = 0;
2047 s32 ret_val;
2048 1760
2049 ret_val = ixgbe_start_hw_generic(hw); 1761 ret_val = ixgbe_start_hw_generic(hw);
1762 if (ret_val != 0)
1763 goto out;
2050 1764
2051 /* Clear the rate limiters */ 1765 ret_val = ixgbe_start_hw_gen2(hw);
2052 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) { 1766 if (ret_val != 0)
2053 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num); 1767 goto out;
2054 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2055 }
2056 IXGBE_WRITE_FLUSH(hw);
2057 1768
2058 /* We need to run link autotry after the driver loads */ 1769 /* We need to run link autotry after the driver loads */
2059 hw->mac.autotry_restart = true; 1770 hw->mac.autotry_restart = true;
1771 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
2060 1772
2061 if (ret_val == 0) 1773 if (ret_val == 0)
2062 ret_val = ixgbe_verify_fw_version_82599(hw); 1774 ret_val = ixgbe_verify_fw_version_82599(hw);
2063 1775out:
2064 return ret_val; 1776 return ret_val;
2065} 1777}
2066 1778
@@ -2069,13 +1781,34 @@ static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2069 * @hw: pointer to hardware structure 1781 * @hw: pointer to hardware structure
2070 * 1782 *
2071 * Determines the physical layer module found on the current adapter. 1783 * Determines the physical layer module found on the current adapter.
1784 * If PHY already detected, maintains current PHY type in hw struct,
1785 * otherwise executes the PHY detection routine.
2072 **/ 1786 **/
2073static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1787static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2074{ 1788{
2075 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1789 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1790
1791 /* Detect PHY if not unknown - returns success if already detected. */
2076 status = ixgbe_identify_phy_generic(hw); 1792 status = ixgbe_identify_phy_generic(hw);
2077 if (status != 0) 1793 if (status != 0) {
2078 status = ixgbe_identify_sfp_module_generic(hw); 1794 /* 82599 10GBASE-T requires an external PHY */
1795 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1796 goto out;
1797 else
1798 status = ixgbe_identify_sfp_module_generic(hw);
1799 }
1800
1801 /* Set PHY type none if no PHY detected */
1802 if (hw->phy.type == ixgbe_phy_unknown) {
1803 hw->phy.type = ixgbe_phy_none;
1804 status = 0;
1805 }
1806
1807 /* Return error if SFP module has been detected but is not supported */
1808 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1809 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1810
1811out:
2079 return status; 1812 return status;
2080} 1813}
2081 1814
@@ -2099,10 +1832,12 @@ static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2099 1832
2100 hw->phy.ops.identify(hw); 1833 hw->phy.ops.identify(hw);
2101 1834
2102 if (hw->phy.type == ixgbe_phy_tn || 1835 switch (hw->phy.type) {
2103 hw->phy.type == ixgbe_phy_cu_unknown) { 1836 case ixgbe_phy_tn:
1837 case ixgbe_phy_aq:
1838 case ixgbe_phy_cu_unknown:
2104 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, 1839 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2105 &ext_ability); 1840 &ext_ability);
2106 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 1841 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2107 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1842 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2108 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 1843 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
@@ -2110,6 +1845,8 @@ static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2110 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 1845 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2111 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1846 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2112 goto out; 1847 goto out;
1848 default:
1849 break;
2113 } 1850 }
2114 1851
2115 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1852 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
@@ -2221,6 +1958,7 @@ static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2221 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 1958 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2222 break; 1959 break;
2223 else 1960 else
1961 /* Use interrupt-safe sleep just in case */
2224 udelay(10); 1962 udelay(10);
2225 } 1963 }
2226 1964
@@ -2239,21 +1977,6 @@ static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2239} 1977}
2240 1978
2241/** 1979/**
2242 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2243 * @hw: pointer to hardware structure
2244 * @device_caps: the EEPROM word with the extra device capabilities
2245 *
2246 * This function will read the EEPROM location for the device capabilities,
2247 * and return the word through device_caps.
2248 **/
2249static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2250{
2251 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2252
2253 return 0;
2254}
2255
2256/**
2257 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1980 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2258 * @hw: pointer to hardware structure 1981 * @hw: pointer to hardware structure
2259 * 1982 *
@@ -2302,48 +2025,107 @@ fw_version_out:
2302} 2025}
2303 2026
2304/** 2027/**
2305 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from 2028 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2306 * the EEPROM
2307 * @hw: pointer to hardware structure 2029 * @hw: pointer to hardware structure
2308 * @wwnn_prefix: the alternative WWNN prefix
2309 * @wwpn_prefix: the alternative WWPN prefix
2310 * 2030 *
2311 * This function will read the EEPROM from the alternative SAN MAC address 2031 * Returns true if the LESM FW module is present and enabled. Otherwise
2312 * block to check the support for the alternative WWNN/WWPN prefix support. 2032 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2313 **/ 2033 **/
2314static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix, 2034static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2315 u16 *wwpn_prefix)
2316{ 2035{
2317 u16 offset, caps; 2036 bool lesm_enabled = false;
2318 u16 alt_san_mac_blk_offset; 2037 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2038 s32 status;
2319 2039
2320 /* clear output first */ 2040 /* get the offset to the Firmware Module block */
2321 *wwnn_prefix = 0xFFFF; 2041 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2322 *wwpn_prefix = 0xFFFF;
2323 2042
2324 /* check if alternative SAN MAC is supported */ 2043 if ((status != 0) ||
2325 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 2044 (fw_offset == 0) || (fw_offset == 0xFFFF))
2326 &alt_san_mac_blk_offset); 2045 goto out;
2327 2046
2328 if ((alt_san_mac_blk_offset == 0) || 2047 /* get the offset to the LESM Parameters block */
2329 (alt_san_mac_blk_offset == 0xFFFF)) 2048 status = hw->eeprom.ops.read(hw, (fw_offset +
2330 goto wwn_prefix_out; 2049 IXGBE_FW_LESM_PARAMETERS_PTR),
2050 &fw_lesm_param_offset);
2331 2051
2332 /* check capability in alternative san mac address block */ 2052 if ((status != 0) ||
2333 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 2053 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2334 hw->eeprom.ops.read(hw, offset, &caps); 2054 goto out;
2335 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2336 goto wwn_prefix_out;
2337 2055
2338 /* get the corresponding prefix for WWNN/WWPN */ 2056 /* get the lesm state word */
2339 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 2057 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2340 hw->eeprom.ops.read(hw, offset, wwnn_prefix); 2058 IXGBE_FW_LESM_STATE_1),
2059 &fw_lesm_state);
2341 2060
2342 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 2061 if ((status == 0) &&
2343 hw->eeprom.ops.read(hw, offset, wwpn_prefix); 2062 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2063 lesm_enabled = true;
2344 2064
2345wwn_prefix_out: 2065out:
2346 return 0; 2066 return lesm_enabled;
2067}
2068
2069/**
2070 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2071 * fastest available method
2072 *
2073 * @hw: pointer to hardware structure
2074 * @offset: offset of word in EEPROM to read
2075 * @words: number of words
2076 * @data: word(s) read from the EEPROM
2077 *
2078 * Retrieves 16 bit word(s) read from EEPROM
2079 **/
2080static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2081 u16 words, u16 *data)
2082{
2083 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2084 s32 ret_val = IXGBE_ERR_CONFIG;
2085
2086 /*
2087 * If EEPROM is detected and can be addressed using 14 bits,
2088 * use EERD otherwise use bit bang
2089 */
2090 if ((eeprom->type == ixgbe_eeprom_spi) &&
2091 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2092 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2093 data);
2094 else
2095 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2096 words,
2097 data);
2098
2099 return ret_val;
2100}
2101
2102/**
2103 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2104 * fastest available method
2105 *
2106 * @hw: pointer to hardware structure
2107 * @offset: offset of word in the EEPROM to read
2108 * @data: word read from the EEPROM
2109 *
2110 * Reads a 16 bit word from the EEPROM
2111 **/
2112static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2113 u16 offset, u16 *data)
2114{
2115 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2116 s32 ret_val = IXGBE_ERR_CONFIG;
2117
2118 /*
2119 * If EEPROM is detected and can be addressed using 14 bits,
2120 * use EERD otherwise use bit bang
2121 */
2122 if ((eeprom->type == ixgbe_eeprom_spi) &&
2123 (offset <= IXGBE_EERD_MAX_ADDR))
2124 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2125 else
2126 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2127
2128 return ret_val;
2347} 2129}
2348 2130
2349static struct ixgbe_mac_operations mac_ops_82599 = { 2131static struct ixgbe_mac_operations mac_ops_82599 = {
@@ -2356,8 +2138,8 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2356 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2138 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2357 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2139 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2358 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2140 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2359 .get_device_caps = &ixgbe_get_device_caps_82599, 2141 .get_device_caps = &ixgbe_get_device_caps_generic,
2360 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599, 2142 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2361 .stop_adapter = &ixgbe_stop_adapter_generic, 2143 .stop_adapter = &ixgbe_stop_adapter_generic,
2362 .get_bus_info = &ixgbe_get_bus_info_generic, 2144 .get_bus_info = &ixgbe_get_bus_info_generic,
2363 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2145 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
@@ -2375,7 +2157,6 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2375 .set_vmdq = &ixgbe_set_vmdq_generic, 2157 .set_vmdq = &ixgbe_set_vmdq_generic,
2376 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2158 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2377 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2159 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2378 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2379 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2160 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2380 .enable_mc = &ixgbe_enable_mc_generic, 2161 .enable_mc = &ixgbe_enable_mc_generic,
2381 .disable_mc = &ixgbe_disable_mc_generic, 2162 .disable_mc = &ixgbe_disable_mc_generic,
@@ -2384,30 +2165,38 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
2384 .fc_enable = &ixgbe_fc_enable_generic, 2165 .fc_enable = &ixgbe_fc_enable_generic,
2385 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2166 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2386 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2167 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2168 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2169 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2170 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2171 .release_swfw_sync = &ixgbe_release_swfw_sync,
2172
2387}; 2173};
2388 2174
2389static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2175static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2390 .init_params = &ixgbe_init_eeprom_params_generic, 2176 .init_params = &ixgbe_init_eeprom_params_generic,
2391 .read = &ixgbe_read_eerd_generic, 2177 .read = &ixgbe_read_eeprom_82599,
2392 .write = &ixgbe_write_eeprom_generic, 2178 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2393 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2179 .write = &ixgbe_write_eeprom_generic,
2394 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2180 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2181 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2182 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2183 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2395}; 2184};
2396 2185
2397static struct ixgbe_phy_operations phy_ops_82599 = { 2186static struct ixgbe_phy_operations phy_ops_82599 = {
2398 .identify = &ixgbe_identify_phy_82599, 2187 .identify = &ixgbe_identify_phy_82599,
2399 .identify_sfp = &ixgbe_identify_sfp_module_generic, 2188 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2400 .init = &ixgbe_init_phy_ops_82599, 2189 .init = &ixgbe_init_phy_ops_82599,
2401 .reset = &ixgbe_reset_phy_generic, 2190 .reset = &ixgbe_reset_phy_generic,
2402 .read_reg = &ixgbe_read_phy_reg_generic, 2191 .read_reg = &ixgbe_read_phy_reg_generic,
2403 .write_reg = &ixgbe_write_phy_reg_generic, 2192 .write_reg = &ixgbe_write_phy_reg_generic,
2404 .setup_link = &ixgbe_setup_phy_link_generic, 2193 .setup_link = &ixgbe_setup_phy_link_generic,
2405 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2194 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2406 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2195 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2407 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2196 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2408 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2197 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2409 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2198 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2410 .check_overtemp = &ixgbe_tn_check_overtemp, 2199 .check_overtemp = &ixgbe_tn_check_overtemp,
2411}; 2200};
2412 2201
2413struct ixgbe_info ixgbe_82599_info = { 2202struct ixgbe_info ixgbe_82599_info = {
@@ -2416,5 +2205,5 @@ struct ixgbe_info ixgbe_82599_info = {
2416 .mac_ops = &mac_ops_82599, 2205 .mac_ops = &mac_ops_82599,
2417 .eeprom_ops = &eeprom_ops_82599, 2206 .eeprom_ops = &eeprom_ops_82599,
2418 .phy_ops = &phy_ops_82599, 2207 .phy_ops = &phy_ops_82599,
2419 .mbx_ops = &mbx_ops_82599, 2208 .mbx_ops = &mbx_ops_generic,
2420}; 2209};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 18:10:43 -0400