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-rw-r--r--drivers/net/ibm_emac/Kconfig70
-rw-r--r--drivers/net/ibm_emac/Makefile11
-rw-r--r--drivers/net/ibm_emac/ibm_emac.h329
-rw-r--r--drivers/net/ibm_emac/ibm_emac_core.c2263
-rw-r--r--drivers/net/ibm_emac/ibm_emac_core.h222
-rw-r--r--drivers/net/ibm_emac/ibm_emac_debug.c211
-rw-r--r--drivers/net/ibm_emac/ibm_emac_debug.h62
-rw-r--r--drivers/net/ibm_emac/ibm_emac_mal.c570
-rw-r--r--drivers/net/ibm_emac/ibm_emac_mal.h267
-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.c398
-rw-r--r--drivers/net/ibm_emac/ibm_emac_phy.h80
-rw-r--r--drivers/net/ibm_emac/ibm_emac_rgmii.c200
-rw-r--r--drivers/net/ibm_emac/ibm_emac_rgmii.h64
-rw-r--r--drivers/net/ibm_emac/ibm_emac_tah.c110
-rw-r--r--drivers/net/ibm_emac/ibm_emac_tah.h87
-rw-r--r--drivers/net/ibm_emac/ibm_emac_zmii.c253
-rw-r--r--drivers/net/ibm_emac/ibm_emac_zmii.h82
17 files changed, 0 insertions, 5279 deletions
diff --git a/drivers/net/ibm_emac/Kconfig b/drivers/net/ibm_emac/Kconfig
deleted file mode 100644
index f61c48047dc0..000000000000
--- a/drivers/net/ibm_emac/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
1config IBM_EMAC
2 tristate "PowerPC 4xx on-chip Ethernet support"
3 depends on 4xx && !PPC_MERGE
4 help
5 This driver supports the PowerPC 4xx EMAC family of on-chip
6 Ethernet controllers.
7
8config IBM_EMAC_RXB
9 int "Number of receive buffers"
10 depends on IBM_EMAC
11 default "128"
12
13config IBM_EMAC_TXB
14 int "Number of transmit buffers"
15 depends on IBM_EMAC
16 default "64"
17
18config IBM_EMAC_POLL_WEIGHT
19 int "MAL NAPI polling weight"
20 depends on IBM_EMAC
21 default "32"
22
23config IBM_EMAC_RX_COPY_THRESHOLD
24 int "RX skb copy threshold (bytes)"
25 depends on IBM_EMAC
26 default "256"
27
28config IBM_EMAC_RX_SKB_HEADROOM
29 int "Additional RX skb headroom (bytes)"
30 depends on IBM_EMAC
31 default "0"
32 help
33 Additional receive skb headroom. Note, that driver
34 will always reserve at least 2 bytes to make IP header
35 aligned, so usually there is no need to add any additional
36 headroom.
37
38 If unsure, set to 0.
39
40config IBM_EMAC_PHY_RX_CLK_FIX
41 bool "PHY Rx clock workaround"
42 depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR)
43 help
44 Enable this if EMAC attached to a PHY which doesn't generate
45 RX clock if there is no link, if this is the case, you will
46 see "TX disable timeout" or "RX disable timeout" in the system
47 log.
48
49 If unsure, say N.
50
51config IBM_EMAC_DEBUG
52 bool "Debugging"
53 depends on IBM_EMAC
54 default n
55
56config IBM_EMAC_ZMII
57 bool
58 depends on IBM_EMAC && (NP405H || NP405L || 44x)
59 default y
60
61config IBM_EMAC_RGMII
62 bool
63 depends on IBM_EMAC && 440GX
64 default y
65
66config IBM_EMAC_TAH
67 bool
68 depends on IBM_EMAC && 440GX
69 default y
70
diff --git a/drivers/net/ibm_emac/Makefile b/drivers/net/ibm_emac/Makefile
deleted file mode 100644
index f98ddf0e807a..000000000000
--- a/drivers/net/ibm_emac/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the PowerPC 4xx on-chip ethernet driver
3#
4
5obj-$(CONFIG_IBM_EMAC) += ibm_emac.o
6
7ibm_emac-objs := ibm_emac_mal.o ibm_emac_core.o ibm_emac_phy.o
8ibm_emac-$(CONFIG_IBM_EMAC_ZMII) += ibm_emac_zmii.o
9ibm_emac-$(CONFIG_IBM_EMAC_RGMII) += ibm_emac_rgmii.o
10ibm_emac-$(CONFIG_IBM_EMAC_TAH) += ibm_emac_tah.o
11ibm_emac-$(CONFIG_IBM_EMAC_DEBUG) += ibm_emac_debug.o
diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h
deleted file mode 100644
index 97ed22bb4320..000000000000
--- a/drivers/net/ibm_emac/ibm_emac.h
+++ /dev/null
@@ -1,329 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac.h
3 *
4 * Register definitions for PowerPC 4xx on-chip ethernet contoller
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Armin Kuster <akuster@mvista.com>
12 * Copyright 2002-2004 MontaVista Software Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_EMAC_H_
21#define __IBM_EMAC_H_
22
23#include <linux/types.h>
24
25/* This is a simple check to prevent use of this driver on non-tested SoCs */
26#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
27 !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
28 !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \
29 !defined(CONFIG_440GR)
30#error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
31#endif
32
33/* EMAC registers Write Access rules */
34struct emac_regs {
35 u32 mr0; /* special */
36 u32 mr1; /* Reset */
37 u32 tmr0; /* special */
38 u32 tmr1; /* special */
39 u32 rmr; /* Reset */
40 u32 isr; /* Always */
41 u32 iser; /* Reset */
42 u32 iahr; /* Reset, R, T */
43 u32 ialr; /* Reset, R, T */
44 u32 vtpid; /* Reset, R, T */
45 u32 vtci; /* Reset, R, T */
46 u32 ptr; /* Reset, T */
47 u32 iaht1; /* Reset, R */
48 u32 iaht2; /* Reset, R */
49 u32 iaht3; /* Reset, R */
50 u32 iaht4; /* Reset, R */
51 u32 gaht1; /* Reset, R */
52 u32 gaht2; /* Reset, R */
53 u32 gaht3; /* Reset, R */
54 u32 gaht4; /* Reset, R */
55 u32 lsah;
56 u32 lsal;
57 u32 ipgvr; /* Reset, T */
58 u32 stacr; /* special */
59 u32 trtr; /* special */
60 u32 rwmr; /* Reset */
61 u32 octx;
62 u32 ocrx;
63 u32 ipcr;
64};
65
66#if !defined(CONFIG_IBM_EMAC4)
67#define EMAC_ETHTOOL_REGS_VER 0
68#define EMAC_ETHTOOL_REGS_SIZE (sizeof(struct emac_regs) - sizeof(u32))
69#else
70#define EMAC_ETHTOOL_REGS_VER 1
71#define EMAC_ETHTOOL_REGS_SIZE sizeof(struct emac_regs)
72#endif
73
74/* EMACx_MR0 */
75#define EMAC_MR0_RXI 0x80000000
76#define EMAC_MR0_TXI 0x40000000
77#define EMAC_MR0_SRST 0x20000000
78#define EMAC_MR0_TXE 0x10000000
79#define EMAC_MR0_RXE 0x08000000
80#define EMAC_MR0_WKE 0x04000000
81
82/* EMACx_MR1 */
83#define EMAC_MR1_FDE 0x80000000
84#define EMAC_MR1_ILE 0x40000000
85#define EMAC_MR1_VLE 0x20000000
86#define EMAC_MR1_EIFC 0x10000000
87#define EMAC_MR1_APP 0x08000000
88#define EMAC_MR1_IST 0x01000000
89
90#define EMAC_MR1_MF_MASK 0x00c00000
91#define EMAC_MR1_MF_10 0x00000000
92#define EMAC_MR1_MF_100 0x00400000
93#if !defined(CONFIG_IBM_EMAC4)
94#define EMAC_MR1_MF_1000 0x00000000
95#define EMAC_MR1_MF_1000GPCS 0x00000000
96#define EMAC_MR1_MF_IPPA(id) 0x00000000
97#else
98#define EMAC_MR1_MF_1000 0x00800000
99#define EMAC_MR1_MF_1000GPCS 0x00c00000
100#define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
101#endif
102
103#define EMAC_TX_FIFO_SIZE 2048
104
105#if !defined(CONFIG_IBM_EMAC4)
106#define EMAC_MR1_RFS_4K 0x00300000
107#define EMAC_MR1_RFS_16K 0x00000000
108#define EMAC_RX_FIFO_SIZE(gige) 4096
109#define EMAC_MR1_TFS_2K 0x00080000
110#define EMAC_MR1_TR0_MULT 0x00008000
111#define EMAC_MR1_JPSM 0x00000000
112#define EMAC_MR1_MWSW_001 0x00000000
113#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
114#else
115#define EMAC_MR1_RFS_4K 0x00180000
116#define EMAC_MR1_RFS_16K 0x00280000
117#define EMAC_RX_FIFO_SIZE(gige) ((gige) ? 16384 : 4096)
118#define EMAC_MR1_TFS_2K 0x00020000
119#define EMAC_MR1_TR 0x00008000
120#define EMAC_MR1_MWSW_001 0x00001000
121#define EMAC_MR1_JPSM 0x00000800
122#define EMAC_MR1_OBCI_MASK 0x00000038
123#define EMAC_MR1_OBCI_50 0x00000000
124#define EMAC_MR1_OBCI_66 0x00000008
125#define EMAC_MR1_OBCI_83 0x00000010
126#define EMAC_MR1_OBCI_100 0x00000018
127#define EMAC_MR1_OBCI_100P 0x00000020
128#define EMAC_MR1_OBCI(freq) ((freq) <= 50 ? EMAC_MR1_OBCI_50 : \
129 (freq) <= 66 ? EMAC_MR1_OBCI_66 : \
130 (freq) <= 83 ? EMAC_MR1_OBCI_83 : \
131 (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)
132#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR | \
133 EMAC_MR1_OBCI(opb))
134#endif
135
136/* EMACx_TMR0 */
137#define EMAC_TMR0_GNP 0x80000000
138#if !defined(CONFIG_IBM_EMAC4)
139#define EMAC_TMR0_DEFAULT 0x00000000
140#else
141#define EMAC_TMR0_TFAE_2_32 0x00000001
142#define EMAC_TMR0_TFAE_4_64 0x00000002
143#define EMAC_TMR0_TFAE_8_128 0x00000003
144#define EMAC_TMR0_TFAE_16_256 0x00000004
145#define EMAC_TMR0_TFAE_32_512 0x00000005
146#define EMAC_TMR0_TFAE_64_1024 0x00000006
147#define EMAC_TMR0_TFAE_128_2048 0x00000007
148#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32
149#endif
150#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
151
152/* EMACx_TMR1 */
153
154/* IBM manuals are not very clear here.
155 * This is my interpretation of how things are. --ebs
156 */
157#if defined(CONFIG_40x)
158#define EMAC_FIFO_ENTRY_SIZE 8
159#define EMAC_MAL_BURST_SIZE (16 * 4)
160#else
161#define EMAC_FIFO_ENTRY_SIZE 16
162#define EMAC_MAL_BURST_SIZE (64 * 4)
163#endif
164
165#if !defined(CONFIG_IBM_EMAC4)
166#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16))
167#else
168#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14))
169#endif
170
171/* EMACx_RMR */
172#define EMAC_RMR_SP 0x80000000
173#define EMAC_RMR_SFCS 0x40000000
174#define EMAC_RMR_RRP 0x20000000
175#define EMAC_RMR_RFP 0x10000000
176#define EMAC_RMR_ROP 0x08000000
177#define EMAC_RMR_RPIR 0x04000000
178#define EMAC_RMR_PPP 0x02000000
179#define EMAC_RMR_PME 0x01000000
180#define EMAC_RMR_PMME 0x00800000
181#define EMAC_RMR_IAE 0x00400000
182#define EMAC_RMR_MIAE 0x00200000
183#define EMAC_RMR_BAE 0x00100000
184#define EMAC_RMR_MAE 0x00080000
185#if !defined(CONFIG_IBM_EMAC4)
186#define EMAC_RMR_BASE 0x00000000
187#else
188#define EMAC_RMR_RFAF_2_32 0x00000001
189#define EMAC_RMR_RFAF_4_64 0x00000002
190#define EMAC_RMR_RFAF_8_128 0x00000003
191#define EMAC_RMR_RFAF_16_256 0x00000004
192#define EMAC_RMR_RFAF_32_512 0x00000005
193#define EMAC_RMR_RFAF_64_1024 0x00000006
194#define EMAC_RMR_RFAF_128_2048 0x00000007
195#define EMAC_RMR_BASE EMAC_RMR_RFAF_128_2048
196#endif
197
198/* EMACx_ISR & EMACx_ISER */
199#if !defined(CONFIG_IBM_EMAC4)
200#define EMAC_ISR_TXPE 0x00000000
201#define EMAC_ISR_RXPE 0x00000000
202#define EMAC_ISR_TXUE 0x00000000
203#define EMAC_ISR_RXOE 0x00000000
204#else
205#define EMAC_ISR_TXPE 0x20000000
206#define EMAC_ISR_RXPE 0x10000000
207#define EMAC_ISR_TXUE 0x08000000
208#define EMAC_ISR_RXOE 0x04000000
209#endif
210#define EMAC_ISR_OVR 0x02000000
211#define EMAC_ISR_PP 0x01000000
212#define EMAC_ISR_BP 0x00800000
213#define EMAC_ISR_RP 0x00400000
214#define EMAC_ISR_SE 0x00200000
215#define EMAC_ISR_ALE 0x00100000
216#define EMAC_ISR_BFCS 0x00080000
217#define EMAC_ISR_PTLE 0x00040000
218#define EMAC_ISR_ORE 0x00020000
219#define EMAC_ISR_IRE 0x00010000
220#define EMAC_ISR_SQE 0x00000080
221#define EMAC_ISR_TE 0x00000040
222#define EMAC_ISR_MOS 0x00000002
223#define EMAC_ISR_MOF 0x00000001
224
225/* EMACx_STACR */
226#define EMAC_STACR_PHYD_MASK 0xffff
227#define EMAC_STACR_PHYD_SHIFT 16
228#define EMAC_STACR_OC 0x00008000
229#define EMAC_STACR_PHYE 0x00004000
230#define EMAC_STACR_STAC_MASK 0x00003000
231#define EMAC_STACR_STAC_READ 0x00001000
232#define EMAC_STACR_STAC_WRITE 0x00002000
233#if !defined(CONFIG_IBM_EMAC4)
234#define EMAC_STACR_OPBC_MASK 0x00000C00
235#define EMAC_STACR_OPBC_50 0x00000000
236#define EMAC_STACR_OPBC_66 0x00000400
237#define EMAC_STACR_OPBC_83 0x00000800
238#define EMAC_STACR_OPBC_100 0x00000C00
239#define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
240 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
241 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
242#define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
243#else
244#define EMAC_STACR_BASE(opb) 0x00000000
245#endif
246#define EMAC_STACR_PCDA_MASK 0x1f
247#define EMAC_STACR_PCDA_SHIFT 5
248#define EMAC_STACR_PRA_MASK 0x1f
249
250/*
251 * For the 440SPe, AMCC inexplicably changed the polarity of
252 * the "operation complete" bit in the MII control register.
253 */
254#if defined(CONFIG_440SPE)
255static inline int emac_phy_done(u32 stacr)
256{
257 return !(stacr & EMAC_STACR_OC);
258};
259#define EMAC_STACR_START EMAC_STACR_OC
260
261#else /* CONFIG_440SPE */
262static inline int emac_phy_done(u32 stacr)
263{
264 return stacr & EMAC_STACR_OC;
265};
266#define EMAC_STACR_START 0
267#endif /* !CONFIG_440SPE */
268
269/* EMACx_TRTR */
270#if !defined(CONFIG_IBM_EMAC4)
271#define EMAC_TRTR_SHIFT 27
272#else
273#define EMAC_TRTR_SHIFT 24
274#endif
275#define EMAC_TRTR(size) ((((size) >> 6) - 1) << EMAC_TRTR_SHIFT)
276
277/* EMACx_RWMR */
278#if !defined(CONFIG_IBM_EMAC4)
279#define EMAC_RWMR(l,h) (((l) << 23) | ( ((h) & 0x1ff) << 7))
280#else
281#define EMAC_RWMR(l,h) (((l) << 22) | ( ((h) & 0x3ff) << 6))
282#endif
283
284/* EMAC specific TX descriptor control fields (write access) */
285#define EMAC_TX_CTRL_GFCS 0x0200
286#define EMAC_TX_CTRL_GP 0x0100
287#define EMAC_TX_CTRL_ISA 0x0080
288#define EMAC_TX_CTRL_RSA 0x0040
289#define EMAC_TX_CTRL_IVT 0x0020
290#define EMAC_TX_CTRL_RVT 0x0010
291#define EMAC_TX_CTRL_TAH_CSUM 0x000e
292
293/* EMAC specific TX descriptor status fields (read access) */
294#define EMAC_TX_ST_BFCS 0x0200
295#define EMAC_TX_ST_LCS 0x0080
296#define EMAC_TX_ST_ED 0x0040
297#define EMAC_TX_ST_EC 0x0020
298#define EMAC_TX_ST_LC 0x0010
299#define EMAC_TX_ST_MC 0x0008
300#define EMAC_TX_ST_SC 0x0004
301#define EMAC_TX_ST_UR 0x0002
302#define EMAC_TX_ST_SQE 0x0001
303#if !defined(CONFIG_IBM_EMAC_TAH)
304#define EMAC_IS_BAD_TX(v) ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
305 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
306 EMAC_TX_ST_MC | EMAC_TX_ST_UR))
307#else
308#define EMAC_IS_BAD_TX(v) ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
309 EMAC_TX_ST_EC | EMAC_TX_ST_LC))
310#endif
311
312/* EMAC specific RX descriptor status fields (read access) */
313#define EMAC_RX_ST_OE 0x0200
314#define EMAC_RX_ST_PP 0x0100
315#define EMAC_RX_ST_BP 0x0080
316#define EMAC_RX_ST_RP 0x0040
317#define EMAC_RX_ST_SE 0x0020
318#define EMAC_RX_ST_AE 0x0010
319#define EMAC_RX_ST_BFCS 0x0008
320#define EMAC_RX_ST_PTL 0x0004
321#define EMAC_RX_ST_ORE 0x0002
322#define EMAC_RX_ST_IRE 0x0001
323#define EMAC_RX_TAH_BAD_CSUM 0x0003
324#define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
325 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
326 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
327 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
328 EMAC_RX_ST_IRE )
329#endif /* __IBM_EMAC_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c
deleted file mode 100644
index 73664f226f32..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_core.c
+++ /dev/null
@@ -1,2263 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_core.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
12 * Armin Kuster <akuster@mvista.com>
13 * Johnnie Peters <jpeters@mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/errno.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/init.h>
29#include <linux/types.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/crc32.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/bitops.h>
37
38#include <asm/processor.h>
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/uaccess.h>
42#include <asm/ocp.h>
43
44#include "ibm_emac_core.h"
45#include "ibm_emac_debug.h"
46
47/*
48 * Lack of dma_unmap_???? calls is intentional.
49 *
50 * API-correct usage requires additional support state information to be
51 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
52 * EMAC design (e.g. TX buffer passed from network stack can be split into
53 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
54 * maintaining such information will add additional overhead.
55 * Current DMA API implementation for 4xx processors only ensures cache coherency
56 * and dma_unmap_???? routines are empty and are likely to stay this way.
57 * I decided to omit dma_unmap_??? calls because I don't want to add additional
58 * complexity just for the sake of following some abstract API, when it doesn't
59 * add any real benefit to the driver. I understand that this decision maybe
60 * controversial, but I really tried to make code API-correct and efficient
61 * at the same time and didn't come up with code I liked :(. --ebs
62 */
63
64#define DRV_NAME "emac"
65#define DRV_VERSION "3.54"
66#define DRV_DESC "PPC 4xx OCP EMAC driver"
67
68MODULE_DESCRIPTION(DRV_DESC);
69MODULE_AUTHOR
70 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
71MODULE_LICENSE("GPL");
72
73/* minimum number of free TX descriptors required to wake up TX process */
74#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
75
76/* If packet size is less than this number, we allocate small skb and copy packet
77 * contents into it instead of just sending original big skb up
78 */
79#define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
80
81/* Since multiple EMACs share MDIO lines in various ways, we need
82 * to avoid re-using the same PHY ID in cases where the arch didn't
83 * setup precise phy_map entries
84 */
85static u32 busy_phy_map;
86
87#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \
88 (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR))
89/* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us
90 * with PHY RX clock problem.
91 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which
92 * also allows controlling each EMAC clock
93 */
94static inline void EMAC_RX_CLK_TX(int idx)
95{
96 unsigned long flags;
97 local_irq_save(flags);
98
99#if defined(CONFIG_405EP)
100 mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));
101#else /* CONFIG_440EP || CONFIG_440GR */
102 SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx));
103#endif
104
105 local_irq_restore(flags);
106}
107
108static inline void EMAC_RX_CLK_DEFAULT(int idx)
109{
110 unsigned long flags;
111 local_irq_save(flags);
112
113#if defined(CONFIG_405EP)
114 mtdcr(0xf3, mfdcr(0xf3) & ~(1 << idx));
115#else /* CONFIG_440EP */
116 SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~(0x08000000 >> idx));
117#endif
118
119 local_irq_restore(flags);
120}
121#else
122#define EMAC_RX_CLK_TX(idx) ((void)0)
123#define EMAC_RX_CLK_DEFAULT(idx) ((void)0)
124#endif
125
126#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && defined(CONFIG_440GX)
127/* We can switch Ethernet clock to the internal source through SDR0_MFR[ECS],
128 * unfortunately this is less flexible than 440EP case, because it's a global
129 * setting for all EMACs, therefore we do this clock trick only during probe.
130 */
131#define EMAC_CLK_INTERNAL SDR_WRITE(DCRN_SDR_MFR, \
132 SDR_READ(DCRN_SDR_MFR) | 0x08000000)
133#define EMAC_CLK_EXTERNAL SDR_WRITE(DCRN_SDR_MFR, \
134 SDR_READ(DCRN_SDR_MFR) & ~0x08000000)
135#else
136#define EMAC_CLK_INTERNAL ((void)0)
137#define EMAC_CLK_EXTERNAL ((void)0)
138#endif
139
140/* I don't want to litter system log with timeout errors
141 * when we have brain-damaged PHY.
142 */
143static inline void emac_report_timeout_error(struct ocp_enet_private *dev,
144 const char *error)
145{
146#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
147 DBG("%d: %s" NL, dev->def->index, error);
148#else
149 if (net_ratelimit())
150 printk(KERN_ERR "emac%d: %s\n", dev->def->index, error);
151#endif
152}
153
154/* PHY polling intervals */
155#define PHY_POLL_LINK_ON HZ
156#define PHY_POLL_LINK_OFF (HZ / 5)
157
158/* Graceful stop timeouts in us.
159 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
160 */
161#define STOP_TIMEOUT_10 1230
162#define STOP_TIMEOUT_100 124
163#define STOP_TIMEOUT_1000 13
164#define STOP_TIMEOUT_1000_JUMBO 73
165
166/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
167static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
168 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
169 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
170 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
171 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
172 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
173 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
174 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
175 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
176 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
177 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
178 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
179 "tx_bd_excessive_collisions", "tx_bd_late_collision",
180 "tx_bd_multple_collisions", "tx_bd_single_collision",
181 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
182 "tx_errors"
183};
184
185static irqreturn_t emac_irq(int irq, void *dev_instance);
186static void emac_clean_tx_ring(struct ocp_enet_private *dev);
187
188static inline int emac_phy_supports_gige(int phy_mode)
189{
190 return phy_mode == PHY_MODE_GMII ||
191 phy_mode == PHY_MODE_RGMII ||
192 phy_mode == PHY_MODE_TBI ||
193 phy_mode == PHY_MODE_RTBI;
194}
195
196static inline int emac_phy_gpcs(int phy_mode)
197{
198 return phy_mode == PHY_MODE_TBI ||
199 phy_mode == PHY_MODE_RTBI;
200}
201
202static inline void emac_tx_enable(struct ocp_enet_private *dev)
203{
204 struct emac_regs __iomem *p = dev->emacp;
205 unsigned long flags;
206 u32 r;
207
208 local_irq_save(flags);
209
210 DBG("%d: tx_enable" NL, dev->def->index);
211
212 r = in_be32(&p->mr0);
213 if (!(r & EMAC_MR0_TXE))
214 out_be32(&p->mr0, r | EMAC_MR0_TXE);
215 local_irq_restore(flags);
216}
217
218static void emac_tx_disable(struct ocp_enet_private *dev)
219{
220 struct emac_regs __iomem *p = dev->emacp;
221 unsigned long flags;
222 u32 r;
223
224 local_irq_save(flags);
225
226 DBG("%d: tx_disable" NL, dev->def->index);
227
228 r = in_be32(&p->mr0);
229 if (r & EMAC_MR0_TXE) {
230 int n = dev->stop_timeout;
231 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
232 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
233 udelay(1);
234 --n;
235 }
236 if (unlikely(!n))
237 emac_report_timeout_error(dev, "TX disable timeout");
238 }
239 local_irq_restore(flags);
240}
241
242static void emac_rx_enable(struct ocp_enet_private *dev)
243{
244 struct emac_regs __iomem *p = dev->emacp;
245 unsigned long flags;
246 u32 r;
247
248 local_irq_save(flags);
249 if (unlikely(dev->commac.rx_stopped))
250 goto out;
251
252 DBG("%d: rx_enable" NL, dev->def->index);
253
254 r = in_be32(&p->mr0);
255 if (!(r & EMAC_MR0_RXE)) {
256 if (unlikely(!(r & EMAC_MR0_RXI))) {
257 /* Wait if previous async disable is still in progress */
258 int n = dev->stop_timeout;
259 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
260 udelay(1);
261 --n;
262 }
263 if (unlikely(!n))
264 emac_report_timeout_error(dev,
265 "RX disable timeout");
266 }
267 out_be32(&p->mr0, r | EMAC_MR0_RXE);
268 }
269 out:
270 local_irq_restore(flags);
271}
272
273static void emac_rx_disable(struct ocp_enet_private *dev)
274{
275 struct emac_regs __iomem *p = dev->emacp;
276 unsigned long flags;
277 u32 r;
278
279 local_irq_save(flags);
280
281 DBG("%d: rx_disable" NL, dev->def->index);
282
283 r = in_be32(&p->mr0);
284 if (r & EMAC_MR0_RXE) {
285 int n = dev->stop_timeout;
286 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
287 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
288 udelay(1);
289 --n;
290 }
291 if (unlikely(!n))
292 emac_report_timeout_error(dev, "RX disable timeout");
293 }
294 local_irq_restore(flags);
295}
296
297static inline void emac_rx_disable_async(struct ocp_enet_private *dev)
298{
299 struct emac_regs __iomem *p = dev->emacp;
300 unsigned long flags;
301 u32 r;
302
303 local_irq_save(flags);
304
305 DBG("%d: rx_disable_async" NL, dev->def->index);
306
307 r = in_be32(&p->mr0);
308 if (r & EMAC_MR0_RXE)
309 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
310 local_irq_restore(flags);
311}
312
313static int emac_reset(struct ocp_enet_private *dev)
314{
315 struct emac_regs __iomem *p = dev->emacp;
316 unsigned long flags;
317 int n = 20;
318
319 DBG("%d: reset" NL, dev->def->index);
320
321 local_irq_save(flags);
322
323 if (!dev->reset_failed) {
324 /* 40x erratum suggests stopping RX channel before reset,
325 * we stop TX as well
326 */
327 emac_rx_disable(dev);
328 emac_tx_disable(dev);
329 }
330
331 out_be32(&p->mr0, EMAC_MR0_SRST);
332 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
333 --n;
334 local_irq_restore(flags);
335
336 if (n) {
337 dev->reset_failed = 0;
338 return 0;
339 } else {
340 emac_report_timeout_error(dev, "reset timeout");
341 dev->reset_failed = 1;
342 return -ETIMEDOUT;
343 }
344}
345
346static void emac_hash_mc(struct ocp_enet_private *dev)
347{
348 struct emac_regs __iomem *p = dev->emacp;
349 u16 gaht[4] = { 0 };
350 struct dev_mc_list *dmi;
351
352 DBG("%d: hash_mc %d" NL, dev->def->index, dev->ndev->mc_count);
353
354 for (dmi = dev->ndev->mc_list; dmi; dmi = dmi->next) {
355 int bit;
356 DECLARE_MAC_BUF(mac);
357 DBG2("%d: mc %s" NL,
358 dev->def->index, print_mac(mac, dmi->dmi_addr));
359
360 bit = 63 - (ether_crc(ETH_ALEN, dmi->dmi_addr) >> 26);
361 gaht[bit >> 4] |= 0x8000 >> (bit & 0x0f);
362 }
363 out_be32(&p->gaht1, gaht[0]);
364 out_be32(&p->gaht2, gaht[1]);
365 out_be32(&p->gaht3, gaht[2]);
366 out_be32(&p->gaht4, gaht[3]);
367}
368
369static inline u32 emac_iff2rmr(struct net_device *ndev)
370{
371 u32 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE |
372 EMAC_RMR_BASE;
373
374 if (ndev->flags & IFF_PROMISC)
375 r |= EMAC_RMR_PME;
376 else if (ndev->flags & IFF_ALLMULTI || ndev->mc_count > 32)
377 r |= EMAC_RMR_PMME;
378 else if (ndev->mc_count > 0)
379 r |= EMAC_RMR_MAE;
380
381 return r;
382}
383
384static inline int emac_opb_mhz(void)
385{
386 return (ocp_sys_info.opb_bus_freq + 500000) / 1000000;
387}
388
389/* BHs disabled */
390static int emac_configure(struct ocp_enet_private *dev)
391{
392 struct emac_regs __iomem *p = dev->emacp;
393 struct net_device *ndev = dev->ndev;
394 int gige;
395 u32 r;
396
397 DBG("%d: configure" NL, dev->def->index);
398
399 if (emac_reset(dev) < 0)
400 return -ETIMEDOUT;
401
402 tah_reset(dev->tah_dev);
403
404 /* Mode register */
405 r = EMAC_MR1_BASE(emac_opb_mhz()) | EMAC_MR1_VLE | EMAC_MR1_IST;
406 if (dev->phy.duplex == DUPLEX_FULL)
407 r |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
408 dev->stop_timeout = STOP_TIMEOUT_10;
409 switch (dev->phy.speed) {
410 case SPEED_1000:
411 if (emac_phy_gpcs(dev->phy.mode)) {
412 r |= EMAC_MR1_MF_1000GPCS |
413 EMAC_MR1_MF_IPPA(dev->phy.address);
414
415 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
416 * identify this GPCS PHY later.
417 */
418 out_be32(&p->ipcr, 0xdeadbeef);
419 } else
420 r |= EMAC_MR1_MF_1000;
421 r |= EMAC_MR1_RFS_16K;
422 gige = 1;
423
424 if (dev->ndev->mtu > ETH_DATA_LEN) {
425 r |= EMAC_MR1_JPSM;
426 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
427 } else
428 dev->stop_timeout = STOP_TIMEOUT_1000;
429 break;
430 case SPEED_100:
431 r |= EMAC_MR1_MF_100;
432 dev->stop_timeout = STOP_TIMEOUT_100;
433 /* Fall through */
434 default:
435 r |= EMAC_MR1_RFS_4K;
436 gige = 0;
437 break;
438 }
439
440 if (dev->rgmii_dev)
441 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_input,
442 dev->phy.speed);
443 else
444 zmii_set_speed(dev->zmii_dev, dev->zmii_input, dev->phy.speed);
445
446#if !defined(CONFIG_40x)
447 /* on 40x erratum forces us to NOT use integrated flow control,
448 * let's hope it works on 44x ;)
449 */
450 if (dev->phy.duplex == DUPLEX_FULL) {
451 if (dev->phy.pause)
452 r |= EMAC_MR1_EIFC | EMAC_MR1_APP;
453 else if (dev->phy.asym_pause)
454 r |= EMAC_MR1_APP;
455 }
456#endif
457 out_be32(&p->mr1, r);
458
459 /* Set individual MAC address */
460 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
461 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
462 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
463 ndev->dev_addr[5]);
464
465 /* VLAN Tag Protocol ID */
466 out_be32(&p->vtpid, 0x8100);
467
468 /* Receive mode register */
469 r = emac_iff2rmr(ndev);
470 if (r & EMAC_RMR_MAE)
471 emac_hash_mc(dev);
472 out_be32(&p->rmr, r);
473
474 /* FIFOs thresholds */
475 r = EMAC_TMR1((EMAC_MAL_BURST_SIZE / EMAC_FIFO_ENTRY_SIZE) + 1,
476 EMAC_TX_FIFO_SIZE / 2 / EMAC_FIFO_ENTRY_SIZE);
477 out_be32(&p->tmr1, r);
478 out_be32(&p->trtr, EMAC_TRTR(EMAC_TX_FIFO_SIZE / 2));
479
480 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
481 there should be still enough space in FIFO to allow the our link
482 partner time to process this frame and also time to send PAUSE
483 frame itself.
484
485 Here is the worst case scenario for the RX FIFO "headroom"
486 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
487
488 1) One maximum-length frame on TX 1522 bytes
489 2) One PAUSE frame time 64 bytes
490 3) PAUSE frame decode time allowance 64 bytes
491 4) One maximum-length frame on RX 1522 bytes
492 5) Round-trip propagation delay of the link (100Mb) 15 bytes
493 ----------
494 3187 bytes
495
496 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
497 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
498 */
499 r = EMAC_RWMR(EMAC_RX_FIFO_SIZE(gige) / 8 / EMAC_FIFO_ENTRY_SIZE,
500 EMAC_RX_FIFO_SIZE(gige) / 4 / EMAC_FIFO_ENTRY_SIZE);
501 out_be32(&p->rwmr, r);
502
503 /* Set PAUSE timer to the maximum */
504 out_be32(&p->ptr, 0xffff);
505
506 /* IRQ sources */
507 out_be32(&p->iser, EMAC_ISR_TXPE | EMAC_ISR_RXPE | /* EMAC_ISR_TXUE |
508 EMAC_ISR_RXOE | */ EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
509 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
510 EMAC_ISR_IRE | EMAC_ISR_TE);
511
512 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
513 if (emac_phy_gpcs(dev->phy.mode))
514 mii_reset_phy(&dev->phy);
515
516 return 0;
517}
518
519/* BHs disabled */
520static void emac_reinitialize(struct ocp_enet_private *dev)
521{
522 DBG("%d: reinitialize" NL, dev->def->index);
523
524 if (!emac_configure(dev)) {
525 emac_tx_enable(dev);
526 emac_rx_enable(dev);
527 }
528}
529
530/* BHs disabled */
531static void emac_full_tx_reset(struct net_device *ndev)
532{
533 struct ocp_enet_private *dev = ndev->priv;
534 struct ocp_func_emac_data *emacdata = dev->def->additions;
535
536 DBG("%d: full_tx_reset" NL, dev->def->index);
537
538 emac_tx_disable(dev);
539 mal_disable_tx_channel(dev->mal, emacdata->mal_tx_chan);
540 emac_clean_tx_ring(dev);
541 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
542
543 emac_configure(dev);
544
545 mal_enable_tx_channel(dev->mal, emacdata->mal_tx_chan);
546 emac_tx_enable(dev);
547 emac_rx_enable(dev);
548
549 netif_wake_queue(ndev);
550}
551
552static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
553{
554 struct emac_regs __iomem *p = dev->emacp;
555 u32 r;
556 int n;
557
558 DBG2("%d: mdio_read(%02x,%02x)" NL, dev->def->index, id, reg);
559
560 /* Enable proper MDIO port */
561 zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);
562
563 /* Wait for management interface to become idle */
564 n = 10;
565 while (!emac_phy_done(in_be32(&p->stacr))) {
566 udelay(1);
567 if (!--n)
568 goto to;
569 }
570
571 /* Issue read command */
572 out_be32(&p->stacr,
573 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ |
574 (reg & EMAC_STACR_PRA_MASK)
575 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)
576 | EMAC_STACR_START);
577
578 /* Wait for read to complete */
579 n = 100;
580 while (!emac_phy_done(r = in_be32(&p->stacr))) {
581 udelay(1);
582 if (!--n)
583 goto to;
584 }
585
586 if (unlikely(r & EMAC_STACR_PHYE)) {
587 DBG("%d: mdio_read(%02x, %02x) failed" NL, dev->def->index,
588 id, reg);
589 return -EREMOTEIO;
590 }
591
592 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
593 DBG2("%d: mdio_read -> %04x" NL, dev->def->index, r);
594 return r;
595 to:
596 DBG("%d: MII management interface timeout (read)" NL, dev->def->index);
597 return -ETIMEDOUT;
598}
599
600static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
601 u16 val)
602{
603 struct emac_regs __iomem *p = dev->emacp;
604 int n;
605
606 DBG2("%d: mdio_write(%02x,%02x,%04x)" NL, dev->def->index, id, reg,
607 val);
608
609 /* Enable proper MDIO port */
610 zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);
611
612 /* Wait for management interface to be idle */
613 n = 10;
614 while (!emac_phy_done(in_be32(&p->stacr))) {
615 udelay(1);
616 if (!--n)
617 goto to;
618 }
619
620 /* Issue write command */
621 out_be32(&p->stacr,
622 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE |
623 (reg & EMAC_STACR_PRA_MASK) |
624 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
625 (val << EMAC_STACR_PHYD_SHIFT) | EMAC_STACR_START);
626
627 /* Wait for write to complete */
628 n = 100;
629 while (!emac_phy_done(in_be32(&p->stacr))) {
630 udelay(1);
631 if (!--n)
632 goto to;
633 }
634 return;
635 to:
636 DBG("%d: MII management interface timeout (write)" NL, dev->def->index);
637}
638
639static int emac_mdio_read(struct net_device *ndev, int id, int reg)
640{
641 struct ocp_enet_private *dev = ndev->priv;
642 int res;
643
644 local_bh_disable();
645 res = __emac_mdio_read(dev->mdio_dev ? dev->mdio_dev : dev, (u8) id,
646 (u8) reg);
647 local_bh_enable();
648 return res;
649}
650
651static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
652{
653 struct ocp_enet_private *dev = ndev->priv;
654
655 local_bh_disable();
656 __emac_mdio_write(dev->mdio_dev ? dev->mdio_dev : dev, (u8) id,
657 (u8) reg, (u16) val);
658 local_bh_enable();
659}
660
661/* BHs disabled */
662static void emac_set_multicast_list(struct net_device *ndev)
663{
664 struct ocp_enet_private *dev = ndev->priv;
665 struct emac_regs __iomem *p = dev->emacp;
666 u32 rmr = emac_iff2rmr(ndev);
667
668 DBG("%d: multicast %08x" NL, dev->def->index, rmr);
669 BUG_ON(!netif_running(dev->ndev));
670
671 /* I decided to relax register access rules here to avoid
672 * full EMAC reset.
673 *
674 * There is a real problem with EMAC4 core if we use MWSW_001 bit
675 * in MR1 register and do a full EMAC reset.
676 * One TX BD status update is delayed and, after EMAC reset, it
677 * never happens, resulting in TX hung (it'll be recovered by TX
678 * timeout handler eventually, but this is just gross).
679 * So we either have to do full TX reset or try to cheat here :)
680 *
681 * The only required change is to RX mode register, so I *think* all
682 * we need is just to stop RX channel. This seems to work on all
683 * tested SoCs. --ebs
684 */
685 emac_rx_disable(dev);
686 if (rmr & EMAC_RMR_MAE)
687 emac_hash_mc(dev);
688 out_be32(&p->rmr, rmr);
689 emac_rx_enable(dev);
690}
691
692/* BHs disabled */
693static int emac_resize_rx_ring(struct ocp_enet_private *dev, int new_mtu)
694{
695 struct ocp_func_emac_data *emacdata = dev->def->additions;
696 int rx_sync_size = emac_rx_sync_size(new_mtu);
697 int rx_skb_size = emac_rx_skb_size(new_mtu);
698 int i, ret = 0;
699
700 emac_rx_disable(dev);
701 mal_disable_rx_channel(dev->mal, emacdata->mal_rx_chan);
702
703 if (dev->rx_sg_skb) {
704 ++dev->estats.rx_dropped_resize;
705 dev_kfree_skb(dev->rx_sg_skb);
706 dev->rx_sg_skb = NULL;
707 }
708
709 /* Make a first pass over RX ring and mark BDs ready, dropping
710 * non-processed packets on the way. We need this as a separate pass
711 * to simplify error recovery in the case of allocation failure later.
712 */
713 for (i = 0; i < NUM_RX_BUFF; ++i) {
714 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
715 ++dev->estats.rx_dropped_resize;
716
717 dev->rx_desc[i].data_len = 0;
718 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
719 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
720 }
721
722 /* Reallocate RX ring only if bigger skb buffers are required */
723 if (rx_skb_size <= dev->rx_skb_size)
724 goto skip;
725
726 /* Second pass, allocate new skbs */
727 for (i = 0; i < NUM_RX_BUFF; ++i) {
728 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
729 if (!skb) {
730 ret = -ENOMEM;
731 goto oom;
732 }
733
734 BUG_ON(!dev->rx_skb[i]);
735 dev_kfree_skb(dev->rx_skb[i]);
736
737 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
738 dev->rx_desc[i].data_ptr =
739 dma_map_single(dev->ldev, skb->data - 2, rx_sync_size,
740 DMA_FROM_DEVICE) + 2;
741 dev->rx_skb[i] = skb;
742 }
743 skip:
744 /* Check if we need to change "Jumbo" bit in MR1 */
745 if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
746 /* This is to prevent starting RX channel in emac_rx_enable() */
747 dev->commac.rx_stopped = 1;
748
749 dev->ndev->mtu = new_mtu;
750 emac_full_tx_reset(dev->ndev);
751 }
752
753 mal_set_rcbs(dev->mal, emacdata->mal_rx_chan, emac_rx_size(new_mtu));
754 oom:
755 /* Restart RX */
756 dev->commac.rx_stopped = dev->rx_slot = 0;
757 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
758 emac_rx_enable(dev);
759
760 return ret;
761}
762
763/* Process ctx, rtnl_lock semaphore */
764static int emac_change_mtu(struct net_device *ndev, int new_mtu)
765{
766 struct ocp_enet_private *dev = ndev->priv;
767 int ret = 0;
768
769 if (new_mtu < EMAC_MIN_MTU || new_mtu > EMAC_MAX_MTU)
770 return -EINVAL;
771
772 DBG("%d: change_mtu(%d)" NL, dev->def->index, new_mtu);
773
774 local_bh_disable();
775 if (netif_running(ndev)) {
776 /* Check if we really need to reinitalize RX ring */
777 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
778 ret = emac_resize_rx_ring(dev, new_mtu);
779 }
780
781 if (!ret) {
782 ndev->mtu = new_mtu;
783 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
784 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
785 }
786 local_bh_enable();
787
788 return ret;
789}
790
791static void emac_clean_tx_ring(struct ocp_enet_private *dev)
792{
793 int i;
794 for (i = 0; i < NUM_TX_BUFF; ++i) {
795 if (dev->tx_skb[i]) {
796 dev_kfree_skb(dev->tx_skb[i]);
797 dev->tx_skb[i] = NULL;
798 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
799 ++dev->estats.tx_dropped;
800 }
801 dev->tx_desc[i].ctrl = 0;
802 dev->tx_desc[i].data_ptr = 0;
803 }
804}
805
806static void emac_clean_rx_ring(struct ocp_enet_private *dev)
807{
808 int i;
809 for (i = 0; i < NUM_RX_BUFF; ++i)
810 if (dev->rx_skb[i]) {
811 dev->rx_desc[i].ctrl = 0;
812 dev_kfree_skb(dev->rx_skb[i]);
813 dev->rx_skb[i] = NULL;
814 dev->rx_desc[i].data_ptr = 0;
815 }
816
817 if (dev->rx_sg_skb) {
818 dev_kfree_skb(dev->rx_sg_skb);
819 dev->rx_sg_skb = NULL;
820 }
821}
822
823static inline int emac_alloc_rx_skb(struct ocp_enet_private *dev, int slot,
824 gfp_t flags)
825{
826 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
827 if (unlikely(!skb))
828 return -ENOMEM;
829
830 dev->rx_skb[slot] = skb;
831 dev->rx_desc[slot].data_len = 0;
832
833 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
834 dev->rx_desc[slot].data_ptr =
835 dma_map_single(dev->ldev, skb->data - 2, dev->rx_sync_size,
836 DMA_FROM_DEVICE) + 2;
837 barrier();
838 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
839 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
840
841 return 0;
842}
843
844static void emac_print_link_status(struct ocp_enet_private *dev)
845{
846 if (netif_carrier_ok(dev->ndev))
847 printk(KERN_INFO "%s: link is up, %d %s%s\n",
848 dev->ndev->name, dev->phy.speed,
849 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
850 dev->phy.pause ? ", pause enabled" :
851 dev->phy.asym_pause ? ", assymetric pause enabled" : "");
852 else
853 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
854}
855
856/* Process ctx, rtnl_lock semaphore */
857static int emac_open(struct net_device *ndev)
858{
859 struct ocp_enet_private *dev = ndev->priv;
860 struct ocp_func_emac_data *emacdata = dev->def->additions;
861 int err, i;
862
863 DBG("%d: open" NL, dev->def->index);
864
865 /* Setup error IRQ handler */
866 err = request_irq(dev->def->irq, emac_irq, 0, "EMAC", dev);
867 if (err) {
868 printk(KERN_ERR "%s: failed to request IRQ %d\n",
869 ndev->name, dev->def->irq);
870 return err;
871 }
872
873 /* Allocate RX ring */
874 for (i = 0; i < NUM_RX_BUFF; ++i)
875 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
876 printk(KERN_ERR "%s: failed to allocate RX ring\n",
877 ndev->name);
878 goto oom;
879 }
880
881 local_bh_disable();
882 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot =
883 dev->commac.rx_stopped = 0;
884 dev->rx_sg_skb = NULL;
885
886 if (dev->phy.address >= 0) {
887 int link_poll_interval;
888 if (dev->phy.def->ops->poll_link(&dev->phy)) {
889 dev->phy.def->ops->read_link(&dev->phy);
890 EMAC_RX_CLK_DEFAULT(dev->def->index);
891 netif_carrier_on(dev->ndev);
892 link_poll_interval = PHY_POLL_LINK_ON;
893 } else {
894 EMAC_RX_CLK_TX(dev->def->index);
895 netif_carrier_off(dev->ndev);
896 link_poll_interval = PHY_POLL_LINK_OFF;
897 }
898 mod_timer(&dev->link_timer, jiffies + link_poll_interval);
899 emac_print_link_status(dev);
900 } else
901 netif_carrier_on(dev->ndev);
902
903 emac_configure(dev);
904 mal_poll_add(dev->mal, &dev->commac);
905 mal_enable_tx_channel(dev->mal, emacdata->mal_tx_chan);
906 mal_set_rcbs(dev->mal, emacdata->mal_rx_chan, emac_rx_size(ndev->mtu));
907 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
908 emac_tx_enable(dev);
909 emac_rx_enable(dev);
910 netif_start_queue(ndev);
911 local_bh_enable();
912
913 return 0;
914 oom:
915 emac_clean_rx_ring(dev);
916 free_irq(dev->def->irq, dev);
917 return -ENOMEM;
918}
919
920/* BHs disabled */
921static int emac_link_differs(struct ocp_enet_private *dev)
922{
923 u32 r = in_be32(&dev->emacp->mr1);
924
925 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
926 int speed, pause, asym_pause;
927
928 if (r & EMAC_MR1_MF_1000)
929 speed = SPEED_1000;
930 else if (r & EMAC_MR1_MF_100)
931 speed = SPEED_100;
932 else
933 speed = SPEED_10;
934
935 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
936 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
937 pause = 1;
938 asym_pause = 0;
939 break;
940 case EMAC_MR1_APP:
941 pause = 0;
942 asym_pause = 1;
943 break;
944 default:
945 pause = asym_pause = 0;
946 }
947 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
948 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
949}
950
951/* BHs disabled */
952static void emac_link_timer(unsigned long data)
953{
954 struct ocp_enet_private *dev = (struct ocp_enet_private *)data;
955 int link_poll_interval;
956
957 DBG2("%d: link timer" NL, dev->def->index);
958
959 if (dev->phy.def->ops->poll_link(&dev->phy)) {
960 if (!netif_carrier_ok(dev->ndev)) {
961 EMAC_RX_CLK_DEFAULT(dev->def->index);
962
963 /* Get new link parameters */
964 dev->phy.def->ops->read_link(&dev->phy);
965
966 if (dev->tah_dev || emac_link_differs(dev))
967 emac_full_tx_reset(dev->ndev);
968
969 netif_carrier_on(dev->ndev);
970 emac_print_link_status(dev);
971 }
972 link_poll_interval = PHY_POLL_LINK_ON;
973 } else {
974 if (netif_carrier_ok(dev->ndev)) {
975 EMAC_RX_CLK_TX(dev->def->index);
976#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
977 emac_reinitialize(dev);
978#endif
979 netif_carrier_off(dev->ndev);
980 emac_print_link_status(dev);
981 }
982
983 /* Retry reset if the previous attempt failed.
984 * This is needed mostly for CONFIG_IBM_EMAC_PHY_RX_CLK_FIX
985 * case, but I left it here because it shouldn't trigger for
986 * sane PHYs anyway.
987 */
988 if (unlikely(dev->reset_failed))
989 emac_reinitialize(dev);
990
991 link_poll_interval = PHY_POLL_LINK_OFF;
992 }
993 mod_timer(&dev->link_timer, jiffies + link_poll_interval);
994}
995
996/* BHs disabled */
997static void emac_force_link_update(struct ocp_enet_private *dev)
998{
999 netif_carrier_off(dev->ndev);
1000 if (timer_pending(&dev->link_timer))
1001 mod_timer(&dev->link_timer, jiffies + PHY_POLL_LINK_OFF);
1002}
1003
1004/* Process ctx, rtnl_lock semaphore */
1005static int emac_close(struct net_device *ndev)
1006{
1007 struct ocp_enet_private *dev = ndev->priv;
1008 struct ocp_func_emac_data *emacdata = dev->def->additions;
1009
1010 DBG("%d: close" NL, dev->def->index);
1011
1012 local_bh_disable();
1013
1014 if (dev->phy.address >= 0)
1015 del_timer_sync(&dev->link_timer);
1016
1017 netif_stop_queue(ndev);
1018 emac_rx_disable(dev);
1019 emac_tx_disable(dev);
1020 mal_disable_rx_channel(dev->mal, emacdata->mal_rx_chan);
1021 mal_disable_tx_channel(dev->mal, emacdata->mal_tx_chan);
1022 mal_poll_del(dev->mal, &dev->commac);
1023 local_bh_enable();
1024
1025 emac_clean_tx_ring(dev);
1026 emac_clean_rx_ring(dev);
1027 free_irq(dev->def->irq, dev);
1028
1029 return 0;
1030}
1031
1032static inline u16 emac_tx_csum(struct ocp_enet_private *dev,
1033 struct sk_buff *skb)
1034{
1035#if defined(CONFIG_IBM_EMAC_TAH)
1036 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1037 ++dev->stats.tx_packets_csum;
1038 return EMAC_TX_CTRL_TAH_CSUM;
1039 }
1040#endif
1041 return 0;
1042}
1043
1044static inline int emac_xmit_finish(struct ocp_enet_private *dev, int len)
1045{
1046 struct emac_regs __iomem *p = dev->emacp;
1047 struct net_device *ndev = dev->ndev;
1048
1049 /* Send the packet out */
1050 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1051
1052 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1053 netif_stop_queue(ndev);
1054 DBG2("%d: stopped TX queue" NL, dev->def->index);
1055 }
1056
1057 ndev->trans_start = jiffies;
1058 ++dev->stats.tx_packets;
1059 dev->stats.tx_bytes += len;
1060
1061 return 0;
1062}
1063
1064/* BHs disabled */
1065static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1066{
1067 struct ocp_enet_private *dev = ndev->priv;
1068 unsigned int len = skb->len;
1069 int slot;
1070
1071 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1072 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1073
1074 slot = dev->tx_slot++;
1075 if (dev->tx_slot == NUM_TX_BUFF) {
1076 dev->tx_slot = 0;
1077 ctrl |= MAL_TX_CTRL_WRAP;
1078 }
1079
1080 DBG2("%d: xmit(%u) %d" NL, dev->def->index, len, slot);
1081
1082 dev->tx_skb[slot] = skb;
1083 dev->tx_desc[slot].data_ptr = dma_map_single(dev->ldev, skb->data, len,
1084 DMA_TO_DEVICE);
1085 dev->tx_desc[slot].data_len = (u16) len;
1086 barrier();
1087 dev->tx_desc[slot].ctrl = ctrl;
1088
1089 return emac_xmit_finish(dev, len);
1090}
1091
1092#if defined(CONFIG_IBM_EMAC_TAH)
1093static inline int emac_xmit_split(struct ocp_enet_private *dev, int slot,
1094 u32 pd, int len, int last, u16 base_ctrl)
1095{
1096 while (1) {
1097 u16 ctrl = base_ctrl;
1098 int chunk = min(len, MAL_MAX_TX_SIZE);
1099 len -= chunk;
1100
1101 slot = (slot + 1) % NUM_TX_BUFF;
1102
1103 if (last && !len)
1104 ctrl |= MAL_TX_CTRL_LAST;
1105 if (slot == NUM_TX_BUFF - 1)
1106 ctrl |= MAL_TX_CTRL_WRAP;
1107
1108 dev->tx_skb[slot] = NULL;
1109 dev->tx_desc[slot].data_ptr = pd;
1110 dev->tx_desc[slot].data_len = (u16) chunk;
1111 dev->tx_desc[slot].ctrl = ctrl;
1112 ++dev->tx_cnt;
1113
1114 if (!len)
1115 break;
1116
1117 pd += chunk;
1118 }
1119 return slot;
1120}
1121
1122/* BHs disabled (SG version for TAH equipped EMACs) */
1123static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1124{
1125 struct ocp_enet_private *dev = ndev->priv;
1126 int nr_frags = skb_shinfo(skb)->nr_frags;
1127 int len = skb->len, chunk;
1128 int slot, i;
1129 u16 ctrl;
1130 u32 pd;
1131
1132 /* This is common "fast" path */
1133 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1134 return emac_start_xmit(skb, ndev);
1135
1136 len -= skb->data_len;
1137
1138 /* Note, this is only an *estimation*, we can still run out of empty
1139 * slots because of the additional fragmentation into
1140 * MAL_MAX_TX_SIZE-sized chunks
1141 */
1142 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1143 goto stop_queue;
1144
1145 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1146 emac_tx_csum(dev, skb);
1147 slot = dev->tx_slot;
1148
1149 /* skb data */
1150 dev->tx_skb[slot] = NULL;
1151 chunk = min(len, MAL_MAX_TX_SIZE);
1152 dev->tx_desc[slot].data_ptr = pd =
1153 dma_map_single(dev->ldev, skb->data, len, DMA_TO_DEVICE);
1154 dev->tx_desc[slot].data_len = (u16) chunk;
1155 len -= chunk;
1156 if (unlikely(len))
1157 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1158 ctrl);
1159 /* skb fragments */
1160 for (i = 0; i < nr_frags; ++i) {
1161 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1162 len = frag->size;
1163
1164 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1165 goto undo_frame;
1166
1167 pd = dma_map_page(dev->ldev, frag->page, frag->page_offset, len,
1168 DMA_TO_DEVICE);
1169
1170 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1171 ctrl);
1172 }
1173
1174 DBG2("%d: xmit_sg(%u) %d - %d" NL, dev->def->index, skb->len,
1175 dev->tx_slot, slot);
1176
1177 /* Attach skb to the last slot so we don't release it too early */
1178 dev->tx_skb[slot] = skb;
1179
1180 /* Send the packet out */
1181 if (dev->tx_slot == NUM_TX_BUFF - 1)
1182 ctrl |= MAL_TX_CTRL_WRAP;
1183 barrier();
1184 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1185 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1186
1187 return emac_xmit_finish(dev, skb->len);
1188
1189 undo_frame:
1190 /* Well, too bad. Our previous estimation was overly optimistic.
1191 * Undo everything.
1192 */
1193 while (slot != dev->tx_slot) {
1194 dev->tx_desc[slot].ctrl = 0;
1195 --dev->tx_cnt;
1196 if (--slot < 0)
1197 slot = NUM_TX_BUFF - 1;
1198 }
1199 ++dev->estats.tx_undo;
1200
1201 stop_queue:
1202 netif_stop_queue(ndev);
1203 DBG2("%d: stopped TX queue" NL, dev->def->index);
1204 return 1;
1205}
1206#else
1207# define emac_start_xmit_sg emac_start_xmit
1208#endif /* !defined(CONFIG_IBM_EMAC_TAH) */
1209
1210/* BHs disabled */
1211static void emac_parse_tx_error(struct ocp_enet_private *dev, u16 ctrl)
1212{
1213 struct ibm_emac_error_stats *st = &dev->estats;
1214 DBG("%d: BD TX error %04x" NL, dev->def->index, ctrl);
1215
1216 ++st->tx_bd_errors;
1217 if (ctrl & EMAC_TX_ST_BFCS)
1218 ++st->tx_bd_bad_fcs;
1219 if (ctrl & EMAC_TX_ST_LCS)
1220 ++st->tx_bd_carrier_loss;
1221 if (ctrl & EMAC_TX_ST_ED)
1222 ++st->tx_bd_excessive_deferral;
1223 if (ctrl & EMAC_TX_ST_EC)
1224 ++st->tx_bd_excessive_collisions;
1225 if (ctrl & EMAC_TX_ST_LC)
1226 ++st->tx_bd_late_collision;
1227 if (ctrl & EMAC_TX_ST_MC)
1228 ++st->tx_bd_multple_collisions;
1229 if (ctrl & EMAC_TX_ST_SC)
1230 ++st->tx_bd_single_collision;
1231 if (ctrl & EMAC_TX_ST_UR)
1232 ++st->tx_bd_underrun;
1233 if (ctrl & EMAC_TX_ST_SQE)
1234 ++st->tx_bd_sqe;
1235}
1236
1237static void emac_poll_tx(void *param)
1238{
1239 struct ocp_enet_private *dev = param;
1240 DBG2("%d: poll_tx, %d %d" NL, dev->def->index, dev->tx_cnt,
1241 dev->ack_slot);
1242
1243 if (dev->tx_cnt) {
1244 u16 ctrl;
1245 int slot = dev->ack_slot, n = 0;
1246 again:
1247 ctrl = dev->tx_desc[slot].ctrl;
1248 if (!(ctrl & MAL_TX_CTRL_READY)) {
1249 struct sk_buff *skb = dev->tx_skb[slot];
1250 ++n;
1251
1252 if (skb) {
1253 dev_kfree_skb(skb);
1254 dev->tx_skb[slot] = NULL;
1255 }
1256 slot = (slot + 1) % NUM_TX_BUFF;
1257
1258 if (unlikely(EMAC_IS_BAD_TX(ctrl)))
1259 emac_parse_tx_error(dev, ctrl);
1260
1261 if (--dev->tx_cnt)
1262 goto again;
1263 }
1264 if (n) {
1265 dev->ack_slot = slot;
1266 if (netif_queue_stopped(dev->ndev) &&
1267 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1268 netif_wake_queue(dev->ndev);
1269
1270 DBG2("%d: tx %d pkts" NL, dev->def->index, n);
1271 }
1272 }
1273}
1274
1275static inline void emac_recycle_rx_skb(struct ocp_enet_private *dev, int slot,
1276 int len)
1277{
1278 struct sk_buff *skb = dev->rx_skb[slot];
1279 DBG2("%d: recycle %d %d" NL, dev->def->index, slot, len);
1280
1281 if (len)
1282 dma_map_single(dev->ldev, skb->data - 2,
1283 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1284
1285 dev->rx_desc[slot].data_len = 0;
1286 barrier();
1287 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1288 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1289}
1290
1291static void emac_parse_rx_error(struct ocp_enet_private *dev, u16 ctrl)
1292{
1293 struct ibm_emac_error_stats *st = &dev->estats;
1294 DBG("%d: BD RX error %04x" NL, dev->def->index, ctrl);
1295
1296 ++st->rx_bd_errors;
1297 if (ctrl & EMAC_RX_ST_OE)
1298 ++st->rx_bd_overrun;
1299 if (ctrl & EMAC_RX_ST_BP)
1300 ++st->rx_bd_bad_packet;
1301 if (ctrl & EMAC_RX_ST_RP)
1302 ++st->rx_bd_runt_packet;
1303 if (ctrl & EMAC_RX_ST_SE)
1304 ++st->rx_bd_short_event;
1305 if (ctrl & EMAC_RX_ST_AE)
1306 ++st->rx_bd_alignment_error;
1307 if (ctrl & EMAC_RX_ST_BFCS)
1308 ++st->rx_bd_bad_fcs;
1309 if (ctrl & EMAC_RX_ST_PTL)
1310 ++st->rx_bd_packet_too_long;
1311 if (ctrl & EMAC_RX_ST_ORE)
1312 ++st->rx_bd_out_of_range;
1313 if (ctrl & EMAC_RX_ST_IRE)
1314 ++st->rx_bd_in_range;
1315}
1316
1317static inline void emac_rx_csum(struct ocp_enet_private *dev,
1318 struct sk_buff *skb, u16 ctrl)
1319{
1320#if defined(CONFIG_IBM_EMAC_TAH)
1321 if (!ctrl && dev->tah_dev) {
1322 skb->ip_summed = CHECKSUM_UNNECESSARY;
1323 ++dev->stats.rx_packets_csum;
1324 }
1325#endif
1326}
1327
1328static inline int emac_rx_sg_append(struct ocp_enet_private *dev, int slot)
1329{
1330 if (likely(dev->rx_sg_skb != NULL)) {
1331 int len = dev->rx_desc[slot].data_len;
1332 int tot_len = dev->rx_sg_skb->len + len;
1333
1334 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1335 ++dev->estats.rx_dropped_mtu;
1336 dev_kfree_skb(dev->rx_sg_skb);
1337 dev->rx_sg_skb = NULL;
1338 } else {
1339 cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
1340 dev->rx_skb[slot]->data, len);
1341 skb_put(dev->rx_sg_skb, len);
1342 emac_recycle_rx_skb(dev, slot, len);
1343 return 0;
1344 }
1345 }
1346 emac_recycle_rx_skb(dev, slot, 0);
1347 return -1;
1348}
1349
1350/* BHs disabled */
1351static int emac_poll_rx(void *param, int budget)
1352{
1353 struct ocp_enet_private *dev = param;
1354 int slot = dev->rx_slot, received = 0;
1355
1356 DBG2("%d: poll_rx(%d)" NL, dev->def->index, budget);
1357
1358 again:
1359 while (budget > 0) {
1360 int len;
1361 struct sk_buff *skb;
1362 u16 ctrl = dev->rx_desc[slot].ctrl;
1363
1364 if (ctrl & MAL_RX_CTRL_EMPTY)
1365 break;
1366
1367 skb = dev->rx_skb[slot];
1368 barrier();
1369 len = dev->rx_desc[slot].data_len;
1370
1371 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1372 goto sg;
1373
1374 ctrl &= EMAC_BAD_RX_MASK;
1375 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1376 emac_parse_rx_error(dev, ctrl);
1377 ++dev->estats.rx_dropped_error;
1378 emac_recycle_rx_skb(dev, slot, 0);
1379 len = 0;
1380 goto next;
1381 }
1382
1383 if (len && len < EMAC_RX_COPY_THRESH) {
1384 struct sk_buff *copy_skb =
1385 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1386 if (unlikely(!copy_skb))
1387 goto oom;
1388
1389 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1390 cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1391 len + 2);
1392 emac_recycle_rx_skb(dev, slot, len);
1393 skb = copy_skb;
1394 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1395 goto oom;
1396
1397 skb_put(skb, len);
1398 push_packet:
1399 skb->protocol = eth_type_trans(skb, dev->ndev);
1400 emac_rx_csum(dev, skb, ctrl);
1401
1402 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1403 ++dev->estats.rx_dropped_stack;
1404 next:
1405 ++dev->stats.rx_packets;
1406 skip:
1407 dev->stats.rx_bytes += len;
1408 slot = (slot + 1) % NUM_RX_BUFF;
1409 --budget;
1410 ++received;
1411 continue;
1412 sg:
1413 if (ctrl & MAL_RX_CTRL_FIRST) {
1414 BUG_ON(dev->rx_sg_skb);
1415 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1416 DBG("%d: rx OOM %d" NL, dev->def->index, slot);
1417 ++dev->estats.rx_dropped_oom;
1418 emac_recycle_rx_skb(dev, slot, 0);
1419 } else {
1420 dev->rx_sg_skb = skb;
1421 skb_put(skb, len);
1422 }
1423 } else if (!emac_rx_sg_append(dev, slot) &&
1424 (ctrl & MAL_RX_CTRL_LAST)) {
1425
1426 skb = dev->rx_sg_skb;
1427 dev->rx_sg_skb = NULL;
1428
1429 ctrl &= EMAC_BAD_RX_MASK;
1430 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1431 emac_parse_rx_error(dev, ctrl);
1432 ++dev->estats.rx_dropped_error;
1433 dev_kfree_skb(skb);
1434 len = 0;
1435 } else
1436 goto push_packet;
1437 }
1438 goto skip;
1439 oom:
1440 DBG("%d: rx OOM %d" NL, dev->def->index, slot);
1441 /* Drop the packet and recycle skb */
1442 ++dev->estats.rx_dropped_oom;
1443 emac_recycle_rx_skb(dev, slot, 0);
1444 goto next;
1445 }
1446
1447 if (received) {
1448 DBG2("%d: rx %d BDs" NL, dev->def->index, received);
1449 dev->rx_slot = slot;
1450 }
1451
1452 if (unlikely(budget && dev->commac.rx_stopped)) {
1453 struct ocp_func_emac_data *emacdata = dev->def->additions;
1454
1455 barrier();
1456 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1457 DBG2("%d: rx restart" NL, dev->def->index);
1458 received = 0;
1459 goto again;
1460 }
1461
1462 if (dev->rx_sg_skb) {
1463 DBG2("%d: dropping partial rx packet" NL,
1464 dev->def->index);
1465 ++dev->estats.rx_dropped_error;
1466 dev_kfree_skb(dev->rx_sg_skb);
1467 dev->rx_sg_skb = NULL;
1468 }
1469
1470 dev->commac.rx_stopped = 0;
1471 mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
1472 emac_rx_enable(dev);
1473 dev->rx_slot = 0;
1474 }
1475 return received;
1476}
1477
1478/* BHs disabled */
1479static int emac_peek_rx(void *param)
1480{
1481 struct ocp_enet_private *dev = param;
1482 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1483}
1484
1485/* BHs disabled */
1486static int emac_peek_rx_sg(void *param)
1487{
1488 struct ocp_enet_private *dev = param;
1489 int slot = dev->rx_slot;
1490 while (1) {
1491 u16 ctrl = dev->rx_desc[slot].ctrl;
1492 if (ctrl & MAL_RX_CTRL_EMPTY)
1493 return 0;
1494 else if (ctrl & MAL_RX_CTRL_LAST)
1495 return 1;
1496
1497 slot = (slot + 1) % NUM_RX_BUFF;
1498
1499 /* I'm just being paranoid here :) */
1500 if (unlikely(slot == dev->rx_slot))
1501 return 0;
1502 }
1503}
1504
1505/* Hard IRQ */
1506static void emac_rxde(void *param)
1507{
1508 struct ocp_enet_private *dev = param;
1509 ++dev->estats.rx_stopped;
1510 emac_rx_disable_async(dev);
1511}
1512
1513/* Hard IRQ */
1514static irqreturn_t emac_irq(int irq, void *dev_instance)
1515{
1516 struct ocp_enet_private *dev = dev_instance;
1517 struct emac_regs __iomem *p = dev->emacp;
1518 struct ibm_emac_error_stats *st = &dev->estats;
1519
1520 u32 isr = in_be32(&p->isr);
1521 out_be32(&p->isr, isr);
1522
1523 DBG("%d: isr = %08x" NL, dev->def->index, isr);
1524
1525 if (isr & EMAC_ISR_TXPE)
1526 ++st->tx_parity;
1527 if (isr & EMAC_ISR_RXPE)
1528 ++st->rx_parity;
1529 if (isr & EMAC_ISR_TXUE)
1530 ++st->tx_underrun;
1531 if (isr & EMAC_ISR_RXOE)
1532 ++st->rx_fifo_overrun;
1533 if (isr & EMAC_ISR_OVR)
1534 ++st->rx_overrun;
1535 if (isr & EMAC_ISR_BP)
1536 ++st->rx_bad_packet;
1537 if (isr & EMAC_ISR_RP)
1538 ++st->rx_runt_packet;
1539 if (isr & EMAC_ISR_SE)
1540 ++st->rx_short_event;
1541 if (isr & EMAC_ISR_ALE)
1542 ++st->rx_alignment_error;
1543 if (isr & EMAC_ISR_BFCS)
1544 ++st->rx_bad_fcs;
1545 if (isr & EMAC_ISR_PTLE)
1546 ++st->rx_packet_too_long;
1547 if (isr & EMAC_ISR_ORE)
1548 ++st->rx_out_of_range;
1549 if (isr & EMAC_ISR_IRE)
1550 ++st->rx_in_range;
1551 if (isr & EMAC_ISR_SQE)
1552 ++st->tx_sqe;
1553 if (isr & EMAC_ISR_TE)
1554 ++st->tx_errors;
1555
1556 return IRQ_HANDLED;
1557}
1558
1559static struct net_device_stats *emac_stats(struct net_device *ndev)
1560{
1561 struct ocp_enet_private *dev = ndev->priv;
1562 struct ibm_emac_stats *st = &dev->stats;
1563 struct ibm_emac_error_stats *est = &dev->estats;
1564 struct net_device_stats *nst = &dev->nstats;
1565
1566 DBG2("%d: stats" NL, dev->def->index);
1567
1568 /* Compute "legacy" statistics */
1569 local_irq_disable();
1570 nst->rx_packets = (unsigned long)st->rx_packets;
1571 nst->rx_bytes = (unsigned long)st->rx_bytes;
1572 nst->tx_packets = (unsigned long)st->tx_packets;
1573 nst->tx_bytes = (unsigned long)st->tx_bytes;
1574 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1575 est->rx_dropped_error +
1576 est->rx_dropped_resize +
1577 est->rx_dropped_mtu);
1578 nst->tx_dropped = (unsigned long)est->tx_dropped;
1579
1580 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1581 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1582 est->rx_fifo_overrun +
1583 est->rx_overrun);
1584 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1585 est->rx_alignment_error);
1586 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1587 est->rx_bad_fcs);
1588 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1589 est->rx_bd_short_event +
1590 est->rx_bd_packet_too_long +
1591 est->rx_bd_out_of_range +
1592 est->rx_bd_in_range +
1593 est->rx_runt_packet +
1594 est->rx_short_event +
1595 est->rx_packet_too_long +
1596 est->rx_out_of_range +
1597 est->rx_in_range);
1598
1599 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1600 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1601 est->tx_underrun);
1602 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1603 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1604 est->tx_bd_excessive_collisions +
1605 est->tx_bd_late_collision +
1606 est->tx_bd_multple_collisions);
1607 local_irq_enable();
1608 return nst;
1609}
1610
1611static void emac_remove(struct ocp_device *ocpdev)
1612{
1613 struct ocp_enet_private *dev = ocp_get_drvdata(ocpdev);
1614
1615 DBG("%d: remove" NL, dev->def->index);
1616
1617 ocp_set_drvdata(ocpdev, NULL);
1618 unregister_netdev(dev->ndev);
1619
1620 tah_fini(dev->tah_dev);
1621 rgmii_fini(dev->rgmii_dev, dev->rgmii_input);
1622 zmii_fini(dev->zmii_dev, dev->zmii_input);
1623
1624 emac_dbg_register(dev->def->index, NULL);
1625
1626 mal_unregister_commac(dev->mal, &dev->commac);
1627 iounmap(dev->emacp);
1628 kfree(dev->ndev);
1629}
1630
1631static struct mal_commac_ops emac_commac_ops = {
1632 .poll_tx = &emac_poll_tx,
1633 .poll_rx = &emac_poll_rx,
1634 .peek_rx = &emac_peek_rx,
1635 .rxde = &emac_rxde,
1636};
1637
1638static struct mal_commac_ops emac_commac_sg_ops = {
1639 .poll_tx = &emac_poll_tx,
1640 .poll_rx = &emac_poll_rx,
1641 .peek_rx = &emac_peek_rx_sg,
1642 .rxde = &emac_rxde,
1643};
1644
1645/* Ethtool support */
1646static int emac_ethtool_get_settings(struct net_device *ndev,
1647 struct ethtool_cmd *cmd)
1648{
1649 struct ocp_enet_private *dev = ndev->priv;
1650
1651 cmd->supported = dev->phy.features;
1652 cmd->port = PORT_MII;
1653 cmd->phy_address = dev->phy.address;
1654 cmd->transceiver =
1655 dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1656
1657 local_bh_disable();
1658 cmd->advertising = dev->phy.advertising;
1659 cmd->autoneg = dev->phy.autoneg;
1660 cmd->speed = dev->phy.speed;
1661 cmd->duplex = dev->phy.duplex;
1662 local_bh_enable();
1663
1664 return 0;
1665}
1666
1667static int emac_ethtool_set_settings(struct net_device *ndev,
1668 struct ethtool_cmd *cmd)
1669{
1670 struct ocp_enet_private *dev = ndev->priv;
1671 u32 f = dev->phy.features;
1672
1673 DBG("%d: set_settings(%d, %d, %d, 0x%08x)" NL, dev->def->index,
1674 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1675
1676 /* Basic sanity checks */
1677 if (dev->phy.address < 0)
1678 return -EOPNOTSUPP;
1679 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1680 return -EINVAL;
1681 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1682 return -EINVAL;
1683 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1684 return -EINVAL;
1685
1686 if (cmd->autoneg == AUTONEG_DISABLE) {
1687 switch (cmd->speed) {
1688 case SPEED_10:
1689 if (cmd->duplex == DUPLEX_HALF
1690 && !(f & SUPPORTED_10baseT_Half))
1691 return -EINVAL;
1692 if (cmd->duplex == DUPLEX_FULL
1693 && !(f & SUPPORTED_10baseT_Full))
1694 return -EINVAL;
1695 break;
1696 case SPEED_100:
1697 if (cmd->duplex == DUPLEX_HALF
1698 && !(f & SUPPORTED_100baseT_Half))
1699 return -EINVAL;
1700 if (cmd->duplex == DUPLEX_FULL
1701 && !(f & SUPPORTED_100baseT_Full))
1702 return -EINVAL;
1703 break;
1704 case SPEED_1000:
1705 if (cmd->duplex == DUPLEX_HALF
1706 && !(f & SUPPORTED_1000baseT_Half))
1707 return -EINVAL;
1708 if (cmd->duplex == DUPLEX_FULL
1709 && !(f & SUPPORTED_1000baseT_Full))
1710 return -EINVAL;
1711 break;
1712 default:
1713 return -EINVAL;
1714 }
1715
1716 local_bh_disable();
1717 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
1718 cmd->duplex);
1719
1720 } else {
1721 if (!(f & SUPPORTED_Autoneg))
1722 return -EINVAL;
1723
1724 local_bh_disable();
1725 dev->phy.def->ops->setup_aneg(&dev->phy,
1726 (cmd->advertising & f) |
1727 (dev->phy.advertising &
1728 (ADVERTISED_Pause |
1729 ADVERTISED_Asym_Pause)));
1730 }
1731 emac_force_link_update(dev);
1732 local_bh_enable();
1733
1734 return 0;
1735}
1736
1737static void emac_ethtool_get_ringparam(struct net_device *ndev,
1738 struct ethtool_ringparam *rp)
1739{
1740 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
1741 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
1742}
1743
1744static void emac_ethtool_get_pauseparam(struct net_device *ndev,
1745 struct ethtool_pauseparam *pp)
1746{
1747 struct ocp_enet_private *dev = ndev->priv;
1748
1749 local_bh_disable();
1750 if ((dev->phy.features & SUPPORTED_Autoneg) &&
1751 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
1752 pp->autoneg = 1;
1753
1754 if (dev->phy.duplex == DUPLEX_FULL) {
1755 if (dev->phy.pause)
1756 pp->rx_pause = pp->tx_pause = 1;
1757 else if (dev->phy.asym_pause)
1758 pp->tx_pause = 1;
1759 }
1760 local_bh_enable();
1761}
1762
1763static u32 emac_ethtool_get_rx_csum(struct net_device *ndev)
1764{
1765 struct ocp_enet_private *dev = ndev->priv;
1766 return dev->tah_dev != 0;
1767}
1768
1769static int emac_get_regs_len(struct ocp_enet_private *dev)
1770{
1771 return sizeof(struct emac_ethtool_regs_subhdr) + EMAC_ETHTOOL_REGS_SIZE;
1772}
1773
1774static int emac_ethtool_get_regs_len(struct net_device *ndev)
1775{
1776 struct ocp_enet_private *dev = ndev->priv;
1777 return sizeof(struct emac_ethtool_regs_hdr) +
1778 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal) +
1779 zmii_get_regs_len(dev->zmii_dev) +
1780 rgmii_get_regs_len(dev->rgmii_dev) +
1781 tah_get_regs_len(dev->tah_dev);
1782}
1783
1784static void *emac_dump_regs(struct ocp_enet_private *dev, void *buf)
1785{
1786 struct emac_ethtool_regs_subhdr *hdr = buf;
1787
1788 hdr->version = EMAC_ETHTOOL_REGS_VER;
1789 hdr->index = dev->def->index;
1790 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE);
1791 return ((void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE);
1792}
1793
1794static void emac_ethtool_get_regs(struct net_device *ndev,
1795 struct ethtool_regs *regs, void *buf)
1796{
1797 struct ocp_enet_private *dev = ndev->priv;
1798 struct emac_ethtool_regs_hdr *hdr = buf;
1799
1800 hdr->components = 0;
1801 buf = hdr + 1;
1802
1803 local_irq_disable();
1804 buf = mal_dump_regs(dev->mal, buf);
1805 buf = emac_dump_regs(dev, buf);
1806 if (dev->zmii_dev) {
1807 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
1808 buf = zmii_dump_regs(dev->zmii_dev, buf);
1809 }
1810 if (dev->rgmii_dev) {
1811 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
1812 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
1813 }
1814 if (dev->tah_dev) {
1815 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
1816 buf = tah_dump_regs(dev->tah_dev, buf);
1817 }
1818 local_irq_enable();
1819}
1820
1821static int emac_ethtool_nway_reset(struct net_device *ndev)
1822{
1823 struct ocp_enet_private *dev = ndev->priv;
1824 int res = 0;
1825
1826 DBG("%d: nway_reset" NL, dev->def->index);
1827
1828 if (dev->phy.address < 0)
1829 return -EOPNOTSUPP;
1830
1831 local_bh_disable();
1832 if (!dev->phy.autoneg) {
1833 res = -EINVAL;
1834 goto out;
1835 }
1836
1837 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
1838 emac_force_link_update(dev);
1839
1840 out:
1841 local_bh_enable();
1842 return res;
1843}
1844
1845static int emac_get_sset_count(struct net_device *ndev, int sset)
1846{
1847 switch (sset) {
1848 case ETH_SS_STATS:
1849 return EMAC_ETHTOOL_STATS_COUNT;
1850 default:
1851 return -EOPNOTSUPP;
1852 }
1853}
1854
1855static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
1856 u8 * buf)
1857{
1858 if (stringset == ETH_SS_STATS)
1859 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
1860}
1861
1862static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
1863 struct ethtool_stats *estats,
1864 u64 * tmp_stats)
1865{
1866 struct ocp_enet_private *dev = ndev->priv;
1867 local_irq_disable();
1868 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
1869 tmp_stats += sizeof(dev->stats) / sizeof(u64);
1870 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
1871 local_irq_enable();
1872}
1873
1874static void emac_ethtool_get_drvinfo(struct net_device *ndev,
1875 struct ethtool_drvinfo *info)
1876{
1877 struct ocp_enet_private *dev = ndev->priv;
1878
1879 strcpy(info->driver, "ibm_emac");
1880 strcpy(info->version, DRV_VERSION);
1881 info->fw_version[0] = '\0';
1882 sprintf(info->bus_info, "PPC 4xx EMAC %d", dev->def->index);
1883 info->regdump_len = emac_ethtool_get_regs_len(ndev);
1884}
1885
1886static const struct ethtool_ops emac_ethtool_ops = {
1887 .get_settings = emac_ethtool_get_settings,
1888 .set_settings = emac_ethtool_set_settings,
1889 .get_drvinfo = emac_ethtool_get_drvinfo,
1890
1891 .get_regs_len = emac_ethtool_get_regs_len,
1892 .get_regs = emac_ethtool_get_regs,
1893
1894 .nway_reset = emac_ethtool_nway_reset,
1895
1896 .get_ringparam = emac_ethtool_get_ringparam,
1897 .get_pauseparam = emac_ethtool_get_pauseparam,
1898
1899 .get_rx_csum = emac_ethtool_get_rx_csum,
1900
1901 .get_strings = emac_ethtool_get_strings,
1902 .get_sset_count = emac_get_sset_count,
1903 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
1904
1905 .get_link = ethtool_op_get_link,
1906};
1907
1908static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1909{
1910 struct ocp_enet_private *dev = ndev->priv;
1911 uint16_t *data = (uint16_t *) & rq->ifr_ifru;
1912
1913 DBG("%d: ioctl %08x" NL, dev->def->index, cmd);
1914
1915 if (dev->phy.address < 0)
1916 return -EOPNOTSUPP;
1917
1918 switch (cmd) {
1919 case SIOCGMIIPHY:
1920 case SIOCDEVPRIVATE:
1921 data[0] = dev->phy.address;
1922 /* Fall through */
1923 case SIOCGMIIREG:
1924 case SIOCDEVPRIVATE + 1:
1925 data[3] = emac_mdio_read(ndev, dev->phy.address, data[1]);
1926 return 0;
1927
1928 case SIOCSMIIREG:
1929 case SIOCDEVPRIVATE + 2:
1930 if (!capable(CAP_NET_ADMIN))
1931 return -EPERM;
1932 emac_mdio_write(ndev, dev->phy.address, data[1], data[2]);
1933 return 0;
1934 default:
1935 return -EOPNOTSUPP;
1936 }
1937}
1938
1939static int __init emac_probe(struct ocp_device *ocpdev)
1940{
1941 struct ocp_func_emac_data *emacdata = ocpdev->def->additions;
1942 struct net_device *ndev;
1943 struct ocp_device *maldev;
1944 struct ocp_enet_private *dev;
1945 int err, i;
1946 DECLARE_MAC_BUF(mac);
1947
1948 DBG("%d: probe" NL, ocpdev->def->index);
1949
1950 if (!emacdata) {
1951 printk(KERN_ERR "emac%d: Missing additional data!\n",
1952 ocpdev->def->index);
1953 return -ENODEV;
1954 }
1955
1956 /* Allocate our net_device structure */
1957 ndev = alloc_etherdev(sizeof(struct ocp_enet_private));
1958 if (!ndev) {
1959 printk(KERN_ERR "emac%d: could not allocate ethernet device!\n",
1960 ocpdev->def->index);
1961 return -ENOMEM;
1962 }
1963 dev = ndev->priv;
1964 dev->ndev = ndev;
1965 dev->ldev = &ocpdev->dev;
1966 dev->def = ocpdev->def;
1967
1968 /* Find MAL device we are connected to */
1969 maldev =
1970 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_MAL, emacdata->mal_idx);
1971 if (!maldev) {
1972 printk(KERN_ERR "emac%d: unknown mal%d device!\n",
1973 dev->def->index, emacdata->mal_idx);
1974 err = -ENODEV;
1975 goto out;
1976 }
1977 dev->mal = ocp_get_drvdata(maldev);
1978 if (!dev->mal) {
1979 printk(KERN_ERR "emac%d: mal%d hasn't been initialized yet!\n",
1980 dev->def->index, emacdata->mal_idx);
1981 err = -ENODEV;
1982 goto out;
1983 }
1984
1985 /* Register with MAL */
1986 dev->commac.ops = &emac_commac_ops;
1987 dev->commac.dev = dev;
1988 dev->commac.tx_chan_mask = MAL_CHAN_MASK(emacdata->mal_tx_chan);
1989 dev->commac.rx_chan_mask = MAL_CHAN_MASK(emacdata->mal_rx_chan);
1990 err = mal_register_commac(dev->mal, &dev->commac);
1991 if (err) {
1992 printk(KERN_ERR "emac%d: failed to register with mal%d!\n",
1993 dev->def->index, emacdata->mal_idx);
1994 goto out;
1995 }
1996 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
1997 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
1998
1999 /* Get pointers to BD rings */
2000 dev->tx_desc =
2001 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal,
2002 emacdata->mal_tx_chan);
2003 dev->rx_desc =
2004 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal,
2005 emacdata->mal_rx_chan);
2006
2007 DBG("%d: tx_desc %p" NL, ocpdev->def->index, dev->tx_desc);
2008 DBG("%d: rx_desc %p" NL, ocpdev->def->index, dev->rx_desc);
2009
2010 /* Clean rings */
2011 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2012 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
2013
2014 /* If we depend on another EMAC for MDIO, check whether it was probed already */
2015 if (emacdata->mdio_idx >= 0 && emacdata->mdio_idx != ocpdev->def->index) {
2016 struct ocp_device *mdiodev =
2017 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC,
2018 emacdata->mdio_idx);
2019 if (!mdiodev) {
2020 printk(KERN_ERR "emac%d: unknown emac%d device!\n",
2021 dev->def->index, emacdata->mdio_idx);
2022 err = -ENODEV;
2023 goto out2;
2024 }
2025 dev->mdio_dev = ocp_get_drvdata(mdiodev);
2026 if (!dev->mdio_dev) {
2027 printk(KERN_ERR
2028 "emac%d: emac%d hasn't been initialized yet!\n",
2029 dev->def->index, emacdata->mdio_idx);
2030 err = -ENODEV;
2031 goto out2;
2032 }
2033 }
2034
2035 /* Attach to ZMII, if needed */
2036 if ((err = zmii_attach(dev)) != 0)
2037 goto out2;
2038
2039 /* Attach to RGMII, if needed */
2040 if ((err = rgmii_attach(dev)) != 0)
2041 goto out3;
2042
2043 /* Attach to TAH, if needed */
2044 if ((err = tah_attach(dev)) != 0)
2045 goto out4;
2046
2047 /* Map EMAC regs */
2048 dev->emacp = ioremap(dev->def->paddr, sizeof(struct emac_regs));
2049 if (!dev->emacp) {
2050 printk(KERN_ERR "emac%d: could not ioremap device registers!\n",
2051 dev->def->index);
2052 err = -ENOMEM;
2053 goto out5;
2054 }
2055
2056 /* Fill in MAC address */
2057 for (i = 0; i < 6; ++i)
2058 ndev->dev_addr[i] = emacdata->mac_addr[i];
2059
2060 /* Set some link defaults before we can find out real parameters */
2061 dev->phy.speed = SPEED_100;
2062 dev->phy.duplex = DUPLEX_FULL;
2063 dev->phy.autoneg = AUTONEG_DISABLE;
2064 dev->phy.pause = dev->phy.asym_pause = 0;
2065 dev->stop_timeout = STOP_TIMEOUT_100;
2066 init_timer(&dev->link_timer);
2067 dev->link_timer.function = emac_link_timer;
2068 dev->link_timer.data = (unsigned long)dev;
2069
2070 /* Find PHY if any */
2071 dev->phy.dev = ndev;
2072 dev->phy.mode = emacdata->phy_mode;
2073 if (emacdata->phy_map != 0xffffffff) {
2074 u32 phy_map = emacdata->phy_map | busy_phy_map;
2075 u32 adv;
2076
2077 DBG("%d: PHY maps %08x %08x" NL, dev->def->index,
2078 emacdata->phy_map, busy_phy_map);
2079
2080 EMAC_RX_CLK_TX(dev->def->index);
2081
2082 dev->phy.mdio_read = emac_mdio_read;
2083 dev->phy.mdio_write = emac_mdio_write;
2084
2085 /* Configure EMAC with defaults so we can at least use MDIO
2086 * This is needed mostly for 440GX
2087 */
2088 if (emac_phy_gpcs(dev->phy.mode)) {
2089 /* XXX
2090 * Make GPCS PHY address equal to EMAC index.
2091 * We probably should take into account busy_phy_map
2092 * and/or phy_map here.
2093 */
2094 dev->phy.address = dev->def->index;
2095 }
2096
2097 emac_configure(dev);
2098
2099 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2100 if (!(phy_map & 1)) {
2101 int r;
2102 busy_phy_map |= 1 << i;
2103
2104 /* Quick check if there is a PHY at the address */
2105 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2106 if (r == 0xffff || r < 0)
2107 continue;
2108 if (!mii_phy_probe(&dev->phy, i))
2109 break;
2110 }
2111 if (i == 0x20) {
2112 printk(KERN_WARNING "emac%d: can't find PHY!\n",
2113 dev->def->index);
2114 goto out6;
2115 }
2116
2117 /* Init PHY */
2118 if (dev->phy.def->ops->init)
2119 dev->phy.def->ops->init(&dev->phy);
2120
2121 /* Disable any PHY features not supported by the platform */
2122 dev->phy.def->features &= ~emacdata->phy_feat_exc;
2123
2124 /* Setup initial link parameters */
2125 if (dev->phy.features & SUPPORTED_Autoneg) {
2126 adv = dev->phy.features;
2127#if !defined(CONFIG_40x)
2128 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2129#endif
2130 /* Restart autonegotiation */
2131 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2132 } else {
2133 u32 f = dev->phy.def->features;
2134 int speed = SPEED_10, fd = DUPLEX_HALF;
2135
2136 /* Select highest supported speed/duplex */
2137 if (f & SUPPORTED_1000baseT_Full) {
2138 speed = SPEED_1000;
2139 fd = DUPLEX_FULL;
2140 } else if (f & SUPPORTED_1000baseT_Half)
2141 speed = SPEED_1000;
2142 else if (f & SUPPORTED_100baseT_Full) {
2143 speed = SPEED_100;
2144 fd = DUPLEX_FULL;
2145 } else if (f & SUPPORTED_100baseT_Half)
2146 speed = SPEED_100;
2147 else if (f & SUPPORTED_10baseT_Full)
2148 fd = DUPLEX_FULL;
2149
2150 /* Force link parameters */
2151 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2152 }
2153 } else {
2154 emac_reset(dev);
2155
2156 /* PHY-less configuration.
2157 * XXX I probably should move these settings to emacdata
2158 */
2159 dev->phy.address = -1;
2160 dev->phy.features = SUPPORTED_100baseT_Full | SUPPORTED_MII;
2161 dev->phy.pause = 1;
2162 }
2163
2164 /* Fill in the driver function table */
2165 ndev->open = &emac_open;
2166 if (dev->tah_dev) {
2167 ndev->hard_start_xmit = &emac_start_xmit_sg;
2168 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2169 } else
2170 ndev->hard_start_xmit = &emac_start_xmit;
2171 ndev->tx_timeout = &emac_full_tx_reset;
2172 ndev->watchdog_timeo = 5 * HZ;
2173 ndev->stop = &emac_close;
2174 ndev->get_stats = &emac_stats;
2175 ndev->set_multicast_list = &emac_set_multicast_list;
2176 ndev->do_ioctl = &emac_ioctl;
2177 if (emac_phy_supports_gige(emacdata->phy_mode)) {
2178 ndev->change_mtu = &emac_change_mtu;
2179 dev->commac.ops = &emac_commac_sg_ops;
2180 }
2181 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2182
2183 netif_carrier_off(ndev);
2184 netif_stop_queue(ndev);
2185
2186 err = register_netdev(ndev);
2187 if (err) {
2188 printk(KERN_ERR "emac%d: failed to register net device (%d)!\n",
2189 dev->def->index, err);
2190 goto out6;
2191 }
2192
2193 ocp_set_drvdata(ocpdev, dev);
2194
2195 printk("%s: emac%d, MAC %s\n",
2196 ndev->name, dev->def->index, print_mac(mac, ndev->dev_addr));
2197
2198 if (dev->phy.address >= 0)
2199 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2200 dev->phy.def->name, dev->phy.address);
2201
2202 emac_dbg_register(dev->def->index, dev);
2203
2204 return 0;
2205 out6:
2206 iounmap(dev->emacp);
2207 out5:
2208 tah_fini(dev->tah_dev);
2209 out4:
2210 rgmii_fini(dev->rgmii_dev, dev->rgmii_input);
2211 out3:
2212 zmii_fini(dev->zmii_dev, dev->zmii_input);
2213 out2:
2214 mal_unregister_commac(dev->mal, &dev->commac);
2215 out:
2216 kfree(ndev);
2217 return err;
2218}
2219
2220static struct ocp_device_id emac_ids[] = {
2221 { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_EMAC },
2222 { .vendor = OCP_VENDOR_INVALID}
2223};
2224
2225static struct ocp_driver emac_driver = {
2226 .name = "emac",
2227 .id_table = emac_ids,
2228 .probe = emac_probe,
2229 .remove = emac_remove,
2230};
2231
2232static int __init emac_init(void)
2233{
2234 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
2235
2236 DBG(": init" NL);
2237
2238 if (mal_init())
2239 return -ENODEV;
2240
2241 EMAC_CLK_INTERNAL;
2242 if (ocp_register_driver(&emac_driver)) {
2243 EMAC_CLK_EXTERNAL;
2244 ocp_unregister_driver(&emac_driver);
2245 mal_exit();
2246 return -ENODEV;
2247 }
2248 EMAC_CLK_EXTERNAL;
2249
2250 emac_init_debug();
2251 return 0;
2252}
2253
2254static void __exit emac_exit(void)
2255{
2256 DBG(": exit" NL);
2257 ocp_unregister_driver(&emac_driver);
2258 mal_exit();
2259 emac_fini_debug();
2260}
2261
2262module_init(emac_init);
2263module_exit(emac_exit);
diff --git a/drivers/net/ibm_emac/ibm_emac_core.h b/drivers/net/ibm_emac/ibm_emac_core.h
deleted file mode 100644
index dabb94afeb98..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_core.h
+++ /dev/null
@@ -1,222 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_core.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Johnnie Peters <jpeters@mvista.com>
12 * Copyright 2000, 2001 MontaVista Softare Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 */
20#ifndef __IBM_EMAC_CORE_H_
21#define __IBM_EMAC_CORE_H_
22
23#include <linux/netdevice.h>
24#include <linux/dma-mapping.h>
25#include <asm/ocp.h>
26
27#include "ibm_emac.h"
28#include "ibm_emac_phy.h"
29#include "ibm_emac_zmii.h"
30#include "ibm_emac_rgmii.h"
31#include "ibm_emac_mal.h"
32#include "ibm_emac_tah.h"
33
34#define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB
35#define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB
36
37/* Simple sanity check */
38#if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
39#error Invalid number of buffer descriptors (greater than 256)
40#endif
41
42// XXX
43#define EMAC_MIN_MTU 46
44#define EMAC_MAX_MTU 9000
45
46/* Maximum L2 header length (VLAN tagged, no FCS) */
47#define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
48
49/* RX BD size for the given MTU */
50static inline int emac_rx_size(int mtu)
51{
52 if (mtu > ETH_DATA_LEN)
53 return MAL_MAX_RX_SIZE;
54 else
55 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
56}
57
58#define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment())
59
60#define EMAC_RX_SKB_HEADROOM \
61 EMAC_DMA_ALIGN(CONFIG_IBM_EMAC_RX_SKB_HEADROOM)
62
63/* Size of RX skb for the given MTU */
64static inline int emac_rx_skb_size(int mtu)
65{
66 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
67 return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM;
68}
69
70/* RX DMA sync size */
71static inline int emac_rx_sync_size(int mtu)
72{
73 return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2);
74}
75
76/* Driver statistcs is split into two parts to make it more cache friendly:
77 * - normal statistics (packet count, etc)
78 * - error statistics
79 *
80 * When statistics is requested by ethtool, these parts are concatenated,
81 * normal one goes first.
82 *
83 * Please, keep these structures in sync with emac_stats_keys.
84 */
85
86/* Normal TX/RX Statistics */
87struct ibm_emac_stats {
88 u64 rx_packets;
89 u64 rx_bytes;
90 u64 tx_packets;
91 u64 tx_bytes;
92 u64 rx_packets_csum;
93 u64 tx_packets_csum;
94};
95
96/* Error statistics */
97struct ibm_emac_error_stats {
98 u64 tx_undo;
99
100 /* Software RX Errors */
101 u64 rx_dropped_stack;
102 u64 rx_dropped_oom;
103 u64 rx_dropped_error;
104 u64 rx_dropped_resize;
105 u64 rx_dropped_mtu;
106 u64 rx_stopped;
107 /* BD reported RX errors */
108 u64 rx_bd_errors;
109 u64 rx_bd_overrun;
110 u64 rx_bd_bad_packet;
111 u64 rx_bd_runt_packet;
112 u64 rx_bd_short_event;
113 u64 rx_bd_alignment_error;
114 u64 rx_bd_bad_fcs;
115 u64 rx_bd_packet_too_long;
116 u64 rx_bd_out_of_range;
117 u64 rx_bd_in_range;
118 /* EMAC IRQ reported RX errors */
119 u64 rx_parity;
120 u64 rx_fifo_overrun;
121 u64 rx_overrun;
122 u64 rx_bad_packet;
123 u64 rx_runt_packet;
124 u64 rx_short_event;
125 u64 rx_alignment_error;
126 u64 rx_bad_fcs;
127 u64 rx_packet_too_long;
128 u64 rx_out_of_range;
129 u64 rx_in_range;
130
131 /* Software TX Errors */
132 u64 tx_dropped;
133 /* BD reported TX errors */
134 u64 tx_bd_errors;
135 u64 tx_bd_bad_fcs;
136 u64 tx_bd_carrier_loss;
137 u64 tx_bd_excessive_deferral;
138 u64 tx_bd_excessive_collisions;
139 u64 tx_bd_late_collision;
140 u64 tx_bd_multple_collisions;
141 u64 tx_bd_single_collision;
142 u64 tx_bd_underrun;
143 u64 tx_bd_sqe;
144 /* EMAC IRQ reported TX errors */
145 u64 tx_parity;
146 u64 tx_underrun;
147 u64 tx_sqe;
148 u64 tx_errors;
149};
150
151#define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct ibm_emac_stats) + \
152 sizeof(struct ibm_emac_error_stats)) \
153 / sizeof(u64))
154
155struct ocp_enet_private {
156 struct net_device *ndev; /* 0 */
157 struct emac_regs __iomem *emacp;
158
159 struct mal_descriptor *tx_desc;
160 int tx_cnt;
161 int tx_slot;
162 int ack_slot;
163
164 struct mal_descriptor *rx_desc;
165 int rx_slot;
166 struct sk_buff *rx_sg_skb; /* 1 */
167 int rx_skb_size;
168 int rx_sync_size;
169
170 struct ibm_emac_stats stats;
171 struct ocp_device *tah_dev;
172
173 struct ibm_ocp_mal *mal;
174 struct mal_commac commac;
175
176 struct sk_buff *tx_skb[NUM_TX_BUFF];
177 struct sk_buff *rx_skb[NUM_RX_BUFF];
178
179 struct ocp_device *zmii_dev;
180 int zmii_input;
181 struct ocp_enet_private *mdio_dev;
182 struct ocp_device *rgmii_dev;
183 int rgmii_input;
184
185 struct ocp_def *def;
186
187 struct mii_phy phy;
188 struct timer_list link_timer;
189 int reset_failed;
190
191 int stop_timeout; /* in us */
192
193 struct ibm_emac_error_stats estats;
194 struct net_device_stats nstats;
195
196 struct device* ldev;
197};
198
199/* Ethtool get_regs complex data.
200 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
201 * when available.
202 *
203 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
204 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
205 * Each register component is preceded with emac_ethtool_regs_subhdr.
206 * Order of the optional headers follows their relative bit posititions
207 * in emac_ethtool_regs_hdr.components
208 */
209#define EMAC_ETHTOOL_REGS_ZMII 0x00000001
210#define EMAC_ETHTOOL_REGS_RGMII 0x00000002
211#define EMAC_ETHTOOL_REGS_TAH 0x00000004
212
213struct emac_ethtool_regs_hdr {
214 u32 components;
215};
216
217struct emac_ethtool_regs_subhdr {
218 u32 version;
219 u32 index;
220};
221
222#endif /* __IBM_EMAC_CORE_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_debug.c b/drivers/net/ibm_emac/ibm_emac_debug.c
deleted file mode 100644
index 1f70906cfb98..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_debug.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_debug.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/netdevice.h>
19#include <linux/sysrq.h>
20#include <asm/io.h>
21
22#include "ibm_emac_core.h"
23
24static void emac_desc_dump(int idx, struct ocp_enet_private *p)
25{
26 int i;
27 printk("** EMAC%d TX BDs **\n"
28 " tx_cnt = %d tx_slot = %d ack_slot = %d\n",
29 idx, p->tx_cnt, p->tx_slot, p->ack_slot);
30 for (i = 0; i < NUM_TX_BUFF / 2; ++i)
31 printk
32 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
33 i, p->tx_desc[i].data_ptr, p->tx_skb[i] ? 'V' : ' ',
34 p->tx_desc[i].ctrl, p->tx_desc[i].data_len,
35 NUM_TX_BUFF / 2 + i,
36 p->tx_desc[NUM_TX_BUFF / 2 + i].data_ptr,
37 p->tx_skb[NUM_TX_BUFF / 2 + i] ? 'V' : ' ',
38 p->tx_desc[NUM_TX_BUFF / 2 + i].ctrl,
39 p->tx_desc[NUM_TX_BUFF / 2 + i].data_len);
40
41 printk("** EMAC%d RX BDs **\n"
42 " rx_slot = %d rx_stopped = %d rx_skb_size = %d rx_sync_size = %d\n"
43 " rx_sg_skb = 0x%p\n",
44 idx, p->rx_slot, p->commac.rx_stopped, p->rx_skb_size,
45 p->rx_sync_size, p->rx_sg_skb);
46 for (i = 0; i < NUM_RX_BUFF / 2; ++i)
47 printk
48 ("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
49 i, p->rx_desc[i].data_ptr, p->rx_skb[i] ? 'V' : ' ',
50 p->rx_desc[i].ctrl, p->rx_desc[i].data_len,
51 NUM_RX_BUFF / 2 + i,
52 p->rx_desc[NUM_RX_BUFF / 2 + i].data_ptr,
53 p->rx_skb[NUM_RX_BUFF / 2 + i] ? 'V' : ' ',
54 p->rx_desc[NUM_RX_BUFF / 2 + i].ctrl,
55 p->rx_desc[NUM_RX_BUFF / 2 + i].data_len);
56}
57
58static void emac_mac_dump(int idx, struct ocp_enet_private *dev)
59{
60 struct emac_regs __iomem *p = dev->emacp;
61
62 printk("** EMAC%d registers **\n"
63 "MR0 = 0x%08x MR1 = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x\n"
64 "RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x\n"
65 "IAR = %04x%08x VTPID = 0x%04x VTCI = 0x%04x\n"
66 "IAHT: 0x%04x 0x%04x 0x%04x 0x%04x "
67 "GAHT: 0x%04x 0x%04x 0x%04x 0x%04x\n"
68 "LSA = %04x%08x IPGVR = 0x%04x\n"
69 "STACR = 0x%08x TRTR = 0x%08x RWMR = 0x%08x\n"
70 "OCTX = 0x%08x OCRX = 0x%08x IPCR = 0x%08x\n",
71 idx, in_be32(&p->mr0), in_be32(&p->mr1),
72 in_be32(&p->tmr0), in_be32(&p->tmr1),
73 in_be32(&p->rmr), in_be32(&p->isr), in_be32(&p->iser),
74 in_be32(&p->iahr), in_be32(&p->ialr), in_be32(&p->vtpid),
75 in_be32(&p->vtci),
76 in_be32(&p->iaht1), in_be32(&p->iaht2), in_be32(&p->iaht3),
77 in_be32(&p->iaht4),
78 in_be32(&p->gaht1), in_be32(&p->gaht2), in_be32(&p->gaht3),
79 in_be32(&p->gaht4),
80 in_be32(&p->lsah), in_be32(&p->lsal), in_be32(&p->ipgvr),
81 in_be32(&p->stacr), in_be32(&p->trtr), in_be32(&p->rwmr),
82 in_be32(&p->octx), in_be32(&p->ocrx), in_be32(&p->ipcr)
83 );
84
85 emac_desc_dump(idx, dev);
86}
87
88static void emac_mal_dump(struct ibm_ocp_mal *mal)
89{
90 struct ocp_func_mal_data *maldata = mal->def->additions;
91 int i;
92
93 printk("** MAL%d Registers **\n"
94 "CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n"
95 "TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n"
96 "RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n",
97 mal->def->index,
98 get_mal_dcrn(mal, MAL_CFG), get_mal_dcrn(mal, MAL_ESR),
99 get_mal_dcrn(mal, MAL_IER),
100 get_mal_dcrn(mal, MAL_TXCASR), get_mal_dcrn(mal, MAL_TXCARR),
101 get_mal_dcrn(mal, MAL_TXEOBISR), get_mal_dcrn(mal, MAL_TXDEIR),
102 get_mal_dcrn(mal, MAL_RXCASR), get_mal_dcrn(mal, MAL_RXCARR),
103 get_mal_dcrn(mal, MAL_RXEOBISR), get_mal_dcrn(mal, MAL_RXDEIR)
104 );
105
106 printk("TX|");
107 for (i = 0; i < maldata->num_tx_chans; ++i) {
108 if (i && !(i % 4))
109 printk("\n ");
110 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_TXCTPR(i)));
111 }
112 printk("\nRX|");
113 for (i = 0; i < maldata->num_rx_chans; ++i) {
114 if (i && !(i % 4))
115 printk("\n ");
116 printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_RXCTPR(i)));
117 }
118 printk("\n ");
119 for (i = 0; i < maldata->num_rx_chans; ++i) {
120 u32 r = get_mal_dcrn(mal, MAL_RCBS(i));
121 if (i && !(i % 3))
122 printk("\n ");
123 printk("RCBS%d = 0x%08x (%d) ", i, r, r * 16);
124 }
125 printk("\n");
126}
127
128static struct ocp_enet_private *__emacs[4];
129static struct ibm_ocp_mal *__mals[1];
130
131void emac_dbg_register(int idx, struct ocp_enet_private *dev)
132{
133 unsigned long flags;
134
135 if (idx >= ARRAY_SIZE(__emacs)) {
136 printk(KERN_WARNING
137 "invalid index %d when registering EMAC for debugging\n",
138 idx);
139 return;
140 }
141
142 local_irq_save(flags);
143 __emacs[idx] = dev;
144 local_irq_restore(flags);
145}
146
147void mal_dbg_register(int idx, struct ibm_ocp_mal *mal)
148{
149 unsigned long flags;
150
151 if (idx >= ARRAY_SIZE(__mals)) {
152 printk(KERN_WARNING
153 "invalid index %d when registering MAL for debugging\n",
154 idx);
155 return;
156 }
157
158 local_irq_save(flags);
159 __mals[idx] = mal;
160 local_irq_restore(flags);
161}
162
163void emac_dbg_dump_all(void)
164{
165 unsigned int i;
166 unsigned long flags;
167
168 local_irq_save(flags);
169
170 for (i = 0; i < ARRAY_SIZE(__mals); ++i)
171 if (__mals[i])
172 emac_mal_dump(__mals[i]);
173
174 for (i = 0; i < ARRAY_SIZE(__emacs); ++i)
175 if (__emacs[i])
176 emac_mac_dump(i, __emacs[i]);
177
178 local_irq_restore(flags);
179}
180
181#if defined(CONFIG_MAGIC_SYSRQ)
182static void emac_sysrq_handler(int key, struct tty_struct *tty)
183{
184 emac_dbg_dump_all();
185}
186
187static struct sysrq_key_op emac_sysrq_op = {
188 .handler = emac_sysrq_handler,
189 .help_msg = "emaC",
190 .action_msg = "Show EMAC(s) status",
191};
192
193int __init emac_init_debug(void)
194{
195 return register_sysrq_key('c', &emac_sysrq_op);
196}
197
198void __exit emac_fini_debug(void)
199{
200 unregister_sysrq_key('c', &emac_sysrq_op);
201}
202
203#else
204int __init emac_init_debug(void)
205{
206 return 0;
207}
208void __exit emac_fini_debug(void)
209{
210}
211#endif /* CONFIG_MAGIC_SYSRQ */
diff --git a/drivers/net/ibm_emac/ibm_emac_debug.h b/drivers/net/ibm_emac/ibm_emac_debug.h
deleted file mode 100644
index 6c7dccc84bf5..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_debug.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_debug.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#ifndef __IBM_EMAC_DEBUG_H_
16#define __IBM_EMAC_DEBUG_H_
17
18#include <linux/init.h>
19#include "ibm_emac_core.h"
20#include "ibm_emac_mal.h"
21
22#if defined(CONFIG_IBM_EMAC_DEBUG)
23void emac_dbg_register(int idx, struct ocp_enet_private *dev);
24void mal_dbg_register(int idx, struct ibm_ocp_mal *mal);
25int emac_init_debug(void) __init;
26void emac_fini_debug(void) __exit;
27void emac_dbg_dump_all(void);
28# define DBG_LEVEL 1
29#else
30# define emac_dbg_register(x,y) ((void)0)
31# define mal_dbg_register(x,y) ((void)0)
32# define emac_init_debug() ((void)0)
33# define emac_fini_debug() ((void)0)
34# define emac_dbg_dump_all() ((void)0)
35# define DBG_LEVEL 0
36#endif
37
38#if DBG_LEVEL > 0
39# define DBG(f,x...) printk("emac" f, ##x)
40# define MAL_DBG(f,x...) printk("mal" f, ##x)
41# define ZMII_DBG(f,x...) printk("zmii" f, ##x)
42# define RGMII_DBG(f,x...) printk("rgmii" f, ##x)
43# define NL "\n"
44#else
45# define DBG(f,x...) ((void)0)
46# define MAL_DBG(f,x...) ((void)0)
47# define ZMII_DBG(f,x...) ((void)0)
48# define RGMII_DBG(f,x...) ((void)0)
49#endif
50#if DBG_LEVEL > 1
51# define DBG2(f,x...) DBG(f, ##x)
52# define MAL_DBG2(f,x...) MAL_DBG(f, ##x)
53# define ZMII_DBG2(f,x...) ZMII_DBG(f, ##x)
54# define RGMII_DBG2(f,x...) RGMII_DBG(f, ##x)
55#else
56# define DBG2(f,x...) ((void)0)
57# define MAL_DBG2(f,x...) ((void)0)
58# define ZMII_DBG2(f,x...) ((void)0)
59# define RGMII_DBG2(f,x...) ((void)0)
60#endif
61
62#endif /* __IBM_EMAC_DEBUG_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.c b/drivers/net/ibm_emac/ibm_emac_mal.c
deleted file mode 100644
index dcd8826fc749..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_mal.c
+++ /dev/null
@@ -1,570 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
11 * David Gibson <hermes@gibson.dropbear.id.au>,
12 *
13 * Armin Kuster <akuster@mvista.com>
14 * Copyright 2002 MontaVista Softare Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 */
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/netdevice.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/dma-mapping.h>
29
30#include <asm/ocp.h>
31
32#include "ibm_emac_core.h"
33#include "ibm_emac_mal.h"
34#include "ibm_emac_debug.h"
35
36int __init mal_register_commac(struct ibm_ocp_mal *mal,
37 struct mal_commac *commac)
38{
39 unsigned long flags;
40 local_irq_save(flags);
41
42 MAL_DBG("%d: reg(%08x, %08x)" NL, mal->def->index,
43 commac->tx_chan_mask, commac->rx_chan_mask);
44
45 /* Don't let multiple commacs claim the same channel(s) */
46 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
47 (mal->rx_chan_mask & commac->rx_chan_mask)) {
48 local_irq_restore(flags);
49 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
50 mal->def->index);
51 return -EBUSY;
52 }
53
54 mal->tx_chan_mask |= commac->tx_chan_mask;
55 mal->rx_chan_mask |= commac->rx_chan_mask;
56 list_add(&commac->list, &mal->list);
57
58 local_irq_restore(flags);
59 return 0;
60}
61
62void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac)
63{
64 unsigned long flags;
65 local_irq_save(flags);
66
67 MAL_DBG("%d: unreg(%08x, %08x)" NL, mal->def->index,
68 commac->tx_chan_mask, commac->rx_chan_mask);
69
70 mal->tx_chan_mask &= ~commac->tx_chan_mask;
71 mal->rx_chan_mask &= ~commac->rx_chan_mask;
72 list_del_init(&commac->list);
73
74 local_irq_restore(flags);
75}
76
77int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size)
78{
79 struct ocp_func_mal_data *maldata = mal->def->additions;
80 BUG_ON(channel < 0 || channel >= maldata->num_rx_chans ||
81 size > MAL_MAX_RX_SIZE);
82
83 MAL_DBG("%d: set_rbcs(%d, %lu)" NL, mal->def->index, channel, size);
84
85 if (size & 0xf) {
86 printk(KERN_WARNING
87 "mal%d: incorrect RX size %lu for the channel %d\n",
88 mal->def->index, size, channel);
89 return -EINVAL;
90 }
91
92 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
93 return 0;
94}
95
96int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel)
97{
98 struct ocp_func_mal_data *maldata = mal->def->additions;
99 BUG_ON(channel < 0 || channel >= maldata->num_tx_chans);
100 return channel * NUM_TX_BUFF;
101}
102
103int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel)
104{
105 struct ocp_func_mal_data *maldata = mal->def->additions;
106 BUG_ON(channel < 0 || channel >= maldata->num_rx_chans);
107 return maldata->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
108}
109
110void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel)
111{
112 local_bh_disable();
113 MAL_DBG("%d: enable_tx(%d)" NL, mal->def->index, channel);
114 set_mal_dcrn(mal, MAL_TXCASR,
115 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
116 local_bh_enable();
117}
118
119void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel)
120{
121 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
122 MAL_DBG("%d: disable_tx(%d)" NL, mal->def->index, channel);
123}
124
125void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel)
126{
127 local_bh_disable();
128 MAL_DBG("%d: enable_rx(%d)" NL, mal->def->index, channel);
129 set_mal_dcrn(mal, MAL_RXCASR,
130 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
131 local_bh_enable();
132}
133
134void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel)
135{
136 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
137 MAL_DBG("%d: disable_rx(%d)" NL, mal->def->index, channel);
138}
139
140void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac)
141{
142 local_bh_disable();
143 MAL_DBG("%d: poll_add(%p)" NL, mal->def->index, commac);
144 list_add_tail(&commac->poll_list, &mal->poll_list);
145 local_bh_enable();
146}
147
148void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac)
149{
150 local_bh_disable();
151 MAL_DBG("%d: poll_del(%p)" NL, mal->def->index, commac);
152 list_del(&commac->poll_list);
153 local_bh_enable();
154}
155
156/* synchronized by mal_poll() */
157static inline void mal_enable_eob_irq(struct ibm_ocp_mal *mal)
158{
159 MAL_DBG2("%d: enable_irq" NL, mal->def->index);
160 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
161}
162
163/* synchronized by __LINK_STATE_RX_SCHED bit in ndev->state */
164static inline void mal_disable_eob_irq(struct ibm_ocp_mal *mal)
165{
166 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
167 MAL_DBG2("%d: disable_irq" NL, mal->def->index);
168}
169
170static irqreturn_t mal_serr(int irq, void *dev_instance)
171{
172 struct ibm_ocp_mal *mal = dev_instance;
173 u32 esr = get_mal_dcrn(mal, MAL_ESR);
174
175 /* Clear the error status register */
176 set_mal_dcrn(mal, MAL_ESR, esr);
177
178 MAL_DBG("%d: SERR %08x" NL, mal->def->index, esr);
179
180 if (esr & MAL_ESR_EVB) {
181 if (esr & MAL_ESR_DE) {
182 /* We ignore Descriptor error,
183 * TXDE or RXDE interrupt will be generated anyway.
184 */
185 return IRQ_HANDLED;
186 }
187
188 if (esr & MAL_ESR_PEIN) {
189 /* PLB error, it's probably buggy hardware or
190 * incorrect physical address in BD (i.e. bug)
191 */
192 if (net_ratelimit())
193 printk(KERN_ERR
194 "mal%d: system error, PLB (ESR = 0x%08x)\n",
195 mal->def->index, esr);
196 return IRQ_HANDLED;
197 }
198
199 /* OPB error, it's probably buggy hardware or incorrect EBC setup */
200 if (net_ratelimit())
201 printk(KERN_ERR
202 "mal%d: system error, OPB (ESR = 0x%08x)\n",
203 mal->def->index, esr);
204 }
205 return IRQ_HANDLED;
206}
207
208static inline void mal_schedule_poll(struct ibm_ocp_mal *mal)
209{
210 if (likely(napi_schedule_prep(&mal->napi))) {
211 MAL_DBG2("%d: schedule_poll" NL, mal->def->index);
212 mal_disable_eob_irq(mal);
213 __napi_schedule(&mal->napi);
214 } else
215 MAL_DBG2("%d: already in poll" NL, mal->def->index);
216}
217
218static irqreturn_t mal_txeob(int irq, void *dev_instance)
219{
220 struct ibm_ocp_mal *mal = dev_instance;
221 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
222 MAL_DBG2("%d: txeob %08x" NL, mal->def->index, r);
223 mal_schedule_poll(mal);
224 set_mal_dcrn(mal, MAL_TXEOBISR, r);
225 return IRQ_HANDLED;
226}
227
228static irqreturn_t mal_rxeob(int irq, void *dev_instance)
229{
230 struct ibm_ocp_mal *mal = dev_instance;
231 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
232 MAL_DBG2("%d: rxeob %08x" NL, mal->def->index, r);
233 mal_schedule_poll(mal);
234 set_mal_dcrn(mal, MAL_RXEOBISR, r);
235 return IRQ_HANDLED;
236}
237
238static irqreturn_t mal_txde(int irq, void *dev_instance)
239{
240 struct ibm_ocp_mal *mal = dev_instance;
241 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
242 set_mal_dcrn(mal, MAL_TXDEIR, deir);
243
244 MAL_DBG("%d: txde %08x" NL, mal->def->index, deir);
245
246 if (net_ratelimit())
247 printk(KERN_ERR
248 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
249 mal->def->index, deir);
250
251 return IRQ_HANDLED;
252}
253
254static irqreturn_t mal_rxde(int irq, void *dev_instance)
255{
256 struct ibm_ocp_mal *mal = dev_instance;
257 struct list_head *l;
258 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
259
260 MAL_DBG("%d: rxde %08x" NL, mal->def->index, deir);
261
262 list_for_each(l, &mal->list) {
263 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
264 if (deir & mc->rx_chan_mask) {
265 mc->rx_stopped = 1;
266 mc->ops->rxde(mc->dev);
267 }
268 }
269
270 mal_schedule_poll(mal);
271 set_mal_dcrn(mal, MAL_RXDEIR, deir);
272
273 return IRQ_HANDLED;
274}
275
276static int mal_poll(struct napi_struct *napi, int budget)
277{
278 struct ibm_ocp_mal *mal = container_of(napi, struct ibm_ocp_mal, napi);
279 struct list_head *l;
280 int received = 0;
281
282 MAL_DBG2("%d: poll(%d) %d ->" NL, mal->def->index, *budget,
283 rx_work_limit);
284 again:
285 /* Process TX skbs */
286 list_for_each(l, &mal->poll_list) {
287 struct mal_commac *mc =
288 list_entry(l, struct mal_commac, poll_list);
289 mc->ops->poll_tx(mc->dev);
290 }
291
292 /* Process RX skbs.
293 * We _might_ need something more smart here to enforce polling fairness.
294 */
295 list_for_each(l, &mal->poll_list) {
296 struct mal_commac *mc =
297 list_entry(l, struct mal_commac, poll_list);
298 int n = mc->ops->poll_rx(mc->dev, budget);
299 if (n) {
300 received += n;
301 budget -= n;
302 if (budget <= 0)
303 goto more_work; // XXX What if this is the last one ?
304 }
305 }
306
307 /* We need to disable IRQs to protect from RXDE IRQ here */
308 local_irq_disable();
309 __napi_complete(napi);
310 mal_enable_eob_irq(mal);
311 local_irq_enable();
312
313 /* Check for "rotting" packet(s) */
314 list_for_each(l, &mal->poll_list) {
315 struct mal_commac *mc =
316 list_entry(l, struct mal_commac, poll_list);
317 if (unlikely(mc->ops->peek_rx(mc->dev) || mc->rx_stopped)) {
318 MAL_DBG2("%d: rotting packet" NL, mal->def->index);
319 if (napi_reschedule(napi))
320 mal_disable_eob_irq(mal);
321 else
322 MAL_DBG2("%d: already in poll list" NL,
323 mal->def->index);
324
325 if (budget > 0)
326 goto again;
327 else
328 goto more_work;
329 }
330 mc->ops->poll_tx(mc->dev);
331 }
332
333 more_work:
334 MAL_DBG2("%d: poll() %d <- %d" NL, mal->def->index, budget, received);
335 return received;
336}
337
338static void mal_reset(struct ibm_ocp_mal *mal)
339{
340 int n = 10;
341 MAL_DBG("%d: reset" NL, mal->def->index);
342
343 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
344
345 /* Wait for reset to complete (1 system clock) */
346 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
347 --n;
348
349 if (unlikely(!n))
350 printk(KERN_ERR "mal%d: reset timeout\n", mal->def->index);
351}
352
353int mal_get_regs_len(struct ibm_ocp_mal *mal)
354{
355 return sizeof(struct emac_ethtool_regs_subhdr) +
356 sizeof(struct ibm_mal_regs);
357}
358
359void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf)
360{
361 struct emac_ethtool_regs_subhdr *hdr = buf;
362 struct ibm_mal_regs *regs = (struct ibm_mal_regs *)(hdr + 1);
363 struct ocp_func_mal_data *maldata = mal->def->additions;
364 int i;
365
366 hdr->version = MAL_VERSION;
367 hdr->index = mal->def->index;
368
369 regs->tx_count = maldata->num_tx_chans;
370 regs->rx_count = maldata->num_rx_chans;
371
372 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
373 regs->esr = get_mal_dcrn(mal, MAL_ESR);
374 regs->ier = get_mal_dcrn(mal, MAL_IER);
375 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
376 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
377 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
378 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
379 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
380 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
381 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
382 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
383
384 for (i = 0; i < regs->tx_count; ++i)
385 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
386
387 for (i = 0; i < regs->rx_count; ++i) {
388 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
389 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
390 }
391 return regs + 1;
392}
393
394static int __init mal_probe(struct ocp_device *ocpdev)
395{
396 struct ibm_ocp_mal *mal;
397 struct ocp_func_mal_data *maldata;
398 int err = 0, i, bd_size;
399
400 MAL_DBG("%d: probe" NL, ocpdev->def->index);
401
402 maldata = ocpdev->def->additions;
403 if (maldata == NULL) {
404 printk(KERN_ERR "mal%d: missing additional data!\n",
405 ocpdev->def->index);
406 return -ENODEV;
407 }
408
409 mal = kzalloc(sizeof(struct ibm_ocp_mal), GFP_KERNEL);
410 if (!mal) {
411 printk(KERN_ERR
412 "mal%d: out of memory allocating MAL structure!\n",
413 ocpdev->def->index);
414 return -ENOMEM;
415 }
416
417 /* XXX This only works for native dcr for now */
418 mal->dcrhost = dcr_map(NULL, maldata->dcr_base, 0);
419
420 mal->def = ocpdev->def;
421
422 INIT_LIST_HEAD(&mal->poll_list);
423 mal->napi.weight = CONFIG_IBM_EMAC_POLL_WEIGHT;
424 mal->napi.poll = mal_poll;
425
426 INIT_LIST_HEAD(&mal->list);
427
428 /* Load power-on reset defaults */
429 mal_reset(mal);
430
431 /* Set the MAL configuration register */
432 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_DEFAULT | MAL_CFG_PLBB |
433 MAL_CFG_OPBBL | MAL_CFG_LEA);
434
435 mal_enable_eob_irq(mal);
436
437 /* Allocate space for BD rings */
438 BUG_ON(maldata->num_tx_chans <= 0 || maldata->num_tx_chans > 32);
439 BUG_ON(maldata->num_rx_chans <= 0 || maldata->num_rx_chans > 32);
440 bd_size = sizeof(struct mal_descriptor) *
441 (NUM_TX_BUFF * maldata->num_tx_chans +
442 NUM_RX_BUFF * maldata->num_rx_chans);
443 mal->bd_virt =
444 dma_alloc_coherent(&ocpdev->dev, bd_size, &mal->bd_dma, GFP_KERNEL);
445
446 if (!mal->bd_virt) {
447 printk(KERN_ERR
448 "mal%d: out of memory allocating RX/TX descriptors!\n",
449 mal->def->index);
450 err = -ENOMEM;
451 goto fail;
452 }
453 memset(mal->bd_virt, 0, bd_size);
454
455 for (i = 0; i < maldata->num_tx_chans; ++i)
456 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
457 sizeof(struct mal_descriptor) *
458 mal_tx_bd_offset(mal, i));
459
460 for (i = 0; i < maldata->num_rx_chans; ++i)
461 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
462 sizeof(struct mal_descriptor) *
463 mal_rx_bd_offset(mal, i));
464
465 err = request_irq(maldata->serr_irq, mal_serr, 0, "MAL SERR", mal);
466 if (err)
467 goto fail2;
468 err = request_irq(maldata->txde_irq, mal_txde, 0, "MAL TX DE", mal);
469 if (err)
470 goto fail3;
471 err = request_irq(maldata->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
472 if (err)
473 goto fail4;
474 err = request_irq(maldata->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
475 if (err)
476 goto fail5;
477 err = request_irq(maldata->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
478 if (err)
479 goto fail6;
480
481 /* Enable all MAL SERR interrupt sources */
482 set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
483
484 /* Advertise this instance to the rest of the world */
485 ocp_set_drvdata(ocpdev, mal);
486
487 mal_dbg_register(mal->def->index, mal);
488
489 printk(KERN_INFO "mal%d: initialized, %d TX channels, %d RX channels\n",
490 mal->def->index, maldata->num_tx_chans, maldata->num_rx_chans);
491 return 0;
492
493 fail6:
494 free_irq(maldata->rxde_irq, mal);
495 fail5:
496 free_irq(maldata->txeob_irq, mal);
497 fail4:
498 free_irq(maldata->txde_irq, mal);
499 fail3:
500 free_irq(maldata->serr_irq, mal);
501 fail2:
502 dma_free_coherent(&ocpdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
503 fail:
504 kfree(mal);
505 return err;
506}
507
508static void __exit mal_remove(struct ocp_device *ocpdev)
509{
510 struct ibm_ocp_mal *mal = ocp_get_drvdata(ocpdev);
511 struct ocp_func_mal_data *maldata = mal->def->additions;
512
513 MAL_DBG("%d: remove" NL, mal->def->index);
514
515 /* Synchronize with scheduled polling */
516 napi_disable(&mal->napi);
517
518 if (!list_empty(&mal->list)) {
519 /* This is *very* bad */
520 printk(KERN_EMERG
521 "mal%d: commac list is not empty on remove!\n",
522 mal->def->index);
523 }
524
525 ocp_set_drvdata(ocpdev, NULL);
526
527 free_irq(maldata->serr_irq, mal);
528 free_irq(maldata->txde_irq, mal);
529 free_irq(maldata->txeob_irq, mal);
530 free_irq(maldata->rxde_irq, mal);
531 free_irq(maldata->rxeob_irq, mal);
532
533 mal_reset(mal);
534
535 mal_dbg_register(mal->def->index, NULL);
536
537 dma_free_coherent(&ocpdev->dev,
538 sizeof(struct mal_descriptor) *
539 (NUM_TX_BUFF * maldata->num_tx_chans +
540 NUM_RX_BUFF * maldata->num_rx_chans), mal->bd_virt,
541 mal->bd_dma);
542
543 kfree(mal);
544}
545
546/* Structure for a device driver */
547static struct ocp_device_id mal_ids[] = {
548 { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_MAL },
549 { .vendor = OCP_VENDOR_INVALID}
550};
551
552static struct ocp_driver mal_driver = {
553 .name = "mal",
554 .id_table = mal_ids,
555
556 .probe = mal_probe,
557 .remove = mal_remove,
558};
559
560int __init mal_init(void)
561{
562 MAL_DBG(": init" NL);
563 return ocp_register_driver(&mal_driver);
564}
565
566void __exit mal_exit(void)
567{
568 MAL_DBG(": exit" NL);
569 ocp_unregister_driver(&mal_driver);
570}
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h
deleted file mode 100644
index b8adbe6d4b01..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_mal.h
+++ /dev/null
@@ -1,267 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_mal.h
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2002 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef __IBM_EMAC_MAL_H_
20#define __IBM_EMAC_MAL_H_
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/netdevice.h>
25
26#include <asm/io.h>
27#include <asm/dcr.h>
28
29/*
30 * These MAL "versions" probably aren't the real versions IBM uses for these
31 * MAL cores, I assigned them just to make #ifdefs in this file nicer and
32 * reflect the fact that 40x and 44x have slightly different MALs. --ebs
33 */
34#if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \
35 defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H)
36#define MAL_VERSION 1
37#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
38 defined(CONFIG_440SPE)
39#define MAL_VERSION 2
40#else
41#error "Unknown SoC, please check chip manual and choose MAL 'version'"
42#endif
43
44/* MALx DCR registers */
45#define MAL_CFG 0x00
46#define MAL_CFG_SR 0x80000000
47#define MAL_CFG_PLBB 0x00004000
48#define MAL_CFG_OPBBL 0x00000080
49#define MAL_CFG_EOPIE 0x00000004
50#define MAL_CFG_LEA 0x00000002
51#define MAL_CFG_SD 0x00000001
52#if MAL_VERSION == 1
53#define MAL_CFG_PLBP_MASK 0x00c00000
54#define MAL_CFG_PLBP_10 0x00800000
55#define MAL_CFG_GA 0x00200000
56#define MAL_CFG_OA 0x00100000
57#define MAL_CFG_PLBLE 0x00080000
58#define MAL_CFG_PLBT_MASK 0x00078000
59#define MAL_CFG_DEFAULT (MAL_CFG_PLBP_10 | MAL_CFG_PLBT_MASK)
60#elif MAL_VERSION == 2
61#define MAL_CFG_RPP_MASK 0x00c00000
62#define MAL_CFG_RPP_10 0x00800000
63#define MAL_CFG_RMBS_MASK 0x00300000
64#define MAL_CFG_WPP_MASK 0x000c0000
65#define MAL_CFG_WPP_10 0x00080000
66#define MAL_CFG_WMBS_MASK 0x00030000
67#define MAL_CFG_PLBLE 0x00008000
68#define MAL_CFG_DEFAULT (MAL_CFG_RMBS_MASK | MAL_CFG_WMBS_MASK | \
69 MAL_CFG_RPP_10 | MAL_CFG_WPP_10)
70#else
71#error "Unknown MAL version"
72#endif
73
74#define MAL_ESR 0x01
75#define MAL_ESR_EVB 0x80000000
76#define MAL_ESR_CIDT 0x40000000
77#define MAL_ESR_CID_MASK 0x3e000000
78#define MAL_ESR_CID_SHIFT 25
79#define MAL_ESR_DE 0x00100000
80#define MAL_ESR_OTE 0x00040000
81#define MAL_ESR_OSE 0x00020000
82#define MAL_ESR_PEIN 0x00010000
83#define MAL_ESR_DEI 0x00000010
84#define MAL_ESR_OTEI 0x00000004
85#define MAL_ESR_OSEI 0x00000002
86#define MAL_ESR_PBEI 0x00000001
87#if MAL_VERSION == 1
88#define MAL_ESR_ONE 0x00080000
89#define MAL_ESR_ONEI 0x00000008
90#elif MAL_VERSION == 2
91#define MAL_ESR_PTE 0x00800000
92#define MAL_ESR_PRE 0x00400000
93#define MAL_ESR_PWE 0x00200000
94#define MAL_ESR_PTEI 0x00000080
95#define MAL_ESR_PREI 0x00000040
96#define MAL_ESR_PWEI 0x00000020
97#else
98#error "Unknown MAL version"
99#endif
100
101#define MAL_IER 0x02
102#define MAL_IER_DE 0x00000010
103#define MAL_IER_OTE 0x00000004
104#define MAL_IER_OE 0x00000002
105#define MAL_IER_PE 0x00000001
106#if MAL_VERSION == 1
107#define MAL_IER_NWE 0x00000008
108#define MAL_IER_SOC_EVENTS MAL_IER_NWE
109#elif MAL_VERSION == 2
110#define MAL_IER_PT 0x00000080
111#define MAL_IER_PRE 0x00000040
112#define MAL_IER_PWE 0x00000020
113#define MAL_IER_SOC_EVENTS (MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE)
114#else
115#error "Unknown MAL version"
116#endif
117#define MAL_IER_EVENTS (MAL_IER_SOC_EVENTS | MAL_IER_OTE | \
118 MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)
119
120#define MAL_TXCASR 0x04
121#define MAL_TXCARR 0x05
122#define MAL_TXEOBISR 0x06
123#define MAL_TXDEIR 0x07
124#define MAL_RXCASR 0x10
125#define MAL_RXCARR 0x11
126#define MAL_RXEOBISR 0x12
127#define MAL_RXDEIR 0x13
128#define MAL_TXCTPR(n) ((n) + 0x20)
129#define MAL_RXCTPR(n) ((n) + 0x40)
130#define MAL_RCBS(n) ((n) + 0x60)
131
132/* In reality MAL can handle TX buffers up to 4095 bytes long,
133 * but this isn't a good round number :) --ebs
134 */
135#define MAL_MAX_TX_SIZE 4080
136#define MAL_MAX_RX_SIZE 4080
137
138static inline int mal_rx_size(int len)
139{
140 len = (len + 0xf) & ~0xf;
141 return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
142}
143
144static inline int mal_tx_chunks(int len)
145{
146 return (len + MAL_MAX_TX_SIZE - 1) / MAL_MAX_TX_SIZE;
147}
148
149#define MAL_CHAN_MASK(n) (0x80000000 >> (n))
150
151/* MAL Buffer Descriptor structure */
152struct mal_descriptor {
153 u16 ctrl; /* MAL / Commac status control bits */
154 u16 data_len; /* Max length is 4K-1 (12 bits) */
155 u32 data_ptr; /* pointer to actual data buffer */
156};
157
158/* the following defines are for the MadMAL status and control registers. */
159/* MADMAL transmit and receive status/control bits */
160#define MAL_RX_CTRL_EMPTY 0x8000
161#define MAL_RX_CTRL_WRAP 0x4000
162#define MAL_RX_CTRL_CM 0x2000
163#define MAL_RX_CTRL_LAST 0x1000
164#define MAL_RX_CTRL_FIRST 0x0800
165#define MAL_RX_CTRL_INTR 0x0400
166#define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
167#define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)
168
169#define MAL_TX_CTRL_READY 0x8000
170#define MAL_TX_CTRL_WRAP 0x4000
171#define MAL_TX_CTRL_CM 0x2000
172#define MAL_TX_CTRL_LAST 0x1000
173#define MAL_TX_CTRL_INTR 0x0400
174
175struct mal_commac_ops {
176 void (*poll_tx) (void *dev);
177 int (*poll_rx) (void *dev, int budget);
178 int (*peek_rx) (void *dev);
179 void (*rxde) (void *dev);
180};
181
182struct mal_commac {
183 struct mal_commac_ops *ops;
184 void *dev;
185 struct list_head poll_list;
186 int rx_stopped;
187
188 u32 tx_chan_mask;
189 u32 rx_chan_mask;
190 struct list_head list;
191};
192
193struct ibm_ocp_mal {
194 dcr_host_t dcrhost;
195
196 struct list_head poll_list;
197 struct napi_struct napi;
198
199 struct list_head list;
200 u32 tx_chan_mask;
201 u32 rx_chan_mask;
202
203 dma_addr_t bd_dma;
204 struct mal_descriptor *bd_virt;
205
206 struct ocp_def *def;
207};
208
209static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg)
210{
211 return dcr_read(mal->dcrhost, reg);
212}
213
214static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val)
215{
216 dcr_write(mal->dcrhost, reg, val);
217}
218
219/* Register MAL devices */
220int mal_init(void) __init;
221void mal_exit(void) __exit;
222
223int mal_register_commac(struct ibm_ocp_mal *mal,
224 struct mal_commac *commac) __init;
225void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac);
226int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size);
227
228/* Returns BD ring offset for a particular channel
229 (in 'struct mal_descriptor' elements)
230*/
231int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel);
232int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel);
233
234void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel);
235void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel);
236void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel);
237void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel);
238
239/* Add/remove EMAC to/from MAL polling list */
240void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac);
241void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac);
242
243/* Ethtool MAL registers */
244struct ibm_mal_regs {
245 u32 tx_count;
246 u32 rx_count;
247
248 u32 cfg;
249 u32 esr;
250 u32 ier;
251 u32 tx_casr;
252 u32 tx_carr;
253 u32 tx_eobisr;
254 u32 tx_deir;
255 u32 rx_casr;
256 u32 rx_carr;
257 u32 rx_eobisr;
258 u32 rx_deir;
259 u32 tx_ctpr[32];
260 u32 rx_ctpr[32];
261 u32 rcbs[32];
262};
263
264int mal_get_regs_len(struct ibm_ocp_mal *mal);
265void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf);
266
267#endif /* __IBM_EMAC_MAL_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.c b/drivers/net/ibm_emac/ibm_emac_phy.c
deleted file mode 100644
index e57862b34cae..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_phy.c
+++ /dev/null
@@ -1,398 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_phy.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
5 * Borrowed from sungem_phy.c, though I only kept the generic MII
6 * driver for now.
7 *
8 * This file should be shared with other drivers or eventually
9 * merged as the "low level" part of miilib
10 *
11 * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
12 * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
13 *
14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/netdevice.h>
19#include <linux/mii.h>
20#include <linux/ethtool.h>
21#include <linux/delay.h>
22
23#include <asm/ocp.h>
24
25#include "ibm_emac_core.h"
26#include "ibm_emac_phy.h"
27
28static inline int phy_read(struct mii_phy *phy, int reg)
29{
30 return phy->mdio_read(phy->dev, phy->address, reg);
31}
32
33static inline void phy_write(struct mii_phy *phy, int reg, int val)
34{
35 phy->mdio_write(phy->dev, phy->address, reg, val);
36}
37
38/*
39 * polls MII_BMCR until BMCR_RESET bit clears or operation times out.
40 *
41 * returns:
42 * >= 0 => success, value in BMCR returned to caller
43 * -EBUSY => failure, RESET bit never cleared
44 * otherwise => failure, lower level PHY read failed
45 */
46static int mii_spin_reset_complete(struct mii_phy *phy)
47{
48 int val;
49 int limit = 10000;
50
51 while (limit--) {
52 val = phy_read(phy, MII_BMCR);
53 if (val >= 0 && !(val & BMCR_RESET))
54 return val; /* success */
55 udelay(10);
56 }
57 if (val & BMCR_RESET)
58 val = -EBUSY;
59
60 if (net_ratelimit())
61 printk(KERN_ERR "emac%d: PHY reset timeout (%d)\n",
62 ((struct ocp_enet_private *)phy->dev->priv)->def->index,
63 val);
64 return val;
65}
66
67int mii_reset_phy(struct mii_phy *phy)
68{
69 int val;
70
71 val = phy_read(phy, MII_BMCR);
72 val &= ~BMCR_ISOLATE;
73 val |= BMCR_RESET;
74 phy_write(phy, MII_BMCR, val);
75
76 udelay(300);
77
78 val = mii_spin_reset_complete(phy);
79 if (val >= 0 && (val & BMCR_ISOLATE))
80 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
81
82 return val < 0;
83}
84
85static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
86{
87 int ctl, adv;
88
89 phy->autoneg = AUTONEG_ENABLE;
90 phy->speed = SPEED_10;
91 phy->duplex = DUPLEX_HALF;
92 phy->pause = phy->asym_pause = 0;
93 phy->advertising = advertise;
94
95 /* Setup standard advertise */
96 adv = phy_read(phy, MII_ADVERTISE);
97 if (adv < 0)
98 return adv;
99 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
100 ADVERTISE_PAUSE_ASYM);
101 if (advertise & ADVERTISED_10baseT_Half)
102 adv |= ADVERTISE_10HALF;
103 if (advertise & ADVERTISED_10baseT_Full)
104 adv |= ADVERTISE_10FULL;
105 if (advertise & ADVERTISED_100baseT_Half)
106 adv |= ADVERTISE_100HALF;
107 if (advertise & ADVERTISED_100baseT_Full)
108 adv |= ADVERTISE_100FULL;
109 if (advertise & ADVERTISED_Pause)
110 adv |= ADVERTISE_PAUSE_CAP;
111 if (advertise & ADVERTISED_Asym_Pause)
112 adv |= ADVERTISE_PAUSE_ASYM;
113 phy_write(phy, MII_ADVERTISE, adv);
114
115 if (phy->features &
116 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
117 adv = phy_read(phy, MII_CTRL1000);
118 if (adv < 0)
119 return adv;
120 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
121 if (advertise & ADVERTISED_1000baseT_Full)
122 adv |= ADVERTISE_1000FULL;
123 if (advertise & ADVERTISED_1000baseT_Half)
124 adv |= ADVERTISE_1000HALF;
125 phy_write(phy, MII_CTRL1000, adv);
126 }
127
128 /* Start/Restart aneg */
129 /* on some PHYs (e.g. National DP83843) a write to MII_ADVERTISE
130 * causes BMCR_RESET to be set on the next read of MII_BMCR, which
131 * if not checked for causes the PHY to be reset below */
132 ctl = mii_spin_reset_complete(phy);
133 if (ctl < 0)
134 return ctl;
135
136 ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
137 phy_write(phy, MII_BMCR, ctl);
138
139 return 0;
140}
141
142static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
143{
144 int ctl;
145
146 phy->autoneg = AUTONEG_DISABLE;
147 phy->speed = speed;
148 phy->duplex = fd;
149 phy->pause = phy->asym_pause = 0;
150
151 /* First reset the PHY */
152 mii_reset_phy(phy);
153
154 ctl = phy_read(phy, MII_BMCR);
155 if (ctl < 0)
156 return ctl;
157 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE | BMCR_SPEED1000);
158
159 /* Select speed & duplex */
160 switch (speed) {
161 case SPEED_10:
162 break;
163 case SPEED_100:
164 ctl |= BMCR_SPEED100;
165 break;
166 case SPEED_1000:
167 ctl |= BMCR_SPEED1000;
168 break;
169 default:
170 return -EINVAL;
171 }
172 if (fd == DUPLEX_FULL)
173 ctl |= BMCR_FULLDPLX;
174 phy_write(phy, MII_BMCR, ctl);
175
176 return 0;
177}
178
179static int genmii_poll_link(struct mii_phy *phy)
180{
181 int status;
182
183 /* Clear latched value with dummy read */
184 phy_read(phy, MII_BMSR);
185 status = phy_read(phy, MII_BMSR);
186 if (status < 0 || (status & BMSR_LSTATUS) == 0)
187 return 0;
188 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
189 return 0;
190 return 1;
191}
192
193static int genmii_read_link(struct mii_phy *phy)
194{
195 if (phy->autoneg == AUTONEG_ENABLE) {
196 int glpa = 0;
197 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
198 if (lpa < 0)
199 return lpa;
200
201 if (phy->features &
202 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
203 int adv = phy_read(phy, MII_CTRL1000);
204 glpa = phy_read(phy, MII_STAT1000);
205
206 if (glpa < 0 || adv < 0)
207 return adv;
208
209 glpa &= adv << 2;
210 }
211
212 phy->speed = SPEED_10;
213 phy->duplex = DUPLEX_HALF;
214 phy->pause = phy->asym_pause = 0;
215
216 if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
217 phy->speed = SPEED_1000;
218 if (glpa & LPA_1000FULL)
219 phy->duplex = DUPLEX_FULL;
220 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
221 phy->speed = SPEED_100;
222 if (lpa & LPA_100FULL)
223 phy->duplex = DUPLEX_FULL;
224 } else if (lpa & LPA_10FULL)
225 phy->duplex = DUPLEX_FULL;
226
227 if (phy->duplex == DUPLEX_FULL) {
228 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
229 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
230 }
231 } else {
232 int bmcr = phy_read(phy, MII_BMCR);
233 if (bmcr < 0)
234 return bmcr;
235
236 if (bmcr & BMCR_FULLDPLX)
237 phy->duplex = DUPLEX_FULL;
238 else
239 phy->duplex = DUPLEX_HALF;
240 if (bmcr & BMCR_SPEED1000)
241 phy->speed = SPEED_1000;
242 else if (bmcr & BMCR_SPEED100)
243 phy->speed = SPEED_100;
244 else
245 phy->speed = SPEED_10;
246
247 phy->pause = phy->asym_pause = 0;
248 }
249 return 0;
250}
251
252/* Generic implementation for most 10/100/1000 PHYs */
253static struct mii_phy_ops generic_phy_ops = {
254 .setup_aneg = genmii_setup_aneg,
255 .setup_forced = genmii_setup_forced,
256 .poll_link = genmii_poll_link,
257 .read_link = genmii_read_link
258};
259
260static struct mii_phy_def genmii_phy_def = {
261 .phy_id = 0x00000000,
262 .phy_id_mask = 0x00000000,
263 .name = "Generic MII",
264 .ops = &generic_phy_ops
265};
266
267/* CIS8201 */
268#define MII_CIS8201_10BTCSR 0x16
269#define TENBTCSR_ECHO_DISABLE 0x2000
270#define MII_CIS8201_EPCR 0x17
271#define EPCR_MODE_MASK 0x3000
272#define EPCR_GMII_MODE 0x0000
273#define EPCR_RGMII_MODE 0x1000
274#define EPCR_TBI_MODE 0x2000
275#define EPCR_RTBI_MODE 0x3000
276#define MII_CIS8201_ACSR 0x1c
277#define ACSR_PIN_PRIO_SELECT 0x0004
278
279static int cis8201_init(struct mii_phy *phy)
280{
281 int epcr;
282
283 epcr = phy_read(phy, MII_CIS8201_EPCR);
284 if (epcr < 0)
285 return epcr;
286
287 epcr &= ~EPCR_MODE_MASK;
288
289 switch (phy->mode) {
290 case PHY_MODE_TBI:
291 epcr |= EPCR_TBI_MODE;
292 break;
293 case PHY_MODE_RTBI:
294 epcr |= EPCR_RTBI_MODE;
295 break;
296 case PHY_MODE_GMII:
297 epcr |= EPCR_GMII_MODE;
298 break;
299 case PHY_MODE_RGMII:
300 default:
301 epcr |= EPCR_RGMII_MODE;
302 }
303
304 phy_write(phy, MII_CIS8201_EPCR, epcr);
305
306 /* MII regs override strap pins */
307 phy_write(phy, MII_CIS8201_ACSR,
308 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
309
310 /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
311 phy_write(phy, MII_CIS8201_10BTCSR,
312 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
313
314 return 0;
315}
316
317static struct mii_phy_ops cis8201_phy_ops = {
318 .init = cis8201_init,
319 .setup_aneg = genmii_setup_aneg,
320 .setup_forced = genmii_setup_forced,
321 .poll_link = genmii_poll_link,
322 .read_link = genmii_read_link
323};
324
325static struct mii_phy_def cis8201_phy_def = {
326 .phy_id = 0x000fc410,
327 .phy_id_mask = 0x000ffff0,
328 .name = "CIS8201 Gigabit Ethernet",
329 .ops = &cis8201_phy_ops
330};
331
332static struct mii_phy_def *mii_phy_table[] = {
333 &cis8201_phy_def,
334 &genmii_phy_def,
335 NULL
336};
337
338int mii_phy_probe(struct mii_phy *phy, int address)
339{
340 struct mii_phy_def *def;
341 int i;
342 int id;
343
344 phy->autoneg = AUTONEG_DISABLE;
345 phy->advertising = 0;
346 phy->address = address;
347 phy->speed = SPEED_10;
348 phy->duplex = DUPLEX_HALF;
349 phy->pause = phy->asym_pause = 0;
350
351 /* Take PHY out of isolate mode and reset it. */
352 if (mii_reset_phy(phy))
353 return -ENODEV;
354
355 /* Read ID and find matching entry */
356 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
357 if (id < 0)
358 return -ENODEV;
359 for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
360 if ((id & def->phy_id_mask) == def->phy_id)
361 break;
362 /* Should never be NULL (we have a generic entry), but... */
363 if (!def)
364 return -ENODEV;
365
366 phy->def = def;
367
368 /* Determine PHY features if needed */
369 phy->features = def->features;
370 if (!phy->features) {
371 u16 bmsr = phy_read(phy, MII_BMSR);
372 if (bmsr & BMSR_ANEGCAPABLE)
373 phy->features |= SUPPORTED_Autoneg;
374 if (bmsr & BMSR_10HALF)
375 phy->features |= SUPPORTED_10baseT_Half;
376 if (bmsr & BMSR_10FULL)
377 phy->features |= SUPPORTED_10baseT_Full;
378 if (bmsr & BMSR_100HALF)
379 phy->features |= SUPPORTED_100baseT_Half;
380 if (bmsr & BMSR_100FULL)
381 phy->features |= SUPPORTED_100baseT_Full;
382 if (bmsr & BMSR_ESTATEN) {
383 u16 esr = phy_read(phy, MII_ESTATUS);
384 if (esr & ESTATUS_1000_TFULL)
385 phy->features |= SUPPORTED_1000baseT_Full;
386 if (esr & ESTATUS_1000_THALF)
387 phy->features |= SUPPORTED_1000baseT_Half;
388 }
389 phy->features |= SUPPORTED_MII;
390 }
391
392 /* Setup default advertising */
393 phy->advertising = phy->features;
394
395 return 0;
396}
397
398MODULE_LICENSE("GPL");
diff --git a/drivers/net/ibm_emac/ibm_emac_phy.h b/drivers/net/ibm_emac/ibm_emac_phy.h
deleted file mode 100644
index a70e0fea54c4..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_phy.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_phy.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support
5 *
6 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
7 * February 2003
8 *
9 * Minor additions by Eugene Surovegin <ebs@ebshome.net>, 2004
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This file basically duplicates sungem_phy.{c,h} with different PHYs
17 * supported. I'm looking into merging that in a single mii layer more
18 * flexible than mii.c
19 */
20
21#ifndef _IBM_OCP_PHY_H_
22#define _IBM_OCP_PHY_H_
23
24struct mii_phy;
25
26/* Operations supported by any kind of PHY */
27struct mii_phy_ops {
28 int (*init) (struct mii_phy * phy);
29 int (*suspend) (struct mii_phy * phy, int wol_options);
30 int (*setup_aneg) (struct mii_phy * phy, u32 advertise);
31 int (*setup_forced) (struct mii_phy * phy, int speed, int fd);
32 int (*poll_link) (struct mii_phy * phy);
33 int (*read_link) (struct mii_phy * phy);
34};
35
36/* Structure used to statically define an mii/gii based PHY */
37struct mii_phy_def {
38 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
39 u32 phy_id_mask; /* Significant bits */
40 u32 features; /* Ethtool SUPPORTED_* defines or
41 0 for autodetect */
42 int magic_aneg; /* Autoneg does all speed test for us */
43 const char *name;
44 const struct mii_phy_ops *ops;
45};
46
47/* An instance of a PHY, partially borrowed from mii_if_info */
48struct mii_phy {
49 struct mii_phy_def *def;
50 u32 advertising; /* Ethtool ADVERTISED_* defines */
51 u32 features; /* Copied from mii_phy_def.features
52 or determined automaticaly */
53 int address; /* PHY address */
54 int mode; /* PHY mode */
55
56 /* 1: autoneg enabled, 0: disabled */
57 int autoneg;
58
59 /* forced speed & duplex (no autoneg)
60 * partner speed & duplex & pause (autoneg)
61 */
62 int speed;
63 int duplex;
64 int pause;
65 int asym_pause;
66
67 /* Provided by host chip */
68 struct net_device *dev;
69 int (*mdio_read) (struct net_device * dev, int addr, int reg);
70 void (*mdio_write) (struct net_device * dev, int addr, int reg,
71 int val);
72};
73
74/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
75 * filled, the remaining fields will be filled on return
76 */
77int mii_phy_probe(struct mii_phy *phy, int address);
78int mii_reset_phy(struct mii_phy *phy);
79
80#endif /* _IBM_OCP_PHY_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_rgmii.c b/drivers/net/ibm_emac/ibm_emac_rgmii.c
deleted file mode 100644
index 9dbb5e5936c3..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_rgmii.c
+++ /dev/null
@@ -1,200 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_rgmii.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Copyright 2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/ethtool.h>
21#include <asm/io.h>
22
23#include "ibm_emac_core.h"
24#include "ibm_emac_debug.h"
25
26/* RGMIIx_FER */
27#define RGMII_FER_MASK(idx) (0x7 << ((idx) * 4))
28#define RGMII_FER_RTBI(idx) (0x4 << ((idx) * 4))
29#define RGMII_FER_RGMII(idx) (0x5 << ((idx) * 4))
30#define RGMII_FER_TBI(idx) (0x6 << ((idx) * 4))
31#define RGMII_FER_GMII(idx) (0x7 << ((idx) * 4))
32
33/* RGMIIx_SSR */
34#define RGMII_SSR_MASK(idx) (0x7 << ((idx) * 8))
35#define RGMII_SSR_100(idx) (0x2 << ((idx) * 8))
36#define RGMII_SSR_1000(idx) (0x4 << ((idx) * 8))
37
38/* RGMII bridge supports only GMII/TBI and RGMII/RTBI PHYs */
39static inline int rgmii_valid_mode(int phy_mode)
40{
41 return phy_mode == PHY_MODE_GMII ||
42 phy_mode == PHY_MODE_RGMII ||
43 phy_mode == PHY_MODE_TBI ||
44 phy_mode == PHY_MODE_RTBI;
45}
46
47static inline const char *rgmii_mode_name(int mode)
48{
49 switch (mode) {
50 case PHY_MODE_RGMII:
51 return "RGMII";
52 case PHY_MODE_TBI:
53 return "TBI";
54 case PHY_MODE_GMII:
55 return "GMII";
56 case PHY_MODE_RTBI:
57 return "RTBI";
58 default:
59 BUG();
60 }
61}
62
63static inline u32 rgmii_mode_mask(int mode, int input)
64{
65 switch (mode) {
66 case PHY_MODE_RGMII:
67 return RGMII_FER_RGMII(input);
68 case PHY_MODE_TBI:
69 return RGMII_FER_TBI(input);
70 case PHY_MODE_GMII:
71 return RGMII_FER_GMII(input);
72 case PHY_MODE_RTBI:
73 return RGMII_FER_RTBI(input);
74 default:
75 BUG();
76 }
77}
78
79static int __init rgmii_init(struct ocp_device *ocpdev, int input, int mode)
80{
81 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
82 struct rgmii_regs *p;
83
84 RGMII_DBG("%d: init(%d, %d)" NL, ocpdev->def->index, input, mode);
85
86 if (!dev) {
87 dev = kzalloc(sizeof(struct ibm_ocp_rgmii), GFP_KERNEL);
88 if (!dev) {
89 printk(KERN_ERR
90 "rgmii%d: couldn't allocate device structure!\n",
91 ocpdev->def->index);
92 return -ENOMEM;
93 }
94
95 p = (struct rgmii_regs *)ioremap(ocpdev->def->paddr,
96 sizeof(struct rgmii_regs));
97 if (!p) {
98 printk(KERN_ERR
99 "rgmii%d: could not ioremap device registers!\n",
100 ocpdev->def->index);
101 kfree(dev);
102 return -ENOMEM;
103 }
104
105 dev->base = p;
106 ocp_set_drvdata(ocpdev, dev);
107
108 /* Disable all inputs by default */
109 out_be32(&p->fer, 0);
110 } else
111 p = dev->base;
112
113 /* Enable this input */
114 out_be32(&p->fer, in_be32(&p->fer) | rgmii_mode_mask(mode, input));
115
116 printk(KERN_NOTICE "rgmii%d: input %d in %s mode\n",
117 ocpdev->def->index, input, rgmii_mode_name(mode));
118
119 ++dev->users;
120 return 0;
121}
122
123int __init rgmii_attach(void *emac)
124{
125 struct ocp_enet_private *dev = emac;
126 struct ocp_func_emac_data *emacdata = dev->def->additions;
127
128 /* Check if we need to attach to a RGMII */
129 if (emacdata->rgmii_idx >= 0 && rgmii_valid_mode(emacdata->phy_mode)) {
130 dev->rgmii_input = emacdata->rgmii_mux;
131 dev->rgmii_dev =
132 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_RGMII,
133 emacdata->rgmii_idx);
134 if (!dev->rgmii_dev) {
135 printk(KERN_ERR "emac%d: unknown rgmii%d!\n",
136 dev->def->index, emacdata->rgmii_idx);
137 return -ENODEV;
138 }
139 if (rgmii_init
140 (dev->rgmii_dev, dev->rgmii_input, emacdata->phy_mode)) {
141 printk(KERN_ERR
142 "emac%d: rgmii%d initialization failed!\n",
143 dev->def->index, emacdata->rgmii_idx);
144 return -ENODEV;
145 }
146 }
147 return 0;
148}
149
150void rgmii_set_speed(struct ocp_device *ocpdev, int input, int speed)
151{
152 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
153 u32 ssr = in_be32(&dev->base->ssr) & ~RGMII_SSR_MASK(input);
154
155 RGMII_DBG("%d: speed(%d, %d)" NL, ocpdev->def->index, input, speed);
156
157 if (speed == SPEED_1000)
158 ssr |= RGMII_SSR_1000(input);
159 else if (speed == SPEED_100)
160 ssr |= RGMII_SSR_100(input);
161
162 out_be32(&dev->base->ssr, ssr);
163}
164
165void __rgmii_fini(struct ocp_device *ocpdev, int input)
166{
167 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
168 BUG_ON(!dev || dev->users == 0);
169
170 RGMII_DBG("%d: fini(%d)" NL, ocpdev->def->index, input);
171
172 /* Disable this input */
173 out_be32(&dev->base->fer,
174 in_be32(&dev->base->fer) & ~RGMII_FER_MASK(input));
175
176 if (!--dev->users) {
177 /* Free everything if this is the last user */
178 ocp_set_drvdata(ocpdev, NULL);
179 iounmap((void *)dev->base);
180 kfree(dev);
181 }
182}
183
184int __rgmii_get_regs_len(struct ocp_device *ocpdev)
185{
186 return sizeof(struct emac_ethtool_regs_subhdr) +
187 sizeof(struct rgmii_regs);
188}
189
190void *rgmii_dump_regs(struct ocp_device *ocpdev, void *buf)
191{
192 struct ibm_ocp_rgmii *dev = ocp_get_drvdata(ocpdev);
193 struct emac_ethtool_regs_subhdr *hdr = buf;
194 struct rgmii_regs *regs = (struct rgmii_regs *)(hdr + 1);
195
196 hdr->version = 0;
197 hdr->index = ocpdev->def->index;
198 memcpy_fromio(regs, dev->base, sizeof(struct rgmii_regs));
199 return regs + 1;
200}
diff --git a/drivers/net/ibm_emac/ibm_emac_rgmii.h b/drivers/net/ibm_emac/ibm_emac_rgmii.h
deleted file mode 100644
index 971e45815c6c..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_rgmii.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_rgmii.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, RGMII bridge support.
5 *
6 * Based on ocp_zmii.h/ibm_emac_zmii.h
7 * Armin Kuster akuster@mvista.com
8 *
9 * Copyright 2004 MontaVista Software, Inc.
10 * Matt Porter <mporter@kernel.crashing.org>
11 *
12 * Copyright (c) 2004, 2005 Zultys Technologies.
13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef _IBM_EMAC_RGMII_H_
22#define _IBM_EMAC_RGMII_H_
23
24
25/* RGMII bridge */
26struct rgmii_regs {
27 u32 fer; /* Function enable register */
28 u32 ssr; /* Speed select register */
29};
30
31/* RGMII device */
32struct ibm_ocp_rgmii {
33 struct rgmii_regs __iomem *base;
34 int users; /* number of EMACs using this RGMII bridge */
35};
36
37#ifdef CONFIG_IBM_EMAC_RGMII
38int rgmii_attach(void *emac) __init;
39
40void __rgmii_fini(struct ocp_device *ocpdev, int input);
41static inline void rgmii_fini(struct ocp_device *ocpdev, int input)
42{
43 if (ocpdev)
44 __rgmii_fini(ocpdev, input);
45}
46
47void rgmii_set_speed(struct ocp_device *ocpdev, int input, int speed);
48
49int __rgmii_get_regs_len(struct ocp_device *ocpdev);
50static inline int rgmii_get_regs_len(struct ocp_device *ocpdev)
51{
52 return ocpdev ? __rgmii_get_regs_len(ocpdev) : 0;
53}
54
55void *rgmii_dump_regs(struct ocp_device *ocpdev, void *buf);
56#else
57# define rgmii_attach(x) 0
58# define rgmii_fini(x,y) ((void)0)
59# define rgmii_set_speed(x,y,z) ((void)0)
60# define rgmii_get_regs_len(x) 0
61# define rgmii_dump_regs(x,buf) (buf)
62#endif /* !CONFIG_IBM_EMAC_RGMII */
63
64#endif /* _IBM_EMAC_RGMII_H_ */
diff --git a/drivers/net/ibm_emac/ibm_emac_tah.c b/drivers/net/ibm_emac/ibm_emac_tah.c
deleted file mode 100644
index 3c2d5ba522a1..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_tah.c
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_tah.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, TAH support.
5 *
6 * Copyright 2004 MontaVista Software, Inc.
7 * Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Copyright (c) 2005 Eugene Surovegin <ebs@ebshome.net>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <asm/io.h>
17
18#include "ibm_emac_core.h"
19
20static int __init tah_init(struct ocp_device *ocpdev)
21{
22 struct tah_regs *p;
23
24 if (ocp_get_drvdata(ocpdev)) {
25 printk(KERN_ERR "tah%d: already in use!\n", ocpdev->def->index);
26 return -EBUSY;
27 }
28
29 /* Initialize TAH and enable IPv4 checksum verification, no TSO yet */
30 p = (struct tah_regs *)ioremap(ocpdev->def->paddr, sizeof(*p));
31 if (!p) {
32 printk(KERN_ERR "tah%d: could not ioremap device registers!\n",
33 ocpdev->def->index);
34 return -ENOMEM;
35 }
36 ocp_set_drvdata(ocpdev, p);
37 __tah_reset(ocpdev);
38
39 return 0;
40}
41
42int __init tah_attach(void *emac)
43{
44 struct ocp_enet_private *dev = emac;
45 struct ocp_func_emac_data *emacdata = dev->def->additions;
46
47 /* Check if we need to attach to a TAH */
48 if (emacdata->tah_idx >= 0) {
49 dev->tah_dev = ocp_find_device(OCP_ANY_ID, OCP_FUNC_TAH,
50 emacdata->tah_idx);
51 if (!dev->tah_dev) {
52 printk(KERN_ERR "emac%d: unknown tah%d!\n",
53 dev->def->index, emacdata->tah_idx);
54 return -ENODEV;
55 }
56 if (tah_init(dev->tah_dev)) {
57 printk(KERN_ERR
58 "emac%d: tah%d initialization failed!\n",
59 dev->def->index, emacdata->tah_idx);
60 return -ENODEV;
61 }
62 }
63 return 0;
64}
65
66void __tah_fini(struct ocp_device *ocpdev)
67{
68 struct tah_regs *p = ocp_get_drvdata(ocpdev);
69 BUG_ON(!p);
70 ocp_set_drvdata(ocpdev, NULL);
71 iounmap((void *)p);
72}
73
74void __tah_reset(struct ocp_device *ocpdev)
75{
76 struct tah_regs *p = ocp_get_drvdata(ocpdev);
77 int n;
78
79 /* Reset TAH */
80 out_be32(&p->mr, TAH_MR_SR);
81 n = 100;
82 while ((in_be32(&p->mr) & TAH_MR_SR) && n)
83 --n;
84
85 if (unlikely(!n))
86 printk(KERN_ERR "tah%d: reset timeout\n", ocpdev->def->index);
87
88 /* 10KB TAH TX FIFO accomodates the max MTU of 9000 */
89 out_be32(&p->mr,
90 TAH_MR_CVR | TAH_MR_ST_768 | TAH_MR_TFS_10KB | TAH_MR_DTFP |
91 TAH_MR_DIG);
92}
93
94int __tah_get_regs_len(struct ocp_device *ocpdev)
95{
96 return sizeof(struct emac_ethtool_regs_subhdr) +
97 sizeof(struct tah_regs);
98}
99
100void *tah_dump_regs(struct ocp_device *ocpdev, void *buf)
101{
102 struct tah_regs *dev = ocp_get_drvdata(ocpdev);
103 struct emac_ethtool_regs_subhdr *hdr = buf;
104 struct tah_regs *regs = (struct tah_regs *)(hdr + 1);
105
106 hdr->version = 0;
107 hdr->index = ocpdev->def->index;
108 memcpy_fromio(regs, dev, sizeof(struct tah_regs));
109 return regs + 1;
110}
diff --git a/drivers/net/ibm_emac/ibm_emac_tah.h b/drivers/net/ibm_emac/ibm_emac_tah.h
deleted file mode 100644
index ccf64915e1e4..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_tah.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_tah.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, TAH support.
5 *
6 * Copyright 2004 MontaVista Software, Inc.
7 * Matt Porter <mporter@kernel.crashing.org>
8 *
9 * Copyright (c) 2005 Eugene Surovegin <ebs@ebshome.net>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#ifndef _IBM_EMAC_TAH_H
18#define _IBM_EMAC_TAH_H
19
20#include <linux/init.h>
21#include <asm/ocp.h>
22
23/* TAH */
24struct tah_regs {
25 u32 revid;
26 u32 pad[3];
27 u32 mr;
28 u32 ssr0;
29 u32 ssr1;
30 u32 ssr2;
31 u32 ssr3;
32 u32 ssr4;
33 u32 ssr5;
34 u32 tsr;
35};
36
37/* TAH engine */
38#define TAH_MR_CVR 0x80000000
39#define TAH_MR_SR 0x40000000
40#define TAH_MR_ST_256 0x01000000
41#define TAH_MR_ST_512 0x02000000
42#define TAH_MR_ST_768 0x03000000
43#define TAH_MR_ST_1024 0x04000000
44#define TAH_MR_ST_1280 0x05000000
45#define TAH_MR_ST_1536 0x06000000
46#define TAH_MR_TFS_16KB 0x00000000
47#define TAH_MR_TFS_2KB 0x00200000
48#define TAH_MR_TFS_4KB 0x00400000
49#define TAH_MR_TFS_6KB 0x00600000
50#define TAH_MR_TFS_8KB 0x00800000
51#define TAH_MR_TFS_10KB 0x00a00000
52#define TAH_MR_DTFP 0x00100000
53#define TAH_MR_DIG 0x00080000
54
55#ifdef CONFIG_IBM_EMAC_TAH
56int tah_attach(void *emac) __init;
57
58void __tah_fini(struct ocp_device *ocpdev);
59static inline void tah_fini(struct ocp_device *ocpdev)
60{
61 if (ocpdev)
62 __tah_fini(ocpdev);
63}
64
65void __tah_reset(struct ocp_device *ocpdev);
66static inline void tah_reset(struct ocp_device *ocpdev)
67{
68 if (ocpdev)
69 __tah_reset(ocpdev);
70}
71
72int __tah_get_regs_len(struct ocp_device *ocpdev);
73static inline int tah_get_regs_len(struct ocp_device *ocpdev)
74{
75 return ocpdev ? __tah_get_regs_len(ocpdev) : 0;
76}
77
78void *tah_dump_regs(struct ocp_device *ocpdev, void *buf);
79#else
80# define tah_attach(x) 0
81# define tah_fini(x) ((void)0)
82# define tah_reset(x) ((void)0)
83# define tah_get_regs_len(x) 0
84# define tah_dump_regs(x,buf) (buf)
85#endif /* !CONFIG_IBM_EMAC_TAH */
86
87#endif /* _IBM_EMAC_TAH_H */
diff --git a/drivers/net/ibm_emac/ibm_emac_zmii.c b/drivers/net/ibm_emac/ibm_emac_zmii.c
deleted file mode 100644
index 2c0fdb0cabff..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_zmii.c
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_zmii.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, ZMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2001 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/ethtool.h>
21#include <asm/io.h>
22
23#include "ibm_emac_core.h"
24#include "ibm_emac_debug.h"
25
26/* ZMIIx_FER */
27#define ZMII_FER_MDI(idx) (0x80000000 >> ((idx) * 4))
28#define ZMII_FER_MDI_ALL (ZMII_FER_MDI(0) | ZMII_FER_MDI(1) | \
29 ZMII_FER_MDI(2) | ZMII_FER_MDI(3))
30
31#define ZMII_FER_SMII(idx) (0x40000000 >> ((idx) * 4))
32#define ZMII_FER_RMII(idx) (0x20000000 >> ((idx) * 4))
33#define ZMII_FER_MII(idx) (0x10000000 >> ((idx) * 4))
34
35/* ZMIIx_SSR */
36#define ZMII_SSR_SCI(idx) (0x40000000 >> ((idx) * 4))
37#define ZMII_SSR_FSS(idx) (0x20000000 >> ((idx) * 4))
38#define ZMII_SSR_SP(idx) (0x10000000 >> ((idx) * 4))
39
40/* ZMII only supports MII, RMII and SMII
41 * we also support autodetection for backward compatibility
42 */
43static inline int zmii_valid_mode(int mode)
44{
45 return mode == PHY_MODE_MII ||
46 mode == PHY_MODE_RMII ||
47 mode == PHY_MODE_SMII ||
48 mode == PHY_MODE_NA;
49}
50
51static inline const char *zmii_mode_name(int mode)
52{
53 switch (mode) {
54 case PHY_MODE_MII:
55 return "MII";
56 case PHY_MODE_RMII:
57 return "RMII";
58 case PHY_MODE_SMII:
59 return "SMII";
60 default:
61 BUG();
62 }
63}
64
65static inline u32 zmii_mode_mask(int mode, int input)
66{
67 switch (mode) {
68 case PHY_MODE_MII:
69 return ZMII_FER_MII(input);
70 case PHY_MODE_RMII:
71 return ZMII_FER_RMII(input);
72 case PHY_MODE_SMII:
73 return ZMII_FER_SMII(input);
74 default:
75 return 0;
76 }
77}
78
79static int __init zmii_init(struct ocp_device *ocpdev, int input, int *mode)
80{
81 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
82 struct zmii_regs __iomem *p;
83
84 ZMII_DBG("%d: init(%d, %d)" NL, ocpdev->def->index, input, *mode);
85
86 if (!dev) {
87 dev = kzalloc(sizeof(struct ibm_ocp_zmii), GFP_KERNEL);
88 if (!dev) {
89 printk(KERN_ERR
90 "zmii%d: couldn't allocate device structure!\n",
91 ocpdev->def->index);
92 return -ENOMEM;
93 }
94 dev->mode = PHY_MODE_NA;
95
96 p = ioremap(ocpdev->def->paddr, sizeof(struct zmii_regs));
97 if (!p) {
98 printk(KERN_ERR
99 "zmii%d: could not ioremap device registers!\n",
100 ocpdev->def->index);
101 kfree(dev);
102 return -ENOMEM;
103 }
104 dev->base = p;
105 ocp_set_drvdata(ocpdev, dev);
106
107 /* We may need FER value for autodetection later */
108 dev->fer_save = in_be32(&p->fer);
109
110 /* Disable all inputs by default */
111 out_be32(&p->fer, 0);
112 } else
113 p = dev->base;
114
115 if (!zmii_valid_mode(*mode)) {
116 /* Probably an EMAC connected to RGMII,
117 * but it still may need ZMII for MDIO
118 */
119 goto out;
120 }
121
122 /* Autodetect ZMII mode if not specified.
123 * This is only for backward compatibility with the old driver.
124 * Please, always specify PHY mode in your board port to avoid
125 * any surprises.
126 */
127 if (dev->mode == PHY_MODE_NA) {
128 if (*mode == PHY_MODE_NA) {
129 u32 r = dev->fer_save;
130
131 ZMII_DBG("%d: autodetecting mode, FER = 0x%08x" NL,
132 ocpdev->def->index, r);
133
134 if (r & (ZMII_FER_MII(0) | ZMII_FER_MII(1)))
135 dev->mode = PHY_MODE_MII;
136 else if (r & (ZMII_FER_RMII(0) | ZMII_FER_RMII(1)))
137 dev->mode = PHY_MODE_RMII;
138 else
139 dev->mode = PHY_MODE_SMII;
140 } else
141 dev->mode = *mode;
142
143 printk(KERN_NOTICE "zmii%d: bridge in %s mode\n",
144 ocpdev->def->index, zmii_mode_name(dev->mode));
145 } else {
146 /* All inputs must use the same mode */
147 if (*mode != PHY_MODE_NA && *mode != dev->mode) {
148 printk(KERN_ERR
149 "zmii%d: invalid mode %d specified for input %d\n",
150 ocpdev->def->index, *mode, input);
151 return -EINVAL;
152 }
153 }
154
155 /* Report back correct PHY mode,
156 * it may be used during PHY initialization.
157 */
158 *mode = dev->mode;
159
160 /* Enable this input */
161 out_be32(&p->fer, in_be32(&p->fer) | zmii_mode_mask(dev->mode, input));
162 out:
163 ++dev->users;
164 return 0;
165}
166
167int __init zmii_attach(void *emac)
168{
169 struct ocp_enet_private *dev = emac;
170 struct ocp_func_emac_data *emacdata = dev->def->additions;
171
172 if (emacdata->zmii_idx >= 0) {
173 dev->zmii_input = emacdata->zmii_mux;
174 dev->zmii_dev =
175 ocp_find_device(OCP_VENDOR_IBM, OCP_FUNC_ZMII,
176 emacdata->zmii_idx);
177 if (!dev->zmii_dev) {
178 printk(KERN_ERR "emac%d: unknown zmii%d!\n",
179 dev->def->index, emacdata->zmii_idx);
180 return -ENODEV;
181 }
182 if (zmii_init
183 (dev->zmii_dev, dev->zmii_input, &emacdata->phy_mode)) {
184 printk(KERN_ERR
185 "emac%d: zmii%d initialization failed!\n",
186 dev->def->index, emacdata->zmii_idx);
187 return -ENODEV;
188 }
189 }
190 return 0;
191}
192
193void __zmii_enable_mdio(struct ocp_device *ocpdev, int input)
194{
195 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
196 u32 fer = in_be32(&dev->base->fer) & ~ZMII_FER_MDI_ALL;
197
198 ZMII_DBG2("%d: mdio(%d)" NL, ocpdev->def->index, input);
199
200 out_be32(&dev->base->fer, fer | ZMII_FER_MDI(input));
201}
202
203void __zmii_set_speed(struct ocp_device *ocpdev, int input, int speed)
204{
205 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
206 u32 ssr = in_be32(&dev->base->ssr);
207
208 ZMII_DBG("%d: speed(%d, %d)" NL, ocpdev->def->index, input, speed);
209
210 if (speed == SPEED_100)
211 ssr |= ZMII_SSR_SP(input);
212 else
213 ssr &= ~ZMII_SSR_SP(input);
214
215 out_be32(&dev->base->ssr, ssr);
216}
217
218void __zmii_fini(struct ocp_device *ocpdev, int input)
219{
220 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
221 BUG_ON(!dev || dev->users == 0);
222
223 ZMII_DBG("%d: fini(%d)" NL, ocpdev->def->index, input);
224
225 /* Disable this input */
226 out_be32(&dev->base->fer,
227 in_be32(&dev->base->fer) & ~zmii_mode_mask(dev->mode, input));
228
229 if (!--dev->users) {
230 /* Free everything if this is the last user */
231 ocp_set_drvdata(ocpdev, NULL);
232 iounmap(dev->base);
233 kfree(dev);
234 }
235}
236
237int __zmii_get_regs_len(struct ocp_device *ocpdev)
238{
239 return sizeof(struct emac_ethtool_regs_subhdr) +
240 sizeof(struct zmii_regs);
241}
242
243void *zmii_dump_regs(struct ocp_device *ocpdev, void *buf)
244{
245 struct ibm_ocp_zmii *dev = ocp_get_drvdata(ocpdev);
246 struct emac_ethtool_regs_subhdr *hdr = buf;
247 struct zmii_regs *regs = (struct zmii_regs *)(hdr + 1);
248
249 hdr->version = 0;
250 hdr->index = ocpdev->def->index;
251 memcpy_fromio(regs, dev->base, sizeof(struct zmii_regs));
252 return regs + 1;
253}
diff --git a/drivers/net/ibm_emac/ibm_emac_zmii.h b/drivers/net/ibm_emac/ibm_emac_zmii.h
deleted file mode 100644
index fad6d8bf983a..000000000000
--- a/drivers/net/ibm_emac/ibm_emac_zmii.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * drivers/net/ibm_emac/ibm_emac_zmii.h
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller, ZMII bridge support.
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Armin Kuster <akuster@mvista.com>
11 * Copyright 2001 MontaVista Softare Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19#ifndef _IBM_EMAC_ZMII_H_
20#define _IBM_EMAC_ZMII_H_
21
22#include <linux/init.h>
23#include <asm/ocp.h>
24
25/* ZMII bridge registers */
26struct zmii_regs {
27 u32 fer; /* Function enable reg */
28 u32 ssr; /* Speed select reg */
29 u32 smiirs; /* SMII status reg */
30};
31
32/* ZMII device */
33struct ibm_ocp_zmii {
34 struct zmii_regs __iomem *base;
35 int mode; /* subset of PHY_MODE_XXXX */
36 int users; /* number of EMACs using this ZMII bridge */
37 u32 fer_save; /* FER value left by firmware */
38};
39
40#ifdef CONFIG_IBM_EMAC_ZMII
41int zmii_attach(void *emac) __init;
42
43void __zmii_fini(struct ocp_device *ocpdev, int input);
44static inline void zmii_fini(struct ocp_device *ocpdev, int input)
45{
46 if (ocpdev)
47 __zmii_fini(ocpdev, input);
48}
49
50void __zmii_enable_mdio(struct ocp_device *ocpdev, int input);
51static inline void zmii_enable_mdio(struct ocp_device *ocpdev, int input)
52{
53 if (ocpdev)
54 __zmii_enable_mdio(ocpdev, input);
55}
56
57void __zmii_set_speed(struct ocp_device *ocpdev, int input, int speed);
58static inline void zmii_set_speed(struct ocp_device *ocpdev, int input,
59 int speed)
60{
61 if (ocpdev)
62 __zmii_set_speed(ocpdev, input, speed);
63}
64
65int __zmii_get_regs_len(struct ocp_device *ocpdev);
66static inline int zmii_get_regs_len(struct ocp_device *ocpdev)
67{
68 return ocpdev ? __zmii_get_regs_len(ocpdev) : 0;
69}
70
71void *zmii_dump_regs(struct ocp_device *ocpdev, void *buf);
72
73#else
74# define zmii_attach(x) 0
75# define zmii_fini(x,y) ((void)0)
76# define zmii_enable_mdio(x,y) ((void)0)
77# define zmii_set_speed(x,y,z) ((void)0)
78# define zmii_get_regs_len(x) 0
79# define zmii_dump_regs(x,buf) (buf)
80#endif /* !CONFIG_IBM_EMAC_ZMII */
81
82#endif /* _IBM_EMAC_ZMII_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 11:25:19 -0500