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path: root/drivers/net/forcedeth.c
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-rw-r--r--drivers/net/forcedeth.c1321
1 files changed, 553 insertions, 768 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 4da05b1b445c..537b6957bb79 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -39,6 +39,9 @@
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic. 40 * superfluous timer interrupts from the nic.
41 */ 41 */
42
43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
42#define FORCEDETH_VERSION "0.64" 45#define FORCEDETH_VERSION "0.64"
43#define DRV_NAME "forcedeth" 46#define DRV_NAME "forcedeth"
44 47
@@ -60,18 +63,13 @@
60#include <linux/if_vlan.h> 63#include <linux/if_vlan.h>
61#include <linux/dma-mapping.h> 64#include <linux/dma-mapping.h>
62#include <linux/slab.h> 65#include <linux/slab.h>
66#include <linux/uaccess.h>
67#include <linux/prefetch.h>
68#include <linux/io.h>
63 69
64#include <asm/irq.h> 70#include <asm/irq.h>
65#include <asm/io.h>
66#include <asm/uaccess.h>
67#include <asm/system.h> 71#include <asm/system.h>
68 72
69#if 0
70#define dprintk printk
71#else
72#define dprintk(x...) do { } while (0)
73#endif
74
75#define TX_WORK_PER_LOOP 64 73#define TX_WORK_PER_LOOP 64
76#define RX_WORK_PER_LOOP 64 74#define RX_WORK_PER_LOOP 64
77 75
@@ -186,9 +184,9 @@ enum {
186 NvRegSlotTime = 0x9c, 184 NvRegSlotTime = 0x9c,
187#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 185#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
188#define NVREG_SLOTTIME_10_100_FULL 0x00007f00 186#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
189#define NVREG_SLOTTIME_1000_FULL 0x0003ff00 187#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
190#define NVREG_SLOTTIME_HALF 0x0000ff00 188#define NVREG_SLOTTIME_HALF 0x0000ff00
191#define NVREG_SLOTTIME_DEFAULT 0x00007f00 189#define NVREG_SLOTTIME_DEFAULT 0x00007f00
192#define NVREG_SLOTTIME_MASK 0x000000ff 190#define NVREG_SLOTTIME_MASK 0x000000ff
193 191
194 NvRegTxDeferral = 0xA0, 192 NvRegTxDeferral = 0xA0,
@@ -297,7 +295,7 @@ enum {
297#define NVREG_WAKEUPFLAGS_ENABLE 0x1111 295#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
298 296
299 NvRegMgmtUnitGetVersion = 0x204, 297 NvRegMgmtUnitGetVersion = 0x204,
300#define NVREG_MGMTUNITGETVERSION 0x01 298#define NVREG_MGMTUNITGETVERSION 0x01
301 NvRegMgmtUnitVersion = 0x208, 299 NvRegMgmtUnitVersion = 0x208,
302#define NVREG_MGMTUNITVERSION 0x08 300#define NVREG_MGMTUNITVERSION 0x08
303 NvRegPowerCap = 0x268, 301 NvRegPowerCap = 0x268,
@@ -368,8 +366,8 @@ struct ring_desc_ex {
368}; 366};
369 367
370union ring_type { 368union ring_type {
371 struct ring_desc* orig; 369 struct ring_desc *orig;
372 struct ring_desc_ex* ex; 370 struct ring_desc_ex *ex;
373}; 371};
374 372
375#define FLAG_MASK_V1 0xffff0000 373#define FLAG_MASK_V1 0xffff0000
@@ -443,11 +441,11 @@ union ring_type {
443#define NV_RX3_VLAN_TAG_PRESENT (1<<16) 441#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
444#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) 442#define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
445 443
446/* Miscelaneous hardware related defines: */ 444/* Miscellaneous hardware related defines: */
447#define NV_PCI_REGSZ_VER1 0x270 445#define NV_PCI_REGSZ_VER1 0x270
448#define NV_PCI_REGSZ_VER2 0x2d4 446#define NV_PCI_REGSZ_VER2 0x2d4
449#define NV_PCI_REGSZ_VER3 0x604 447#define NV_PCI_REGSZ_VER3 0x604
450#define NV_PCI_REGSZ_MAX 0x604 448#define NV_PCI_REGSZ_MAX 0x604
451 449
452/* various timeout delays: all in usec */ 450/* various timeout delays: all in usec */
453#define NV_TXRX_RESET_DELAY 4 451#define NV_TXRX_RESET_DELAY 4
@@ -717,7 +715,7 @@ static const struct register_test nv_registers_test[] = {
717 { NvRegMulticastAddrA, 0xffffffff }, 715 { NvRegMulticastAddrA, 0xffffffff },
718 { NvRegTxWatermark, 0x0ff }, 716 { NvRegTxWatermark, 0x0ff },
719 { NvRegWakeUpFlags, 0x07777 }, 717 { NvRegWakeUpFlags, 0x07777 },
720 { 0,0 } 718 { 0, 0 }
721}; 719};
722 720
723struct nv_skb_map { 721struct nv_skb_map {
@@ -777,7 +775,6 @@ struct fe_priv {
777 u32 driver_data; 775 u32 driver_data;
778 u32 device_id; 776 u32 device_id;
779 u32 register_size; 777 u32 register_size;
780 int rx_csum;
781 u32 mac_in_use; 778 u32 mac_in_use;
782 int mgmt_version; 779 int mgmt_version;
783 int mgmt_sema; 780 int mgmt_sema;
@@ -911,7 +908,7 @@ static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
911 * Power down phy when interface is down (persists through reboot; 908 * Power down phy when interface is down (persists through reboot;
912 * older Linux and other OSes may not power it up again) 909 * older Linux and other OSes may not power it up again)
913 */ 910 */
914static int phy_power_down = 0; 911static int phy_power_down;
915 912
916static inline struct fe_priv *get_nvpriv(struct net_device *dev) 913static inline struct fe_priv *get_nvpriv(struct net_device *dev)
917{ 914{
@@ -948,7 +945,7 @@ static bool nv_optimized(struct fe_priv *np)
948} 945}
949 946
950static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, 947static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
951 int delay, int delaymax, const char *msg) 948 int delay, int delaymax)
952{ 949{
953 u8 __iomem *base = get_hwbase(dev); 950 u8 __iomem *base = get_hwbase(dev);
954 951
@@ -956,11 +953,8 @@ static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
956 do { 953 do {
957 udelay(delay); 954 udelay(delay);
958 delaymax -= delay; 955 delaymax -= delay;
959 if (delaymax < 0) { 956 if (delaymax < 0)
960 if (msg)
961 printk("%s", msg);
962 return 1; 957 return 1;
963 }
964 } while ((readl(base + offset) & mask) != target); 958 } while ((readl(base + offset) & mask) != target);
965 return 0; 959 return 0;
966} 960}
@@ -984,12 +978,10 @@ static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
984 u8 __iomem *base = get_hwbase(dev); 978 u8 __iomem *base = get_hwbase(dev);
985 979
986 if (!nv_optimized(np)) { 980 if (!nv_optimized(np)) {
987 if (rxtx_flags & NV_SETUP_RX_RING) { 981 if (rxtx_flags & NV_SETUP_RX_RING)
988 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); 982 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
989 } 983 if (rxtx_flags & NV_SETUP_TX_RING)
990 if (rxtx_flags & NV_SETUP_TX_RING) {
991 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); 984 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
992 }
993 } else { 985 } else {
994 if (rxtx_flags & NV_SETUP_RX_RING) { 986 if (rxtx_flags & NV_SETUP_RX_RING) {
995 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); 987 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
@@ -1015,10 +1007,8 @@ static void free_rings(struct net_device *dev)
1015 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), 1007 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1016 np->rx_ring.ex, np->ring_addr); 1008 np->rx_ring.ex, np->ring_addr);
1017 } 1009 }
1018 if (np->rx_skb) 1010 kfree(np->rx_skb);
1019 kfree(np->rx_skb); 1011 kfree(np->tx_skb);
1020 if (np->tx_skb)
1021 kfree(np->tx_skb);
1022} 1012}
1023 1013
1024static int using_multi_irqs(struct net_device *dev) 1014static int using_multi_irqs(struct net_device *dev)
@@ -1145,23 +1135,15 @@ static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1145 writel(reg, base + NvRegMIIControl); 1135 writel(reg, base + NvRegMIIControl);
1146 1136
1147 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, 1137 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1148 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { 1138 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1149 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1150 dev->name, miireg, addr);
1151 retval = -1; 1139 retval = -1;
1152 } else if (value != MII_READ) { 1140 } else if (value != MII_READ) {
1153 /* it was a write operation - fewer failures are detectable */ 1141 /* it was a write operation - fewer failures are detectable */
1154 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1155 dev->name, value, miireg, addr);
1156 retval = 0; 1142 retval = 0;
1157 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { 1143 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1158 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1159 dev->name, miireg, addr);
1160 retval = -1; 1144 retval = -1;
1161 } else { 1145 } else {
1162 retval = readl(base + NvRegMIIData); 1146 retval = readl(base + NvRegMIIData);
1163 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1164 dev->name, miireg, addr, retval);
1165 } 1147 }
1166 1148
1167 return retval; 1149 return retval;
@@ -1174,16 +1156,15 @@ static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1174 unsigned int tries = 0; 1156 unsigned int tries = 0;
1175 1157
1176 miicontrol = BMCR_RESET | bmcr_setup; 1158 miicontrol = BMCR_RESET | bmcr_setup;
1177 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { 1159 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1178 return -1; 1160 return -1;
1179 }
1180 1161
1181 /* wait for 500ms */ 1162 /* wait for 500ms */
1182 msleep(500); 1163 msleep(500);
1183 1164
1184 /* must wait till reset is deasserted */ 1165 /* must wait till reset is deasserted */
1185 while (miicontrol & BMCR_RESET) { 1166 while (miicontrol & BMCR_RESET) {
1186 msleep(10); 1167 usleep_range(10000, 20000);
1187 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 1168 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1188 /* FIXME: 100 tries seem excessive */ 1169 /* FIXME: 100 tries seem excessive */
1189 if (tries++ > 100) 1170 if (tries++ > 100)
@@ -1192,106 +1173,239 @@ static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1192 return 0; 1173 return 0;
1193} 1174}
1194 1175
1176static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1177{
1178 static const struct {
1179 int reg;
1180 int init;
1181 } ri[] = {
1182 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1183 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1184 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1185 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1186 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1187 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1188 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1189 };
1190 int i;
1191
1192 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1193 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1194 return PHY_ERROR;
1195 }
1196
1197 return 0;
1198}
1199
1200static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1201{
1202 u32 reg;
1203 u8 __iomem *base = get_hwbase(dev);
1204 u32 powerstate = readl(base + NvRegPowerState2);
1205
1206 /* need to perform hw phy reset */
1207 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1208 writel(powerstate, base + NvRegPowerState2);
1209 msleep(25);
1210
1211 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1212 writel(powerstate, base + NvRegPowerState2);
1213 msleep(25);
1214
1215 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1216 reg |= PHY_REALTEK_INIT9;
1217 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1218 return PHY_ERROR;
1219 if (mii_rw(dev, np->phyaddr,
1220 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1221 return PHY_ERROR;
1222 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1223 if (!(reg & PHY_REALTEK_INIT11)) {
1224 reg |= PHY_REALTEK_INIT11;
1225 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1226 return PHY_ERROR;
1227 }
1228 if (mii_rw(dev, np->phyaddr,
1229 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1230 return PHY_ERROR;
1231
1232 return 0;
1233}
1234
1235static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1236{
1237 u32 phy_reserved;
1238
1239 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1240 phy_reserved = mii_rw(dev, np->phyaddr,
1241 PHY_REALTEK_INIT_REG6, MII_READ);
1242 phy_reserved |= PHY_REALTEK_INIT7;
1243 if (mii_rw(dev, np->phyaddr,
1244 PHY_REALTEK_INIT_REG6, phy_reserved))
1245 return PHY_ERROR;
1246 }
1247
1248 return 0;
1249}
1250
1251static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1252{
1253 u32 phy_reserved;
1254
1255 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1256 if (mii_rw(dev, np->phyaddr,
1257 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1258 return PHY_ERROR;
1259 phy_reserved = mii_rw(dev, np->phyaddr,
1260 PHY_REALTEK_INIT_REG2, MII_READ);
1261 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1262 phy_reserved |= PHY_REALTEK_INIT3;
1263 if (mii_rw(dev, np->phyaddr,
1264 PHY_REALTEK_INIT_REG2, phy_reserved))
1265 return PHY_ERROR;
1266 if (mii_rw(dev, np->phyaddr,
1267 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1268 return PHY_ERROR;
1269 }
1270
1271 return 0;
1272}
1273
1274static int init_cicada(struct net_device *dev, struct fe_priv *np,
1275 u32 phyinterface)
1276{
1277 u32 phy_reserved;
1278
1279 if (phyinterface & PHY_RGMII) {
1280 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1281 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1282 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1283 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1284 return PHY_ERROR;
1285 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1286 phy_reserved |= PHY_CICADA_INIT5;
1287 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1288 return PHY_ERROR;
1289 }
1290 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1291 phy_reserved |= PHY_CICADA_INIT6;
1292 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1293 return PHY_ERROR;
1294
1295 return 0;
1296}
1297
1298static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1299{
1300 u32 phy_reserved;
1301
1302 if (mii_rw(dev, np->phyaddr,
1303 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1304 return PHY_ERROR;
1305 if (mii_rw(dev, np->phyaddr,
1306 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1307 return PHY_ERROR;
1308 phy_reserved = mii_rw(dev, np->phyaddr,
1309 PHY_VITESSE_INIT_REG4, MII_READ);
1310 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1311 return PHY_ERROR;
1312 phy_reserved = mii_rw(dev, np->phyaddr,
1313 PHY_VITESSE_INIT_REG3, MII_READ);
1314 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1315 phy_reserved |= PHY_VITESSE_INIT3;
1316 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1317 return PHY_ERROR;
1318 if (mii_rw(dev, np->phyaddr,
1319 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1320 return PHY_ERROR;
1321 if (mii_rw(dev, np->phyaddr,
1322 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1323 return PHY_ERROR;
1324 phy_reserved = mii_rw(dev, np->phyaddr,
1325 PHY_VITESSE_INIT_REG4, MII_READ);
1326 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1327 phy_reserved |= PHY_VITESSE_INIT3;
1328 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1329 return PHY_ERROR;
1330 phy_reserved = mii_rw(dev, np->phyaddr,
1331 PHY_VITESSE_INIT_REG3, MII_READ);
1332 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1333 return PHY_ERROR;
1334 if (mii_rw(dev, np->phyaddr,
1335 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1336 return PHY_ERROR;
1337 if (mii_rw(dev, np->phyaddr,
1338 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1339 return PHY_ERROR;
1340 phy_reserved = mii_rw(dev, np->phyaddr,
1341 PHY_VITESSE_INIT_REG4, MII_READ);
1342 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1343 return PHY_ERROR;
1344 phy_reserved = mii_rw(dev, np->phyaddr,
1345 PHY_VITESSE_INIT_REG3, MII_READ);
1346 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1347 phy_reserved |= PHY_VITESSE_INIT8;
1348 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1349 return PHY_ERROR;
1350 if (mii_rw(dev, np->phyaddr,
1351 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1352 return PHY_ERROR;
1353 if (mii_rw(dev, np->phyaddr,
1354 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1355 return PHY_ERROR;
1356
1357 return 0;
1358}
1359
1195static int phy_init(struct net_device *dev) 1360static int phy_init(struct net_device *dev)
1196{ 1361{
1197 struct fe_priv *np = get_nvpriv(dev); 1362 struct fe_priv *np = get_nvpriv(dev);
1198 u8 __iomem *base = get_hwbase(dev); 1363 u8 __iomem *base = get_hwbase(dev);
1199 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; 1364 u32 phyinterface;
1365 u32 mii_status, mii_control, mii_control_1000, reg;
1200 1366
1201 /* phy errata for E3016 phy */ 1367 /* phy errata for E3016 phy */
1202 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { 1368 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1203 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); 1369 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1204 reg &= ~PHY_MARVELL_E3016_INITMASK; 1370 reg &= ~PHY_MARVELL_E3016_INITMASK;
1205 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { 1371 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1206 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); 1372 netdev_info(dev, "%s: phy write to errata reg failed\n",
1373 pci_name(np->pci_dev));
1207 return PHY_ERROR; 1374 return PHY_ERROR;
1208 } 1375 }
1209 } 1376 }
1210 if (np->phy_oui == PHY_OUI_REALTEK) { 1377 if (np->phy_oui == PHY_OUI_REALTEK) {
1211 if (np->phy_model == PHY_MODEL_REALTEK_8211 && 1378 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1212 np->phy_rev == PHY_REV_REALTEK_8211B) { 1379 np->phy_rev == PHY_REV_REALTEK_8211B) {
1213 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1380 if (init_realtek_8211b(dev, np)) {
1214 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1381 netdev_info(dev, "%s: phy init failed\n",
1215 return PHY_ERROR; 1382 pci_name(np->pci_dev));
1216 }
1217 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1218 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1219 return PHY_ERROR;
1220 }
1221 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1222 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1223 return PHY_ERROR;
1224 }
1225 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1226 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1227 return PHY_ERROR; 1383 return PHY_ERROR;
1228 } 1384 }
1229 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { 1385 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1230 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1386 np->phy_rev == PHY_REV_REALTEK_8211C) {
1387 if (init_realtek_8211c(dev, np)) {
1388 netdev_info(dev, "%s: phy init failed\n",
1389 pci_name(np->pci_dev));
1231 return PHY_ERROR; 1390 return PHY_ERROR;
1232 } 1391 }
1233 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { 1392 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1234 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1393 if (init_realtek_8201(dev, np)) {
1235 return PHY_ERROR; 1394 netdev_info(dev, "%s: phy init failed\n",
1236 } 1395 pci_name(np->pci_dev));
1237 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1238 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239 return PHY_ERROR; 1396 return PHY_ERROR;
1240 } 1397 }
1241 } 1398 }
1242 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1243 np->phy_rev == PHY_REV_REALTEK_8211C) {
1244 u32 powerstate = readl(base + NvRegPowerState2);
1245
1246 /* need to perform hw phy reset */
1247 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1248 writel(powerstate, base + NvRegPowerState2);
1249 msleep(25);
1250
1251 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1252 writel(powerstate, base + NvRegPowerState2);
1253 msleep(25);
1254
1255 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1256 reg |= PHY_REALTEK_INIT9;
1257 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1258 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1259 return PHY_ERROR;
1260 }
1261 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1262 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1263 return PHY_ERROR;
1264 }
1265 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1266 if (!(reg & PHY_REALTEK_INIT11)) {
1267 reg |= PHY_REALTEK_INIT11;
1268 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1269 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1270 return PHY_ERROR;
1271 }
1272 }
1273 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1274 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1275 return PHY_ERROR;
1276 }
1277 }
1278 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1279 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1280 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1281 phy_reserved |= PHY_REALTEK_INIT7;
1282 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1283 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284 return PHY_ERROR;
1285 }
1286 }
1287 }
1288 } 1399 }
1289 1400
1290 /* set advertise register */ 1401 /* set advertise register */
1291 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); 1402 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1292 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); 1403 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1404 ADVERTISE_100HALF | ADVERTISE_100FULL |
1405 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1293 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { 1406 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1294 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); 1407 netdev_info(dev, "%s: phy write to advertise failed\n",
1408 pci_name(np->pci_dev));
1295 return PHY_ERROR; 1409 return PHY_ERROR;
1296 } 1410 }
1297 1411
@@ -1302,7 +1416,8 @@ static int phy_init(struct net_device *dev)
1302 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); 1416 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1303 if (mii_status & PHY_GIGABIT) { 1417 if (mii_status & PHY_GIGABIT) {
1304 np->gigabit = PHY_GIGABIT; 1418 np->gigabit = PHY_GIGABIT;
1305 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); 1419 mii_control_1000 = mii_rw(dev, np->phyaddr,
1420 MII_CTRL1000, MII_READ);
1306 mii_control_1000 &= ~ADVERTISE_1000HALF; 1421 mii_control_1000 &= ~ADVERTISE_1000HALF;
1307 if (phyinterface & PHY_RGMII) 1422 if (phyinterface & PHY_RGMII)
1308 mii_control_1000 |= ADVERTISE_1000FULL; 1423 mii_control_1000 |= ADVERTISE_1000FULL;
@@ -1310,11 +1425,11 @@ static int phy_init(struct net_device *dev)
1310 mii_control_1000 &= ~ADVERTISE_1000FULL; 1425 mii_control_1000 &= ~ADVERTISE_1000FULL;
1311 1426
1312 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { 1427 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1313 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1428 netdev_info(dev, "%s: phy init failed\n",
1429 pci_name(np->pci_dev));
1314 return PHY_ERROR; 1430 return PHY_ERROR;
1315 } 1431 }
1316 } 1432 } else
1317 else
1318 np->gigabit = 0; 1433 np->gigabit = 0;
1319 1434
1320 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 1435 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
@@ -1326,7 +1441,8 @@ static int phy_init(struct net_device *dev)
1326 /* start autoneg since we already performed hw reset above */ 1441 /* start autoneg since we already performed hw reset above */
1327 mii_control |= BMCR_ANRESTART; 1442 mii_control |= BMCR_ANRESTART;
1328 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { 1443 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1329 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev)); 1444 netdev_info(dev, "%s: phy init failed\n",
1445 pci_name(np->pci_dev));
1330 return PHY_ERROR; 1446 return PHY_ERROR;
1331 } 1447 }
1332 } else { 1448 } else {
@@ -1334,179 +1450,54 @@ static int phy_init(struct net_device *dev)
1334 * (certain phys need bmcr to be setup with reset) 1450 * (certain phys need bmcr to be setup with reset)
1335 */ 1451 */
1336 if (phy_reset(dev, mii_control)) { 1452 if (phy_reset(dev, mii_control)) {
1337 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); 1453 netdev_info(dev, "%s: phy reset failed\n",
1454 pci_name(np->pci_dev));
1338 return PHY_ERROR; 1455 return PHY_ERROR;
1339 } 1456 }
1340 } 1457 }
1341 1458
1342 /* phy vendor specific configuration */ 1459 /* phy vendor specific configuration */
1343 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { 1460 if ((np->phy_oui == PHY_OUI_CICADA)) {
1344 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); 1461 if (init_cicada(dev, np, phyinterface)) {
1345 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); 1462 netdev_info(dev, "%s: phy init failed\n",
1346 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); 1463 pci_name(np->pci_dev));
1347 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1348 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1349 return PHY_ERROR;
1350 }
1351 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1352 phy_reserved |= PHY_CICADA_INIT5;
1353 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1354 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1355 return PHY_ERROR;
1356 }
1357 }
1358 if (np->phy_oui == PHY_OUI_CICADA) {
1359 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1360 phy_reserved |= PHY_CICADA_INIT6;
1361 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1362 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1363 return PHY_ERROR;
1364 }
1365 }
1366 if (np->phy_oui == PHY_OUI_VITESSE) {
1367 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1368 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1369 return PHY_ERROR;
1370 }
1371 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1372 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1373 return PHY_ERROR;
1374 }
1375 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1376 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1377 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1378 return PHY_ERROR;
1379 }
1380 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1381 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1382 phy_reserved |= PHY_VITESSE_INIT3;
1383 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1384 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1385 return PHY_ERROR;
1386 }
1387 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1388 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1389 return PHY_ERROR; 1464 return PHY_ERROR;
1390 } 1465 }
1391 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { 1466 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1392 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1467 if (init_vitesse(dev, np)) {
1468 netdev_info(dev, "%s: phy init failed\n",
1469 pci_name(np->pci_dev));
1393 return PHY_ERROR; 1470 return PHY_ERROR;
1394 } 1471 }
1395 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); 1472 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1396 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1397 phy_reserved |= PHY_VITESSE_INIT3;
1398 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1399 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1400 return PHY_ERROR;
1401 }
1402 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1403 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1404 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1405 return PHY_ERROR;
1406 }
1407 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1408 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1409 return PHY_ERROR;
1410 }
1411 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1412 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1413 return PHY_ERROR;
1414 }
1415 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1416 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1417 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1418 return PHY_ERROR;
1419 }
1420 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1421 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1422 phy_reserved |= PHY_VITESSE_INIT8;
1423 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1424 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1425 return PHY_ERROR;
1426 }
1427 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1428 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1429 return PHY_ERROR;
1430 }
1431 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1432 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1433 return PHY_ERROR;
1434 }
1435 }
1436 if (np->phy_oui == PHY_OUI_REALTEK) {
1437 if (np->phy_model == PHY_MODEL_REALTEK_8211 && 1473 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1438 np->phy_rev == PHY_REV_REALTEK_8211B) { 1474 np->phy_rev == PHY_REV_REALTEK_8211B) {
1439 /* reset could have cleared these out, set them back */ 1475 /* reset could have cleared these out, set them back */
1440 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1476 if (init_realtek_8211b(dev, np)) {
1441 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1477 netdev_info(dev, "%s: phy init failed\n",
1478 pci_name(np->pci_dev));
1442 return PHY_ERROR; 1479 return PHY_ERROR;
1443 } 1480 }
1444 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { 1481 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1445 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1482 if (init_realtek_8201(dev, np) ||
1446 return PHY_ERROR; 1483 init_realtek_8201_cross(dev, np)) {
1447 } 1484 netdev_info(dev, "%s: phy init failed\n",
1448 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { 1485 pci_name(np->pci_dev));
1449 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1450 return PHY_ERROR;
1451 }
1452 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1453 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1454 return PHY_ERROR;
1455 }
1456 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1457 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1458 return PHY_ERROR;
1459 }
1460 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1461 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1462 return PHY_ERROR;
1463 }
1464 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1465 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1466 return PHY_ERROR; 1486 return PHY_ERROR;
1467 } 1487 }
1468 } 1488 }
1469 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1470 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1471 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1472 phy_reserved |= PHY_REALTEK_INIT7;
1473 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1474 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1475 return PHY_ERROR;
1476 }
1477 }
1478 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1479 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1480 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1481 return PHY_ERROR;
1482 }
1483 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1484 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1485 phy_reserved |= PHY_REALTEK_INIT3;
1486 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1487 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1488 return PHY_ERROR;
1489 }
1490 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1491 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1492 return PHY_ERROR;
1493 }
1494 }
1495 }
1496 } 1489 }
1497 1490
1498 /* some phys clear out pause advertisment on reset, set it back */ 1491 /* some phys clear out pause advertisement on reset, set it back */
1499 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); 1492 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1500 1493
1501 /* restart auto negotiation, power down phy */ 1494 /* restart auto negotiation, power down phy */
1502 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 1495 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1503 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); 1496 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1504 if (phy_power_down) { 1497 if (phy_power_down)
1505 mii_control |= BMCR_PDOWN; 1498 mii_control |= BMCR_PDOWN;
1506 } 1499 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1507 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1508 return PHY_ERROR; 1500 return PHY_ERROR;
1509 }
1510 1501
1511 return 0; 1502 return 0;
1512} 1503}
@@ -1517,7 +1508,6 @@ static void nv_start_rx(struct net_device *dev)
1517 u8 __iomem *base = get_hwbase(dev); 1508 u8 __iomem *base = get_hwbase(dev);
1518 u32 rx_ctrl = readl(base + NvRegReceiverControl); 1509 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1519 1510
1520 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1521 /* Already running? Stop it. */ 1511 /* Already running? Stop it. */
1522 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { 1512 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1523 rx_ctrl &= ~NVREG_RCVCTL_START; 1513 rx_ctrl &= ~NVREG_RCVCTL_START;
@@ -1526,12 +1516,10 @@ static void nv_start_rx(struct net_device *dev)
1526 } 1516 }
1527 writel(np->linkspeed, base + NvRegLinkSpeed); 1517 writel(np->linkspeed, base + NvRegLinkSpeed);
1528 pci_push(base); 1518 pci_push(base);
1529 rx_ctrl |= NVREG_RCVCTL_START; 1519 rx_ctrl |= NVREG_RCVCTL_START;
1530 if (np->mac_in_use) 1520 if (np->mac_in_use)
1531 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; 1521 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1532 writel(rx_ctrl, base + NvRegReceiverControl); 1522 writel(rx_ctrl, base + NvRegReceiverControl);
1533 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1534 dev->name, np->duplex, np->linkspeed);
1535 pci_push(base); 1523 pci_push(base);
1536} 1524}
1537 1525
@@ -1541,15 +1529,15 @@ static void nv_stop_rx(struct net_device *dev)
1541 u8 __iomem *base = get_hwbase(dev); 1529 u8 __iomem *base = get_hwbase(dev);
1542 u32 rx_ctrl = readl(base + NvRegReceiverControl); 1530 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1543 1531
1544 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1545 if (!np->mac_in_use) 1532 if (!np->mac_in_use)
1546 rx_ctrl &= ~NVREG_RCVCTL_START; 1533 rx_ctrl &= ~NVREG_RCVCTL_START;
1547 else 1534 else
1548 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; 1535 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1549 writel(rx_ctrl, base + NvRegReceiverControl); 1536 writel(rx_ctrl, base + NvRegReceiverControl);
1550 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, 1537 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1551 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, 1538 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1552 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); 1539 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1540 __func__);
1553 1541
1554 udelay(NV_RXSTOP_DELAY2); 1542 udelay(NV_RXSTOP_DELAY2);
1555 if (!np->mac_in_use) 1543 if (!np->mac_in_use)
@@ -1562,7 +1550,6 @@ static void nv_start_tx(struct net_device *dev)
1562 u8 __iomem *base = get_hwbase(dev); 1550 u8 __iomem *base = get_hwbase(dev);
1563 u32 tx_ctrl = readl(base + NvRegTransmitterControl); 1551 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1564 1552
1565 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1566 tx_ctrl |= NVREG_XMITCTL_START; 1553 tx_ctrl |= NVREG_XMITCTL_START;
1567 if (np->mac_in_use) 1554 if (np->mac_in_use)
1568 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; 1555 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
@@ -1576,15 +1563,15 @@ static void nv_stop_tx(struct net_device *dev)
1576 u8 __iomem *base = get_hwbase(dev); 1563 u8 __iomem *base = get_hwbase(dev);
1577 u32 tx_ctrl = readl(base + NvRegTransmitterControl); 1564 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1578 1565
1579 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1580 if (!np->mac_in_use) 1566 if (!np->mac_in_use)
1581 tx_ctrl &= ~NVREG_XMITCTL_START; 1567 tx_ctrl &= ~NVREG_XMITCTL_START;
1582 else 1568 else
1583 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; 1569 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1584 writel(tx_ctrl, base + NvRegTransmitterControl); 1570 writel(tx_ctrl, base + NvRegTransmitterControl);
1585 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, 1571 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1586 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, 1572 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1587 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); 1573 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1574 __func__);
1588 1575
1589 udelay(NV_TXSTOP_DELAY2); 1576 udelay(NV_TXSTOP_DELAY2);
1590 if (!np->mac_in_use) 1577 if (!np->mac_in_use)
@@ -1609,7 +1596,6 @@ static void nv_txrx_reset(struct net_device *dev)
1609 struct fe_priv *np = netdev_priv(dev); 1596 struct fe_priv *np = netdev_priv(dev);
1610 u8 __iomem *base = get_hwbase(dev); 1597 u8 __iomem *base = get_hwbase(dev);
1611 1598
1612 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1613 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); 1599 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1614 pci_push(base); 1600 pci_push(base);
1615 udelay(NV_TXRX_RESET_DELAY); 1601 udelay(NV_TXRX_RESET_DELAY);
@@ -1623,8 +1609,6 @@ static void nv_mac_reset(struct net_device *dev)
1623 u8 __iomem *base = get_hwbase(dev); 1609 u8 __iomem *base = get_hwbase(dev);
1624 u32 temp1, temp2, temp3; 1610 u32 temp1, temp2, temp3;
1625 1611
1626 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1627
1628 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); 1612 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1629 pci_push(base); 1613 pci_push(base);
1630 1614
@@ -1745,7 +1729,7 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev)
1745static int nv_alloc_rx(struct net_device *dev) 1729static int nv_alloc_rx(struct net_device *dev)
1746{ 1730{
1747 struct fe_priv *np = netdev_priv(dev); 1731 struct fe_priv *np = netdev_priv(dev);
1748 struct ring_desc* less_rx; 1732 struct ring_desc *less_rx;
1749 1733
1750 less_rx = np->get_rx.orig; 1734 less_rx = np->get_rx.orig;
1751 if (less_rx-- == np->first_rx.orig) 1735 if (less_rx-- == np->first_rx.orig)
@@ -1767,9 +1751,8 @@ static int nv_alloc_rx(struct net_device *dev)
1767 np->put_rx.orig = np->first_rx.orig; 1751 np->put_rx.orig = np->first_rx.orig;
1768 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) 1752 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1769 np->put_rx_ctx = np->first_rx_ctx; 1753 np->put_rx_ctx = np->first_rx_ctx;
1770 } else { 1754 } else
1771 return 1; 1755 return 1;
1772 }
1773 } 1756 }
1774 return 0; 1757 return 0;
1775} 1758}
@@ -1777,7 +1760,7 @@ static int nv_alloc_rx(struct net_device *dev)
1777static int nv_alloc_rx_optimized(struct net_device *dev) 1760static int nv_alloc_rx_optimized(struct net_device *dev)
1778{ 1761{
1779 struct fe_priv *np = netdev_priv(dev); 1762 struct fe_priv *np = netdev_priv(dev);
1780 struct ring_desc_ex* less_rx; 1763 struct ring_desc_ex *less_rx;
1781 1764
1782 less_rx = np->get_rx.ex; 1765 less_rx = np->get_rx.ex;
1783 if (less_rx-- == np->first_rx.ex) 1766 if (less_rx-- == np->first_rx.ex)
@@ -1800,9 +1783,8 @@ static int nv_alloc_rx_optimized(struct net_device *dev)
1800 np->put_rx.ex = np->first_rx.ex; 1783 np->put_rx.ex = np->first_rx.ex;
1801 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) 1784 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1802 np->put_rx_ctx = np->first_rx_ctx; 1785 np->put_rx_ctx = np->first_rx_ctx;
1803 } else { 1786 } else
1804 return 1; 1787 return 1;
1805 }
1806 } 1788 }
1807 return 0; 1789 return 0;
1808} 1790}
@@ -2018,24 +2000,24 @@ static void nv_legacybackoff_reseed(struct net_device *dev)
2018 2000
2019/* Known Good seed sets */ 2001/* Known Good seed sets */
2020static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { 2002static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2021 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, 2003 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2022 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, 2004 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2023 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, 2005 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2024 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, 2006 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2025 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, 2007 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2026 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, 2008 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2027 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, 2009 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2028 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}}; 2010 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2029 2011
2030static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { 2012static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2031 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, 2013 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2032 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, 2014 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2033 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, 2015 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2034 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, 2016 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2035 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, 2017 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2036 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, 2018 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2037 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, 2019 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2038 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}}; 2020 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2039 2021
2040static void nv_gear_backoff_reseed(struct net_device *dev) 2022static void nv_gear_backoff_reseed(struct net_device *dev)
2041{ 2023{
@@ -2083,13 +2065,12 @@ static void nv_gear_backoff_reseed(struct net_device *dev)
2083 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); 2065 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2084 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; 2066 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2085 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; 2067 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2086 writel(temp,base + NvRegBackOffControl); 2068 writel(temp, base + NvRegBackOffControl);
2087 2069
2088 /* Setup seeds for all gear LFSRs. */ 2070 /* Setup seeds for all gear LFSRs. */
2089 get_random_bytes(&seedset, sizeof(seedset)); 2071 get_random_bytes(&seedset, sizeof(seedset));
2090 seedset = seedset % BACKOFF_SEEDSET_ROWS; 2072 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2091 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) 2073 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2092 {
2093 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); 2074 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2094 temp |= main_seedset[seedset][i-1] & 0x3ff; 2075 temp |= main_seedset[seedset][i-1] & 0x3ff;
2095 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); 2076 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
@@ -2113,10 +2094,10 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2113 u32 size = skb_headlen(skb); 2094 u32 size = skb_headlen(skb);
2114 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); 2095 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2115 u32 empty_slots; 2096 u32 empty_slots;
2116 struct ring_desc* put_tx; 2097 struct ring_desc *put_tx;
2117 struct ring_desc* start_tx; 2098 struct ring_desc *start_tx;
2118 struct ring_desc* prev_tx; 2099 struct ring_desc *prev_tx;
2119 struct nv_skb_map* prev_tx_ctx; 2100 struct nv_skb_map *prev_tx_ctx;
2120 unsigned long flags; 2101 unsigned long flags;
2121 2102
2122 /* add fragments to entries count */ 2103 /* add fragments to entries count */
@@ -2204,18 +2185,6 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2204 2185
2205 spin_unlock_irqrestore(&np->lock, flags); 2186 spin_unlock_irqrestore(&np->lock, flags);
2206 2187
2207 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2208 dev->name, entries, tx_flags_extra);
2209 {
2210 int j;
2211 for (j=0; j<64; j++) {
2212 if ((j%16) == 0)
2213 dprintk("\n%03x:", j);
2214 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2215 }
2216 dprintk("\n");
2217 }
2218
2219 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); 2188 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2220 return NETDEV_TX_OK; 2189 return NETDEV_TX_OK;
2221} 2190}
@@ -2233,11 +2202,11 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2233 u32 size = skb_headlen(skb); 2202 u32 size = skb_headlen(skb);
2234 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); 2203 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2235 u32 empty_slots; 2204 u32 empty_slots;
2236 struct ring_desc_ex* put_tx; 2205 struct ring_desc_ex *put_tx;
2237 struct ring_desc_ex* start_tx; 2206 struct ring_desc_ex *start_tx;
2238 struct ring_desc_ex* prev_tx; 2207 struct ring_desc_ex *prev_tx;
2239 struct nv_skb_map* prev_tx_ctx; 2208 struct nv_skb_map *prev_tx_ctx;
2240 struct nv_skb_map* start_tx_ctx; 2209 struct nv_skb_map *start_tx_ctx;
2241 unsigned long flags; 2210 unsigned long flags;
2242 2211
2243 /* add fragments to entries count */ 2212 /* add fragments to entries count */
@@ -2321,14 +2290,11 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2321 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; 2290 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2322 2291
2323 /* vlan tag */ 2292 /* vlan tag */
2324 if (likely(!np->vlangrp)) { 2293 if (vlan_tx_tag_present(skb))
2294 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2295 vlan_tx_tag_get(skb));
2296 else
2325 start_tx->txvlan = 0; 2297 start_tx->txvlan = 0;
2326 } else {
2327 if (vlan_tx_tag_present(skb))
2328 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2329 else
2330 start_tx->txvlan = 0;
2331 }
2332 2298
2333 spin_lock_irqsave(&np->lock, flags); 2299 spin_lock_irqsave(&np->lock, flags);
2334 2300
@@ -2358,18 +2324,6 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2358 2324
2359 spin_unlock_irqrestore(&np->lock, flags); 2325 spin_unlock_irqrestore(&np->lock, flags);
2360 2326
2361 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2362 dev->name, entries, tx_flags_extra);
2363 {
2364 int j;
2365 for (j=0; j<64; j++) {
2366 if ((j%16) == 0)
2367 dprintk("\n%03x:", j);
2368 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2369 }
2370 dprintk("\n");
2371 }
2372
2373 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); 2327 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2374 return NETDEV_TX_OK; 2328 return NETDEV_TX_OK;
2375} 2329}
@@ -2402,15 +2356,12 @@ static int nv_tx_done(struct net_device *dev, int limit)
2402 struct fe_priv *np = netdev_priv(dev); 2356 struct fe_priv *np = netdev_priv(dev);
2403 u32 flags; 2357 u32 flags;
2404 int tx_work = 0; 2358 int tx_work = 0;
2405 struct ring_desc* orig_get_tx = np->get_tx.orig; 2359 struct ring_desc *orig_get_tx = np->get_tx.orig;
2406 2360
2407 while ((np->get_tx.orig != np->put_tx.orig) && 2361 while ((np->get_tx.orig != np->put_tx.orig) &&
2408 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && 2362 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2409 (tx_work < limit)) { 2363 (tx_work < limit)) {
2410 2364
2411 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2412 dev->name, flags);
2413
2414 nv_unmap_txskb(np, np->get_tx_ctx); 2365 nv_unmap_txskb(np, np->get_tx_ctx);
2415 2366
2416 if (np->desc_ver == DESC_VER_1) { 2367 if (np->desc_ver == DESC_VER_1) {
@@ -2467,15 +2418,12 @@ static int nv_tx_done_optimized(struct net_device *dev, int limit)
2467 struct fe_priv *np = netdev_priv(dev); 2418 struct fe_priv *np = netdev_priv(dev);
2468 u32 flags; 2419 u32 flags;
2469 int tx_work = 0; 2420 int tx_work = 0;
2470 struct ring_desc_ex* orig_get_tx = np->get_tx.ex; 2421 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2471 2422
2472 while ((np->get_tx.ex != np->put_tx.ex) && 2423 while ((np->get_tx.ex != np->put_tx.ex) &&
2473 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && 2424 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2474 (tx_work < limit)) { 2425 (tx_work < limit)) {
2475 2426
2476 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2477 dev->name, flags);
2478
2479 nv_unmap_txskb(np, np->get_tx_ctx); 2427 nv_unmap_txskb(np, np->get_tx_ctx);
2480 2428
2481 if (flags & NV_TX2_LASTPACKET) { 2429 if (flags & NV_TX2_LASTPACKET) {
@@ -2494,9 +2442,8 @@ static int nv_tx_done_optimized(struct net_device *dev, int limit)
2494 np->get_tx_ctx->skb = NULL; 2442 np->get_tx_ctx->skb = NULL;
2495 tx_work++; 2443 tx_work++;
2496 2444
2497 if (np->tx_limit) { 2445 if (np->tx_limit)
2498 nv_tx_flip_ownership(dev); 2446 nv_tx_flip_ownership(dev);
2499 }
2500 } 2447 }
2501 if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) 2448 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2502 np->get_tx.ex = np->first_tx.ex; 2449 np->get_tx.ex = np->first_tx.ex;
@@ -2521,57 +2468,56 @@ static void nv_tx_timeout(struct net_device *dev)
2521 u32 status; 2468 u32 status;
2522 union ring_type put_tx; 2469 union ring_type put_tx;
2523 int saved_tx_limit; 2470 int saved_tx_limit;
2471 int i;
2524 2472
2525 if (np->msi_flags & NV_MSI_X_ENABLED) 2473 if (np->msi_flags & NV_MSI_X_ENABLED)
2526 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; 2474 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2527 else 2475 else
2528 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; 2476 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2529 2477
2530 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); 2478 netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
2531 2479
2532 { 2480 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2533 int i; 2481 netdev_info(dev, "Dumping tx registers\n");
2534 2482 for (i = 0; i <= np->register_size; i += 32) {
2535 printk(KERN_INFO "%s: Ring at %lx\n", 2483 netdev_info(dev,
2536 dev->name, (unsigned long)np->ring_addr); 2484 "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2537 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); 2485 i,
2538 for (i=0;i<=np->register_size;i+= 32) { 2486 readl(base + i + 0), readl(base + i + 4),
2539 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", 2487 readl(base + i + 8), readl(base + i + 12),
2540 i, 2488 readl(base + i + 16), readl(base + i + 20),
2541 readl(base + i + 0), readl(base + i + 4), 2489 readl(base + i + 24), readl(base + i + 28));
2542 readl(base + i + 8), readl(base + i + 12), 2490 }
2543 readl(base + i + 16), readl(base + i + 20), 2491 netdev_info(dev, "Dumping tx ring\n");
2544 readl(base + i + 24), readl(base + i + 28)); 2492 for (i = 0; i < np->tx_ring_size; i += 4) {
2545 } 2493 if (!nv_optimized(np)) {
2546 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); 2494 netdev_info(dev,
2547 for (i=0;i<np->tx_ring_size;i+= 4) { 2495 "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2548 if (!nv_optimized(np)) { 2496 i,
2549 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", 2497 le32_to_cpu(np->tx_ring.orig[i].buf),
2550 i, 2498 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2551 le32_to_cpu(np->tx_ring.orig[i].buf), 2499 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2552 le32_to_cpu(np->tx_ring.orig[i].flaglen), 2500 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2553 le32_to_cpu(np->tx_ring.orig[i+1].buf), 2501 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2554 le32_to_cpu(np->tx_ring.orig[i+1].flaglen), 2502 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2555 le32_to_cpu(np->tx_ring.orig[i+2].buf), 2503 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2556 le32_to_cpu(np->tx_ring.orig[i+2].flaglen), 2504 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2557 le32_to_cpu(np->tx_ring.orig[i+3].buf), 2505 } else {
2558 le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); 2506 netdev_info(dev,
2559 } else { 2507 "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2560 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", 2508 i,
2561 i, 2509 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2562 le32_to_cpu(np->tx_ring.ex[i].bufhigh), 2510 le32_to_cpu(np->tx_ring.ex[i].buflow),
2563 le32_to_cpu(np->tx_ring.ex[i].buflow), 2511 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2564 le32_to_cpu(np->tx_ring.ex[i].flaglen), 2512 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2565 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), 2513 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2566 le32_to_cpu(np->tx_ring.ex[i+1].buflow), 2514 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2567 le32_to_cpu(np->tx_ring.ex[i+1].flaglen), 2515 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2568 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), 2516 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2569 le32_to_cpu(np->tx_ring.ex[i+2].buflow), 2517 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2570 le32_to_cpu(np->tx_ring.ex[i+2].flaglen), 2518 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2571 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), 2519 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2572 le32_to_cpu(np->tx_ring.ex[i+3].buflow), 2520 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2573 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2574 }
2575 } 2521 }
2576 } 2522 }
2577 2523
@@ -2589,7 +2535,7 @@ static void nv_tx_timeout(struct net_device *dev)
2589 else 2535 else
2590 nv_tx_done_optimized(dev, np->tx_ring_size); 2536 nv_tx_done_optimized(dev, np->tx_ring_size);
2591 2537
2592 /* save current HW postion */ 2538 /* save current HW position */
2593 if (np->tx_change_owner) 2539 if (np->tx_change_owner)
2594 put_tx.ex = np->tx_change_owner->first_tx_desc; 2540 put_tx.ex = np->tx_change_owner->first_tx_desc;
2595 else 2541 else
@@ -2619,15 +2565,13 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2619 int protolen; /* length as stored in the proto field */ 2565 int protolen; /* length as stored in the proto field */
2620 2566
2621 /* 1) calculate len according to header */ 2567 /* 1) calculate len according to header */
2622 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { 2568 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2623 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); 2569 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2624 hdrlen = VLAN_HLEN; 2570 hdrlen = VLAN_HLEN;
2625 } else { 2571 } else {
2626 protolen = ntohs( ((struct ethhdr *)packet)->h_proto); 2572 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2627 hdrlen = ETH_HLEN; 2573 hdrlen = ETH_HLEN;
2628 } 2574 }
2629 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2630 dev->name, datalen, protolen, hdrlen);
2631 if (protolen > ETH_DATA_LEN) 2575 if (protolen > ETH_DATA_LEN)
2632 return datalen; /* Value in proto field not a len, no checks possible */ 2576 return datalen; /* Value in proto field not a len, no checks possible */
2633 2577
@@ -2638,26 +2582,18 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2638 /* more data on wire than in 802 header, trim of 2582 /* more data on wire than in 802 header, trim of
2639 * additional data. 2583 * additional data.
2640 */ 2584 */
2641 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2642 dev->name, protolen);
2643 return protolen; 2585 return protolen;
2644 } else { 2586 } else {
2645 /* less data on wire than mentioned in header. 2587 /* less data on wire than mentioned in header.
2646 * Discard the packet. 2588 * Discard the packet.
2647 */ 2589 */
2648 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2649 dev->name);
2650 return -1; 2590 return -1;
2651 } 2591 }
2652 } else { 2592 } else {
2653 /* short packet. Accept only if 802 values are also short */ 2593 /* short packet. Accept only if 802 values are also short */
2654 if (protolen > ETH_ZLEN) { 2594 if (protolen > ETH_ZLEN) {
2655 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2656 dev->name);
2657 return -1; 2595 return -1;
2658 } 2596 }
2659 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2660 dev->name, datalen);
2661 return datalen; 2597 return datalen;
2662 } 2598 }
2663} 2599}
@@ -2670,13 +2606,10 @@ static int nv_rx_process(struct net_device *dev, int limit)
2670 struct sk_buff *skb; 2606 struct sk_buff *skb;
2671 int len; 2607 int len;
2672 2608
2673 while((np->get_rx.orig != np->put_rx.orig) && 2609 while ((np->get_rx.orig != np->put_rx.orig) &&
2674 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && 2610 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2675 (rx_work < limit)) { 2611 (rx_work < limit)) {
2676 2612
2677 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2678 dev->name, flags);
2679
2680 /* 2613 /*
2681 * the packet is for us - immediately tear down the pci mapping. 2614 * the packet is for us - immediately tear down the pci mapping.
2682 * TODO: check if a prefetch of the first cacheline improves 2615 * TODO: check if a prefetch of the first cacheline improves
@@ -2688,16 +2621,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
2688 skb = np->get_rx_ctx->skb; 2621 skb = np->get_rx_ctx->skb;
2689 np->get_rx_ctx->skb = NULL; 2622 np->get_rx_ctx->skb = NULL;
2690 2623
2691 {
2692 int j;
2693 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2694 for (j=0; j<64; j++) {
2695 if ((j%16) == 0)
2696 dprintk("\n%03x:", j);
2697 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2698 }
2699 dprintk("\n");
2700 }
2701 /* look at what we actually got: */ 2624 /* look at what we actually got: */
2702 if (np->desc_ver == DESC_VER_1) { 2625 if (np->desc_ver == DESC_VER_1) {
2703 if (likely(flags & NV_RX_DESCRIPTORVALID)) { 2626 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
@@ -2713,9 +2636,8 @@ static int nv_rx_process(struct net_device *dev, int limit)
2713 } 2636 }
2714 /* framing errors are soft errors */ 2637 /* framing errors are soft errors */
2715 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { 2638 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2716 if (flags & NV_RX_SUBSTRACT1) { 2639 if (flags & NV_RX_SUBSTRACT1)
2717 len--; 2640 len--;
2718 }
2719 } 2641 }
2720 /* the rest are hard errors */ 2642 /* the rest are hard errors */
2721 else { 2643 else {
@@ -2748,9 +2670,8 @@ static int nv_rx_process(struct net_device *dev, int limit)
2748 } 2670 }
2749 /* framing errors are soft errors */ 2671 /* framing errors are soft errors */
2750 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { 2672 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2751 if (flags & NV_RX2_SUBSTRACT1) { 2673 if (flags & NV_RX2_SUBSTRACT1)
2752 len--; 2674 len--;
2753 }
2754 } 2675 }
2755 /* the rest are hard errors */ 2676 /* the rest are hard errors */
2756 else { 2677 else {
@@ -2774,8 +2695,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
2774 /* got a valid packet - forward it to the network core */ 2695 /* got a valid packet - forward it to the network core */
2775 skb_put(skb, len); 2696 skb_put(skb, len);
2776 skb->protocol = eth_type_trans(skb, dev); 2697 skb->protocol = eth_type_trans(skb, dev);
2777 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2778 dev->name, len, skb->protocol);
2779 napi_gro_receive(&np->napi, skb); 2698 napi_gro_receive(&np->napi, skb);
2780 dev->stats.rx_packets++; 2699 dev->stats.rx_packets++;
2781 dev->stats.rx_bytes += len; 2700 dev->stats.rx_bytes += len;
@@ -2800,13 +2719,10 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
2800 struct sk_buff *skb; 2719 struct sk_buff *skb;
2801 int len; 2720 int len;
2802 2721
2803 while((np->get_rx.ex != np->put_rx.ex) && 2722 while ((np->get_rx.ex != np->put_rx.ex) &&
2804 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && 2723 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2805 (rx_work < limit)) { 2724 (rx_work < limit)) {
2806 2725
2807 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2808 dev->name, flags);
2809
2810 /* 2726 /*
2811 * the packet is for us - immediately tear down the pci mapping. 2727 * the packet is for us - immediately tear down the pci mapping.
2812 * TODO: check if a prefetch of the first cacheline improves 2728 * TODO: check if a prefetch of the first cacheline improves
@@ -2818,16 +2734,6 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
2818 skb = np->get_rx_ctx->skb; 2734 skb = np->get_rx_ctx->skb;
2819 np->get_rx_ctx->skb = NULL; 2735 np->get_rx_ctx->skb = NULL;
2820 2736
2821 {
2822 int j;
2823 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2824 for (j=0; j<64; j++) {
2825 if ((j%16) == 0)
2826 dprintk("\n%03x:", j);
2827 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2828 }
2829 dprintk("\n");
2830 }
2831 /* look at what we actually got: */ 2737 /* look at what we actually got: */
2832 if (likely(flags & NV_RX2_DESCRIPTORVALID)) { 2738 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2833 len = flags & LEN_MASK_V2; 2739 len = flags & LEN_MASK_V2;
@@ -2841,9 +2747,8 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
2841 } 2747 }
2842 /* framing errors are soft errors */ 2748 /* framing errors are soft errors */
2843 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { 2749 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2844 if (flags & NV_RX2_SUBSTRACT1) { 2750 if (flags & NV_RX2_SUBSTRACT1)
2845 len--; 2751 len--;
2846 }
2847 } 2752 }
2848 /* the rest are hard errors */ 2753 /* the rest are hard errors */
2849 else { 2754 else {
@@ -2861,9 +2766,6 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
2861 skb->protocol = eth_type_trans(skb, dev); 2766 skb->protocol = eth_type_trans(skb, dev);
2862 prefetch(skb->data); 2767 prefetch(skb->data);
2863 2768
2864 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2865 dev->name, len, skb->protocol);
2866
2867 if (likely(!np->vlangrp)) { 2769 if (likely(!np->vlangrp)) {
2868 napi_gro_receive(&np->napi, skb); 2770 napi_gro_receive(&np->napi, skb);
2869 } else { 2771 } else {
@@ -2952,7 +2854,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
2952 /* reinit nic view of the rx queue */ 2854 /* reinit nic view of the rx queue */
2953 writel(np->rx_buf_sz, base + NvRegOffloadConfig); 2855 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2954 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); 2856 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2955 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), 2857 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2956 base + NvRegRingSizes); 2858 base + NvRegRingSizes);
2957 pci_push(base); 2859 pci_push(base);
2958 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); 2860 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
@@ -2989,7 +2891,7 @@ static void nv_copy_mac_to_hw(struct net_device *dev)
2989static int nv_set_mac_address(struct net_device *dev, void *addr) 2891static int nv_set_mac_address(struct net_device *dev, void *addr)
2990{ 2892{
2991 struct fe_priv *np = netdev_priv(dev); 2893 struct fe_priv *np = netdev_priv(dev);
2992 struct sockaddr *macaddr = (struct sockaddr*)addr; 2894 struct sockaddr *macaddr = (struct sockaddr *)addr;
2993 2895
2994 if (!is_valid_ether_addr(macaddr->sa_data)) 2896 if (!is_valid_ether_addr(macaddr->sa_data))
2995 return -EADDRNOTAVAIL; 2897 return -EADDRNOTAVAIL;
@@ -3079,8 +2981,6 @@ static void nv_set_multicast(struct net_device *dev)
3079 writel(mask[0], base + NvRegMulticastMaskA); 2981 writel(mask[0], base + NvRegMulticastMaskA);
3080 writel(mask[1], base + NvRegMulticastMaskB); 2982 writel(mask[1], base + NvRegMulticastMaskB);
3081 writel(pff, base + NvRegPacketFilterFlags); 2983 writel(pff, base + NvRegPacketFilterFlags);
3082 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3083 dev->name);
3084 nv_start_rx(dev); 2984 nv_start_rx(dev);
3085 spin_unlock_irq(&np->lock); 2985 spin_unlock_irq(&np->lock);
3086} 2986}
@@ -3155,8 +3055,6 @@ static int nv_update_linkspeed(struct net_device *dev)
3155 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); 3055 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3156 3056
3157 if (!(mii_status & BMSR_LSTATUS)) { 3057 if (!(mii_status & BMSR_LSTATUS)) {
3158 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3159 dev->name);
3160 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; 3058 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3161 newdup = 0; 3059 newdup = 0;
3162 retval = 0; 3060 retval = 0;
@@ -3164,8 +3062,6 @@ static int nv_update_linkspeed(struct net_device *dev)
3164 } 3062 }
3165 3063
3166 if (np->autoneg == 0) { 3064 if (np->autoneg == 0) {
3167 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3168 dev->name, np->fixed_mode);
3169 if (np->fixed_mode & LPA_100FULL) { 3065 if (np->fixed_mode & LPA_100FULL) {
3170 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; 3066 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3171 newdup = 1; 3067 newdup = 1;
@@ -3188,14 +3084,11 @@ static int nv_update_linkspeed(struct net_device *dev)
3188 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; 3084 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3189 newdup = 0; 3085 newdup = 0;
3190 retval = 0; 3086 retval = 0;
3191 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3192 goto set_speed; 3087 goto set_speed;
3193 } 3088 }
3194 3089
3195 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); 3090 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3196 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); 3091 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3197 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3198 dev->name, adv, lpa);
3199 3092
3200 retval = 1; 3093 retval = 1;
3201 if (np->gigabit == PHY_GIGABIT) { 3094 if (np->gigabit == PHY_GIGABIT) {
@@ -3204,8 +3097,6 @@ static int nv_update_linkspeed(struct net_device *dev)
3204 3097
3205 if ((control_1000 & ADVERTISE_1000FULL) && 3098 if ((control_1000 & ADVERTISE_1000FULL) &&
3206 (status_1000 & LPA_1000FULL)) { 3099 (status_1000 & LPA_1000FULL)) {
3207 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3208 dev->name);
3209 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; 3100 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3210 newdup = 1; 3101 newdup = 1;
3211 goto set_speed; 3102 goto set_speed;
@@ -3227,7 +3118,6 @@ static int nv_update_linkspeed(struct net_device *dev)
3227 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; 3118 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3228 newdup = 0; 3119 newdup = 0;
3229 } else { 3120 } else {
3230 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3231 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; 3121 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3232 newdup = 0; 3122 newdup = 0;
3233 } 3123 }
@@ -3236,9 +3126,6 @@ set_speed:
3236 if (np->duplex == newdup && np->linkspeed == newls) 3126 if (np->duplex == newdup && np->linkspeed == newls)
3237 return retval; 3127 return retval;
3238 3128
3239 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3240 dev->name, np->linkspeed, np->duplex, newls, newdup);
3241
3242 np->duplex = newdup; 3129 np->duplex = newdup;
3243 np->linkspeed = newls; 3130 np->linkspeed = newls;
3244 3131
@@ -3305,7 +3192,7 @@ set_speed:
3305 } 3192 }
3306 writel(txreg, base + NvRegTxWatermark); 3193 writel(txreg, base + NvRegTxWatermark);
3307 3194
3308 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), 3195 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3309 base + NvRegMisc1); 3196 base + NvRegMisc1);
3310 pci_push(base); 3197 pci_push(base);
3311 writel(np->linkspeed, base + NvRegLinkSpeed); 3198 writel(np->linkspeed, base + NvRegLinkSpeed);
@@ -3315,8 +3202,8 @@ set_speed:
3315 /* setup pause frame */ 3202 /* setup pause frame */
3316 if (np->duplex != 0) { 3203 if (np->duplex != 0) {
3317 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { 3204 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3318 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM); 3205 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3319 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM); 3206 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3320 3207
3321 switch (adv_pause) { 3208 switch (adv_pause) {
3322 case ADVERTISE_PAUSE_CAP: 3209 case ADVERTISE_PAUSE_CAP:
@@ -3327,22 +3214,17 @@ set_speed:
3327 } 3214 }
3328 break; 3215 break;
3329 case ADVERTISE_PAUSE_ASYM: 3216 case ADVERTISE_PAUSE_ASYM:
3330 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM)) 3217 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3331 {
3332 pause_flags |= NV_PAUSEFRAME_TX_ENABLE; 3218 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3333 }
3334 break; 3219 break;
3335 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM: 3220 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3336 if (lpa_pause & LPA_PAUSE_CAP) 3221 if (lpa_pause & LPA_PAUSE_CAP) {
3337 {
3338 pause_flags |= NV_PAUSEFRAME_RX_ENABLE; 3222 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3339 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) 3223 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3340 pause_flags |= NV_PAUSEFRAME_TX_ENABLE; 3224 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3341 } 3225 }
3342 if (lpa_pause == LPA_PAUSE_ASYM) 3226 if (lpa_pause == LPA_PAUSE_ASYM)
3343 {
3344 pause_flags |= NV_PAUSEFRAME_RX_ENABLE; 3227 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3345 }
3346 break; 3228 break;
3347 } 3229 }
3348 } else { 3230 } else {
@@ -3364,14 +3246,14 @@ static void nv_linkchange(struct net_device *dev)
3364 if (nv_update_linkspeed(dev)) { 3246 if (nv_update_linkspeed(dev)) {
3365 if (!netif_carrier_ok(dev)) { 3247 if (!netif_carrier_ok(dev)) {
3366 netif_carrier_on(dev); 3248 netif_carrier_on(dev);
3367 printk(KERN_INFO "%s: link up.\n", dev->name); 3249 netdev_info(dev, "link up\n");
3368 nv_txrx_gate(dev, false); 3250 nv_txrx_gate(dev, false);
3369 nv_start_rx(dev); 3251 nv_start_rx(dev);
3370 } 3252 }
3371 } else { 3253 } else {
3372 if (netif_carrier_ok(dev)) { 3254 if (netif_carrier_ok(dev)) {
3373 netif_carrier_off(dev); 3255 netif_carrier_off(dev);
3374 printk(KERN_INFO "%s: link down.\n", dev->name); 3256 netdev_info(dev, "link down\n");
3375 nv_txrx_gate(dev, true); 3257 nv_txrx_gate(dev, true);
3376 nv_stop_rx(dev); 3258 nv_stop_rx(dev);
3377 } 3259 }
@@ -3385,11 +3267,9 @@ static void nv_link_irq(struct net_device *dev)
3385 3267
3386 miistat = readl(base + NvRegMIIStatus); 3268 miistat = readl(base + NvRegMIIStatus);
3387 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); 3269 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3388 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3389 3270
3390 if (miistat & (NVREG_MIISTAT_LINKCHANGE)) 3271 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3391 nv_linkchange(dev); 3272 nv_linkchange(dev);
3392 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3393} 3273}
3394 3274
3395static void nv_msi_workaround(struct fe_priv *np) 3275static void nv_msi_workaround(struct fe_priv *np)
@@ -3440,8 +3320,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
3440 struct fe_priv *np = netdev_priv(dev); 3320 struct fe_priv *np = netdev_priv(dev);
3441 u8 __iomem *base = get_hwbase(dev); 3321 u8 __iomem *base = get_hwbase(dev);
3442 3322
3443 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3444
3445 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { 3323 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3446 np->events = readl(base + NvRegIrqStatus); 3324 np->events = readl(base + NvRegIrqStatus);
3447 writel(np->events, base + NvRegIrqStatus); 3325 writel(np->events, base + NvRegIrqStatus);
@@ -3449,7 +3327,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
3449 np->events = readl(base + NvRegMSIXIrqStatus); 3327 np->events = readl(base + NvRegMSIXIrqStatus);
3450 writel(np->events, base + NvRegMSIXIrqStatus); 3328 writel(np->events, base + NvRegMSIXIrqStatus);
3451 } 3329 }
3452 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3453 if (!(np->events & np->irqmask)) 3330 if (!(np->events & np->irqmask))
3454 return IRQ_NONE; 3331 return IRQ_NONE;
3455 3332
@@ -3463,8 +3340,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
3463 __napi_schedule(&np->napi); 3340 __napi_schedule(&np->napi);
3464 } 3341 }
3465 3342
3466 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3467
3468 return IRQ_HANDLED; 3343 return IRQ_HANDLED;
3469} 3344}
3470 3345
@@ -3479,8 +3354,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3479 struct fe_priv *np = netdev_priv(dev); 3354 struct fe_priv *np = netdev_priv(dev);
3480 u8 __iomem *base = get_hwbase(dev); 3355 u8 __iomem *base = get_hwbase(dev);
3481 3356
3482 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3483
3484 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { 3357 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3485 np->events = readl(base + NvRegIrqStatus); 3358 np->events = readl(base + NvRegIrqStatus);
3486 writel(np->events, base + NvRegIrqStatus); 3359 writel(np->events, base + NvRegIrqStatus);
@@ -3488,7 +3361,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3488 np->events = readl(base + NvRegMSIXIrqStatus); 3361 np->events = readl(base + NvRegMSIXIrqStatus);
3489 writel(np->events, base + NvRegMSIXIrqStatus); 3362 writel(np->events, base + NvRegMSIXIrqStatus);
3490 } 3363 }
3491 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3492 if (!(np->events & np->irqmask)) 3364 if (!(np->events & np->irqmask))
3493 return IRQ_NONE; 3365 return IRQ_NONE;
3494 3366
@@ -3501,7 +3373,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3501 writel(0, base + NvRegIrqMask); 3373 writel(0, base + NvRegIrqMask);
3502 __napi_schedule(&np->napi); 3374 __napi_schedule(&np->napi);
3503 } 3375 }
3504 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3505 3376
3506 return IRQ_HANDLED; 3377 return IRQ_HANDLED;
3507} 3378}
@@ -3515,12 +3386,9 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3515 int i; 3386 int i;
3516 unsigned long flags; 3387 unsigned long flags;
3517 3388
3518 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); 3389 for (i = 0;; i++) {
3519
3520 for (i=0; ; i++) {
3521 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; 3390 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3522 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); 3391 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3523 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3524 if (!(events & np->irqmask)) 3392 if (!(events & np->irqmask))
3525 break; 3393 break;
3526 3394
@@ -3539,12 +3407,12 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3539 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); 3407 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3540 } 3408 }
3541 spin_unlock_irqrestore(&np->lock, flags); 3409 spin_unlock_irqrestore(&np->lock, flags);
3542 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); 3410 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3411 __func__, i);
3543 break; 3412 break;
3544 } 3413 }
3545 3414
3546 } 3415 }
3547 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3548 3416
3549 return IRQ_RETVAL(i); 3417 return IRQ_RETVAL(i);
3550} 3418}
@@ -3556,7 +3424,7 @@ static int nv_napi_poll(struct napi_struct *napi, int budget)
3556 u8 __iomem *base = get_hwbase(dev); 3424 u8 __iomem *base = get_hwbase(dev);
3557 unsigned long flags; 3425 unsigned long flags;
3558 int retcode; 3426 int retcode;
3559 int rx_count, tx_work=0, rx_work=0; 3427 int rx_count, tx_work = 0, rx_work = 0;
3560 3428
3561 do { 3429 do {
3562 if (!nv_optimized(np)) { 3430 if (!nv_optimized(np)) {
@@ -3629,12 +3497,9 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3629 int i; 3497 int i;
3630 unsigned long flags; 3498 unsigned long flags;
3631 3499
3632 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); 3500 for (i = 0;; i++) {
3633
3634 for (i=0; ; i++) {
3635 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; 3501 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3636 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); 3502 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3637 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3638 if (!(events & np->irqmask)) 3503 if (!(events & np->irqmask))
3639 break; 3504 break;
3640 3505
@@ -3658,11 +3523,11 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3658 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); 3523 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3659 } 3524 }
3660 spin_unlock_irqrestore(&np->lock, flags); 3525 spin_unlock_irqrestore(&np->lock, flags);
3661 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); 3526 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3527 __func__, i);
3662 break; 3528 break;
3663 } 3529 }
3664 } 3530 }
3665 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3666 3531
3667 return IRQ_RETVAL(i); 3532 return IRQ_RETVAL(i);
3668} 3533}
@@ -3676,12 +3541,9 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data)
3676 int i; 3541 int i;
3677 unsigned long flags; 3542 unsigned long flags;
3678 3543
3679 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); 3544 for (i = 0;; i++) {
3680
3681 for (i=0; ; i++) {
3682 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; 3545 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3683 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); 3546 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3684 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3685 if (!(events & np->irqmask)) 3547 if (!(events & np->irqmask))
3686 break; 3548 break;
3687 3549
@@ -3726,12 +3588,12 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data)
3726 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); 3588 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3727 } 3589 }
3728 spin_unlock_irqrestore(&np->lock, flags); 3590 spin_unlock_irqrestore(&np->lock, flags);
3729 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); 3591 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3592 __func__, i);
3730 break; 3593 break;
3731 } 3594 }
3732 3595
3733 } 3596 }
3734 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3735 3597
3736 return IRQ_RETVAL(i); 3598 return IRQ_RETVAL(i);
3737} 3599}
@@ -3743,8 +3605,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data)
3743 u8 __iomem *base = get_hwbase(dev); 3605 u8 __iomem *base = get_hwbase(dev);
3744 u32 events; 3606 u32 events;
3745 3607
3746 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3747
3748 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { 3608 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3749 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; 3609 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3750 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); 3610 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
@@ -3753,7 +3613,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data)
3753 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); 3613 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3754 } 3614 }
3755 pci_push(base); 3615 pci_push(base);
3756 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3757 if (!(events & NVREG_IRQ_TIMER)) 3616 if (!(events & NVREG_IRQ_TIMER))
3758 return IRQ_RETVAL(0); 3617 return IRQ_RETVAL(0);
3759 3618
@@ -3763,8 +3622,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data)
3763 np->intr_test = 1; 3622 np->intr_test = 1;
3764 spin_unlock(&np->lock); 3623 spin_unlock(&np->lock);
3765 3624
3766 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3767
3768 return IRQ_RETVAL(1); 3625 return IRQ_RETVAL(1);
3769} 3626}
3770 3627
@@ -3779,17 +3636,15 @@ static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3779 * the remaining 8 interrupts. 3636 * the remaining 8 interrupts.
3780 */ 3637 */
3781 for (i = 0; i < 8; i++) { 3638 for (i = 0; i < 8; i++) {
3782 if ((irqmask >> i) & 0x1) { 3639 if ((irqmask >> i) & 0x1)
3783 msixmap |= vector << (i << 2); 3640 msixmap |= vector << (i << 2);
3784 }
3785 } 3641 }
3786 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); 3642 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3787 3643
3788 msixmap = 0; 3644 msixmap = 0;
3789 for (i = 0; i < 8; i++) { 3645 for (i = 0; i < 8; i++) {
3790 if ((irqmask >> (i + 8)) & 0x1) { 3646 if ((irqmask >> (i + 8)) & 0x1)
3791 msixmap |= vector << (i << 2); 3647 msixmap |= vector << (i << 2);
3792 }
3793 } 3648 }
3794 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); 3649 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3795} 3650}
@@ -3812,17 +3667,19 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3812 } 3667 }
3813 3668
3814 if (np->msi_flags & NV_MSI_X_CAPABLE) { 3669 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3815 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { 3670 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3816 np->msi_x_entry[i].entry = i; 3671 np->msi_x_entry[i].entry = i;
3817 } 3672 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3818 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { 3673 if (ret == 0) {
3819 np->msi_flags |= NV_MSI_X_ENABLED; 3674 np->msi_flags |= NV_MSI_X_ENABLED;
3820 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { 3675 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3821 /* Request irq for rx handling */ 3676 /* Request irq for rx handling */
3822 sprintf(np->name_rx, "%s-rx", dev->name); 3677 sprintf(np->name_rx, "%s-rx", dev->name);
3823 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, 3678 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3824 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { 3679 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3825 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); 3680 netdev_info(dev,
3681 "request_irq failed for rx %d\n",
3682 ret);
3826 pci_disable_msix(np->pci_dev); 3683 pci_disable_msix(np->pci_dev);
3827 np->msi_flags &= ~NV_MSI_X_ENABLED; 3684 np->msi_flags &= ~NV_MSI_X_ENABLED;
3828 goto out_err; 3685 goto out_err;
@@ -3831,7 +3688,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3831 sprintf(np->name_tx, "%s-tx", dev->name); 3688 sprintf(np->name_tx, "%s-tx", dev->name);
3832 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, 3689 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3833 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { 3690 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3834 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); 3691 netdev_info(dev,
3692 "request_irq failed for tx %d\n",
3693 ret);
3835 pci_disable_msix(np->pci_dev); 3694 pci_disable_msix(np->pci_dev);
3836 np->msi_flags &= ~NV_MSI_X_ENABLED; 3695 np->msi_flags &= ~NV_MSI_X_ENABLED;
3837 goto out_free_rx; 3696 goto out_free_rx;
@@ -3840,7 +3699,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3840 sprintf(np->name_other, "%s-other", dev->name); 3699 sprintf(np->name_other, "%s-other", dev->name);
3841 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, 3700 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3842 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { 3701 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3843 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); 3702 netdev_info(dev,
3703 "request_irq failed for link %d\n",
3704 ret);
3844 pci_disable_msix(np->pci_dev); 3705 pci_disable_msix(np->pci_dev);
3845 np->msi_flags &= ~NV_MSI_X_ENABLED; 3706 np->msi_flags &= ~NV_MSI_X_ENABLED;
3846 goto out_free_tx; 3707 goto out_free_tx;
@@ -3854,7 +3715,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3854 } else { 3715 } else {
3855 /* Request irq for all interrupts */ 3716 /* Request irq for all interrupts */
3856 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { 3717 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3857 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); 3718 netdev_info(dev,
3719 "request_irq failed %d\n",
3720 ret);
3858 pci_disable_msix(np->pci_dev); 3721 pci_disable_msix(np->pci_dev);
3859 np->msi_flags &= ~NV_MSI_X_ENABLED; 3722 np->msi_flags &= ~NV_MSI_X_ENABLED;
3860 goto out_err; 3723 goto out_err;
@@ -3867,11 +3730,13 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3867 } 3730 }
3868 } 3731 }
3869 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { 3732 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3870 if ((ret = pci_enable_msi(np->pci_dev)) == 0) { 3733 ret = pci_enable_msi(np->pci_dev);
3734 if (ret == 0) {
3871 np->msi_flags |= NV_MSI_ENABLED; 3735 np->msi_flags |= NV_MSI_ENABLED;
3872 dev->irq = np->pci_dev->irq; 3736 dev->irq = np->pci_dev->irq;
3873 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { 3737 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3874 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); 3738 netdev_info(dev, "request_irq failed %d\n",
3739 ret);
3875 pci_disable_msi(np->pci_dev); 3740 pci_disable_msi(np->pci_dev);
3876 np->msi_flags &= ~NV_MSI_ENABLED; 3741 np->msi_flags &= ~NV_MSI_ENABLED;
3877 dev->irq = np->pci_dev->irq; 3742 dev->irq = np->pci_dev->irq;
@@ -3906,9 +3771,8 @@ static void nv_free_irq(struct net_device *dev)
3906 int i; 3771 int i;
3907 3772
3908 if (np->msi_flags & NV_MSI_X_ENABLED) { 3773 if (np->msi_flags & NV_MSI_X_ENABLED) {
3909 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { 3774 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3910 free_irq(np->msi_x_entry[i].vector, dev); 3775 free_irq(np->msi_x_entry[i].vector, dev);
3911 }
3912 pci_disable_msix(np->pci_dev); 3776 pci_disable_msix(np->pci_dev);
3913 np->msi_flags &= ~NV_MSI_X_ENABLED; 3777 np->msi_flags &= ~NV_MSI_X_ENABLED;
3914 } else { 3778 } else {
@@ -3957,7 +3821,7 @@ static void nv_do_nic_poll(unsigned long data)
3957 3821
3958 if (np->recover_error) { 3822 if (np->recover_error) {
3959 np->recover_error = 0; 3823 np->recover_error = 0;
3960 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name); 3824 netdev_info(dev, "MAC in recoverable error state\n");
3961 if (netif_running(dev)) { 3825 if (netif_running(dev)) {
3962 netif_tx_lock_bh(dev); 3826 netif_tx_lock_bh(dev);
3963 netif_addr_lock(dev); 3827 netif_addr_lock(dev);
@@ -3978,7 +3842,7 @@ static void nv_do_nic_poll(unsigned long data)
3978 /* reinit nic view of the rx queue */ 3842 /* reinit nic view of the rx queue */
3979 writel(np->rx_buf_sz, base + NvRegOffloadConfig); 3843 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3980 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); 3844 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3981 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), 3845 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3982 base + NvRegRingSizes); 3846 base + NvRegRingSizes);
3983 pci_push(base); 3847 pci_push(base);
3984 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); 3848 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
@@ -4085,12 +3949,14 @@ static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4085 writel(flags, base + NvRegWakeUpFlags); 3949 writel(flags, base + NvRegWakeUpFlags);
4086 spin_unlock_irq(&np->lock); 3950 spin_unlock_irq(&np->lock);
4087 } 3951 }
3952 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4088 return 0; 3953 return 0;
4089} 3954}
4090 3955
4091static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3956static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4092{ 3957{
4093 struct fe_priv *np = netdev_priv(dev); 3958 struct fe_priv *np = netdev_priv(dev);
3959 u32 speed;
4094 int adv; 3960 int adv;
4095 3961
4096 spin_lock_irq(&np->lock); 3962 spin_lock_irq(&np->lock);
@@ -4108,25 +3974,28 @@ static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4108 } 3974 }
4109 3975
4110 if (netif_carrier_ok(dev)) { 3976 if (netif_carrier_ok(dev)) {
4111 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { 3977 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4112 case NVREG_LINKSPEED_10: 3978 case NVREG_LINKSPEED_10:
4113 ecmd->speed = SPEED_10; 3979 speed = SPEED_10;
4114 break; 3980 break;
4115 case NVREG_LINKSPEED_100: 3981 case NVREG_LINKSPEED_100:
4116 ecmd->speed = SPEED_100; 3982 speed = SPEED_100;
4117 break; 3983 break;
4118 case NVREG_LINKSPEED_1000: 3984 case NVREG_LINKSPEED_1000:
4119 ecmd->speed = SPEED_1000; 3985 speed = SPEED_1000;
3986 break;
3987 default:
3988 speed = -1;
4120 break; 3989 break;
4121 } 3990 }
4122 ecmd->duplex = DUPLEX_HALF; 3991 ecmd->duplex = DUPLEX_HALF;
4123 if (np->duplex) 3992 if (np->duplex)
4124 ecmd->duplex = DUPLEX_FULL; 3993 ecmd->duplex = DUPLEX_FULL;
4125 } else { 3994 } else {
4126 ecmd->speed = -1; 3995 speed = -1;
4127 ecmd->duplex = -1; 3996 ecmd->duplex = -1;
4128 } 3997 }
4129 3998 ethtool_cmd_speed_set(ecmd, speed);
4130 ecmd->autoneg = np->autoneg; 3999 ecmd->autoneg = np->autoneg;
4131 4000
4132 ecmd->advertising = ADVERTISED_MII; 4001 ecmd->advertising = ADVERTISED_MII;
@@ -4165,6 +4034,7 @@ static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4165static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 4034static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4166{ 4035{
4167 struct fe_priv *np = netdev_priv(dev); 4036 struct fe_priv *np = netdev_priv(dev);
4037 u32 speed = ethtool_cmd_speed(ecmd);
4168 4038
4169 if (ecmd->port != PORT_MII) 4039 if (ecmd->port != PORT_MII)
4170 return -EINVAL; 4040 return -EINVAL;
@@ -4188,9 +4058,9 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4188 4058
4189 } else if (ecmd->autoneg == AUTONEG_DISABLE) { 4059 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4190 /* Note: autonegotiation disable, speed 1000 intentionally 4060 /* Note: autonegotiation disable, speed 1000 intentionally
4191 * forbidden - noone should need that. */ 4061 * forbidden - no one should need that. */
4192 4062
4193 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) 4063 if (speed != SPEED_10 && speed != SPEED_100)
4194 return -EINVAL; 4064 return -EINVAL;
4195 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) 4065 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4196 return -EINVAL; 4066 return -EINVAL;
@@ -4238,7 +4108,7 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4238 adv |= ADVERTISE_100HALF; 4108 adv |= ADVERTISE_100HALF;
4239 if (ecmd->advertising & ADVERTISED_100baseT_Full) 4109 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4240 adv |= ADVERTISE_100FULL; 4110 adv |= ADVERTISE_100FULL;
4241 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ 4111 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4242 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 4112 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4243 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) 4113 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4244 adv |= ADVERTISE_PAUSE_ASYM; 4114 adv |= ADVERTISE_PAUSE_ASYM;
@@ -4253,14 +4123,14 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4253 } 4123 }
4254 4124
4255 if (netif_running(dev)) 4125 if (netif_running(dev))
4256 printk(KERN_INFO "%s: link down.\n", dev->name); 4126 netdev_info(dev, "link down\n");
4257 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 4127 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4258 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { 4128 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4259 bmcr |= BMCR_ANENABLE; 4129 bmcr |= BMCR_ANENABLE;
4260 /* reset the phy in order for settings to stick, 4130 /* reset the phy in order for settings to stick,
4261 * and cause autoneg to start */ 4131 * and cause autoneg to start */
4262 if (phy_reset(dev, bmcr)) { 4132 if (phy_reset(dev, bmcr)) {
4263 printk(KERN_INFO "%s: phy reset failed\n", dev->name); 4133 netdev_info(dev, "phy reset failed\n");
4264 return -EINVAL; 4134 return -EINVAL;
4265 } 4135 }
4266 } else { 4136 } else {
@@ -4274,16 +4144,16 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4274 4144
4275 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); 4145 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4276 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 4146 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4277 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) 4147 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4278 adv |= ADVERTISE_10HALF; 4148 adv |= ADVERTISE_10HALF;
4279 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) 4149 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4280 adv |= ADVERTISE_10FULL; 4150 adv |= ADVERTISE_10FULL;
4281 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) 4151 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4282 adv |= ADVERTISE_100HALF; 4152 adv |= ADVERTISE_100HALF;
4283 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) 4153 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4284 adv |= ADVERTISE_100FULL; 4154 adv |= ADVERTISE_100FULL;
4285 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); 4155 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4286 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */ 4156 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4287 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 4157 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4288 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; 4158 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4289 } 4159 }
@@ -4309,7 +4179,7 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4309 if (np->phy_oui == PHY_OUI_MARVELL) { 4179 if (np->phy_oui == PHY_OUI_MARVELL) {
4310 /* reset the phy in order for forced mode settings to stick */ 4180 /* reset the phy in order for forced mode settings to stick */
4311 if (phy_reset(dev, bmcr)) { 4181 if (phy_reset(dev, bmcr)) {
4312 printk(KERN_INFO "%s: phy reset failed\n", dev->name); 4182 netdev_info(dev, "phy reset failed\n");
4313 return -EINVAL; 4183 return -EINVAL;
4314 } 4184 }
4315 } else { 4185 } else {
@@ -4347,7 +4217,7 @@ static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void
4347 4217
4348 regs->version = FORCEDETH_REGS_VER; 4218 regs->version = FORCEDETH_REGS_VER;
4349 spin_lock_irq(&np->lock); 4219 spin_lock_irq(&np->lock);
4350 for (i = 0;i <= np->register_size/sizeof(u32); i++) 4220 for (i = 0; i <= np->register_size/sizeof(u32); i++)
4351 rbuf[i] = readl(base + i*sizeof(u32)); 4221 rbuf[i] = readl(base + i*sizeof(u32));
4352 spin_unlock_irq(&np->lock); 4222 spin_unlock_irq(&np->lock);
4353} 4223}
@@ -4371,7 +4241,7 @@ static int nv_nway_reset(struct net_device *dev)
4371 spin_unlock(&np->lock); 4241 spin_unlock(&np->lock);
4372 netif_addr_unlock(dev); 4242 netif_addr_unlock(dev);
4373 netif_tx_unlock_bh(dev); 4243 netif_tx_unlock_bh(dev);
4374 printk(KERN_INFO "%s: link down.\n", dev->name); 4244 netdev_info(dev, "link down\n");
4375 } 4245 }
4376 4246
4377 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 4247 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
@@ -4379,7 +4249,7 @@ static int nv_nway_reset(struct net_device *dev)
4379 bmcr |= BMCR_ANENABLE; 4249 bmcr |= BMCR_ANENABLE;
4380 /* reset the phy in order for settings to stick*/ 4250 /* reset the phy in order for settings to stick*/
4381 if (phy_reset(dev, bmcr)) { 4251 if (phy_reset(dev, bmcr)) {
4382 printk(KERN_INFO "%s: phy reset failed\n", dev->name); 4252 netdev_info(dev, "phy reset failed\n");
4383 return -EINVAL; 4253 return -EINVAL;
4384 } 4254 }
4385 } else { 4255 } else {
@@ -4399,16 +4269,6 @@ static int nv_nway_reset(struct net_device *dev)
4399 return ret; 4269 return ret;
4400} 4270}
4401 4271
4402static int nv_set_tso(struct net_device *dev, u32 value)
4403{
4404 struct fe_priv *np = netdev_priv(dev);
4405
4406 if ((np->driver_data & DEV_HAS_CHECKSUM))
4407 return ethtool_op_set_tso(dev, value);
4408 else
4409 return -EOPNOTSUPP;
4410}
4411
4412static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) 4272static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4413{ 4273{
4414 struct fe_priv *np = netdev_priv(dev); 4274 struct fe_priv *np = netdev_priv(dev);
@@ -4467,10 +4327,9 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
4467 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), 4327 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4468 rxtx_ring, ring_addr); 4328 rxtx_ring, ring_addr);
4469 } 4329 }
4470 if (rx_skbuff) 4330
4471 kfree(rx_skbuff); 4331 kfree(rx_skbuff);
4472 if (tx_skbuff) 4332 kfree(tx_skbuff);
4473 kfree(tx_skbuff);
4474 goto exit; 4333 goto exit;
4475 } 4334 }
4476 4335
@@ -4494,14 +4353,14 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
4494 np->tx_ring_size = ring->tx_pending; 4353 np->tx_ring_size = ring->tx_pending;
4495 4354
4496 if (!nv_optimized(np)) { 4355 if (!nv_optimized(np)) {
4497 np->rx_ring.orig = (struct ring_desc*)rxtx_ring; 4356 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4498 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; 4357 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4499 } else { 4358 } else {
4500 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring; 4359 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4501 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; 4360 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4502 } 4361 }
4503 np->rx_skb = (struct nv_skb_map*)rx_skbuff; 4362 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4504 np->tx_skb = (struct nv_skb_map*)tx_skbuff; 4363 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4505 np->ring_addr = ring_addr; 4364 np->ring_addr = ring_addr;
4506 4365
4507 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); 4366 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
@@ -4518,7 +4377,7 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
4518 /* reinit nic view of the queues */ 4377 /* reinit nic view of the queues */
4519 writel(np->rx_buf_sz, base + NvRegOffloadConfig); 4378 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4520 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); 4379 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4521 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), 4380 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4522 base + NvRegRingSizes); 4381 base + NvRegRingSizes);
4523 pci_push(base); 4382 pci_push(base);
4524 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); 4383 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
@@ -4553,12 +4412,11 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
4553 4412
4554 if ((!np->autoneg && np->duplex == 0) || 4413 if ((!np->autoneg && np->duplex == 0) ||
4555 (np->autoneg && !pause->autoneg && np->duplex == 0)) { 4414 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4556 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", 4415 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4557 dev->name);
4558 return -EINVAL; 4416 return -EINVAL;
4559 } 4417 }
4560 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { 4418 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4561 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name); 4419 netdev_info(dev, "hardware does not support tx pause frames\n");
4562 return -EINVAL; 4420 return -EINVAL;
4563 } 4421 }
4564 4422
@@ -4586,14 +4444,14 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
4586 4444
4587 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); 4445 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4588 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 4446 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4589 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ 4447 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4590 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 4448 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4591 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) 4449 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4592 adv |= ADVERTISE_PAUSE_ASYM; 4450 adv |= ADVERTISE_PAUSE_ASYM;
4593 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); 4451 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4594 4452
4595 if (netif_running(dev)) 4453 if (netif_running(dev))
4596 printk(KERN_INFO "%s: link down.\n", dev->name); 4454 netdev_info(dev, "link down\n");
4597 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 4455 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4598 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 4456 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4599 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); 4457 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
@@ -4617,58 +4475,36 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
4617 return 0; 4475 return 0;
4618} 4476}
4619 4477
4620static u32 nv_get_rx_csum(struct net_device *dev) 4478static u32 nv_fix_features(struct net_device *dev, u32 features)
4621{ 4479{
4622 struct fe_priv *np = netdev_priv(dev); 4480 /* vlan is dependent on rx checksum offload */
4623 return (np->rx_csum) != 0; 4481 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4482 features |= NETIF_F_RXCSUM;
4483
4484 return features;
4624} 4485}
4625 4486
4626static int nv_set_rx_csum(struct net_device *dev, u32 data) 4487static int nv_set_features(struct net_device *dev, u32 features)
4627{ 4488{
4628 struct fe_priv *np = netdev_priv(dev); 4489 struct fe_priv *np = netdev_priv(dev);
4629 u8 __iomem *base = get_hwbase(dev); 4490 u8 __iomem *base = get_hwbase(dev);
4630 int retcode = 0; 4491 u32 changed = dev->features ^ features;
4631
4632 if (np->driver_data & DEV_HAS_CHECKSUM) {
4633 if (data) {
4634 np->rx_csum = 1;
4635 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4636 } else {
4637 np->rx_csum = 0;
4638 /* vlan is dependent on rx checksum offload */
4639 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4640 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4641 }
4642 if (netif_running(dev)) {
4643 spin_lock_irq(&np->lock);
4644 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4645 spin_unlock_irq(&np->lock);
4646 }
4647 } else {
4648 return -EINVAL;
4649 }
4650 4492
4651 return retcode; 4493 if (changed & NETIF_F_RXCSUM) {
4652} 4494 spin_lock_irq(&np->lock);
4653 4495
4654static int nv_set_tx_csum(struct net_device *dev, u32 data) 4496 if (features & NETIF_F_RXCSUM)
4655{ 4497 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4656 struct fe_priv *np = netdev_priv(dev); 4498 else
4499 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4657 4500
4658 if (np->driver_data & DEV_HAS_CHECKSUM) 4501 if (netif_running(dev))
4659 return ethtool_op_set_tx_csum(dev, data); 4502 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4660 else
4661 return -EOPNOTSUPP;
4662}
4663 4503
4664static int nv_set_sg(struct net_device *dev, u32 data) 4504 spin_unlock_irq(&np->lock);
4665{ 4505 }
4666 struct fe_priv *np = netdev_priv(dev);
4667 4506
4668 if (np->driver_data & DEV_HAS_CHECKSUM) 4507 return 0;
4669 return ethtool_op_set_sg(dev, data);
4670 else
4671 return -EOPNOTSUPP;
4672} 4508}
4673 4509
4674static int nv_get_sset_count(struct net_device *dev, int sset) 4510static int nv_get_sset_count(struct net_device *dev, int sset)
@@ -4844,7 +4680,7 @@ static int nv_loopback_test(struct net_device *dev)
4844 /* reinit nic view of the rx queue */ 4680 /* reinit nic view of the rx queue */
4845 writel(np->rx_buf_sz, base + NvRegOffloadConfig); 4681 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4846 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); 4682 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4847 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), 4683 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4848 base + NvRegRingSizes); 4684 base + NvRegRingSizes);
4849 pci_push(base); 4685 pci_push(base);
4850 4686
@@ -4855,8 +4691,7 @@ static int nv_loopback_test(struct net_device *dev)
4855 pkt_len = ETH_DATA_LEN; 4691 pkt_len = ETH_DATA_LEN;
4856 tx_skb = dev_alloc_skb(pkt_len); 4692 tx_skb = dev_alloc_skb(pkt_len);
4857 if (!tx_skb) { 4693 if (!tx_skb) {
4858 printk(KERN_ERR "dev_alloc_skb() failed during loopback test" 4694 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4859 " of %s\n", dev->name);
4860 ret = 0; 4695 ret = 0;
4861 goto out; 4696 goto out;
4862 } 4697 }
@@ -4896,29 +4731,22 @@ static int nv_loopback_test(struct net_device *dev)
4896 if (flags & NV_RX_ERROR) 4731 if (flags & NV_RX_ERROR)
4897 ret = 0; 4732 ret = 0;
4898 } else { 4733 } else {
4899 if (flags & NV_RX2_ERROR) { 4734 if (flags & NV_RX2_ERROR)
4900 ret = 0; 4735 ret = 0;
4901 }
4902 } 4736 }
4903 4737
4904 if (ret) { 4738 if (ret) {
4905 if (len != pkt_len) { 4739 if (len != pkt_len) {
4906 ret = 0; 4740 ret = 0;
4907 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4908 dev->name, len, pkt_len);
4909 } else { 4741 } else {
4910 rx_skb = np->rx_skb[0].skb; 4742 rx_skb = np->rx_skb[0].skb;
4911 for (i = 0; i < pkt_len; i++) { 4743 for (i = 0; i < pkt_len; i++) {
4912 if (rx_skb->data[i] != (u8)(i & 0xff)) { 4744 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4913 ret = 0; 4745 ret = 0;
4914 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4915 dev->name, i);
4916 break; 4746 break;
4917 } 4747 }
4918 } 4748 }
4919 } 4749 }
4920 } else {
4921 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4922 } 4750 }
4923 4751
4924 pci_unmap_single(np->pci_dev, test_dma_addr, 4752 pci_unmap_single(np->pci_dev, test_dma_addr,
@@ -4961,11 +4789,10 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64
4961 netif_addr_lock(dev); 4789 netif_addr_lock(dev);
4962 spin_lock_irq(&np->lock); 4790 spin_lock_irq(&np->lock);
4963 nv_disable_hw_interrupts(dev, np->irqmask); 4791 nv_disable_hw_interrupts(dev, np->irqmask);
4964 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { 4792 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4965 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); 4793 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4966 } else { 4794 else
4967 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); 4795 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4968 }
4969 /* stop engines */ 4796 /* stop engines */
4970 nv_stop_rxtx(dev); 4797 nv_stop_rxtx(dev);
4971 nv_txrx_reset(dev); 4798 nv_txrx_reset(dev);
@@ -5006,7 +4833,7 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64
5006 /* reinit nic view of the rx queue */ 4833 /* reinit nic view of the rx queue */
5007 writel(np->rx_buf_sz, base + NvRegOffloadConfig); 4834 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5008 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); 4835 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5009 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), 4836 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5010 base + NvRegRingSizes); 4837 base + NvRegRingSizes);
5011 pci_push(base); 4838 pci_push(base);
5012 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); 4839 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
@@ -5042,15 +4869,10 @@ static const struct ethtool_ops ops = {
5042 .get_regs_len = nv_get_regs_len, 4869 .get_regs_len = nv_get_regs_len,
5043 .get_regs = nv_get_regs, 4870 .get_regs = nv_get_regs,
5044 .nway_reset = nv_nway_reset, 4871 .nway_reset = nv_nway_reset,
5045 .set_tso = nv_set_tso,
5046 .get_ringparam = nv_get_ringparam, 4872 .get_ringparam = nv_get_ringparam,
5047 .set_ringparam = nv_set_ringparam, 4873 .set_ringparam = nv_set_ringparam,
5048 .get_pauseparam = nv_get_pauseparam, 4874 .get_pauseparam = nv_get_pauseparam,
5049 .set_pauseparam = nv_set_pauseparam, 4875 .set_pauseparam = nv_set_pauseparam,
5050 .get_rx_csum = nv_get_rx_csum,
5051 .set_rx_csum = nv_set_rx_csum,
5052 .set_tx_csum = nv_set_tx_csum,
5053 .set_sg = nv_set_sg,
5054 .get_strings = nv_get_strings, 4876 .get_strings = nv_get_strings,
5055 .get_ethtool_stats = nv_get_ethtool_stats, 4877 .get_ethtool_stats = nv_get_ethtool_stats,
5056 .get_sset_count = nv_get_sset_count, 4878 .get_sset_count = nv_get_sset_count,
@@ -5109,8 +4931,7 @@ static int nv_mgmt_acquire_sema(struct net_device *dev)
5109 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { 4931 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5110 np->mgmt_sema = 1; 4932 np->mgmt_sema = 1;
5111 return 1; 4933 return 1;
5112 } 4934 } else
5113 else
5114 udelay(50); 4935 udelay(50);
5115 } 4936 }
5116 4937
@@ -5170,8 +4991,6 @@ static int nv_open(struct net_device *dev)
5170 int oom, i; 4991 int oom, i;
5171 u32 low; 4992 u32 low;
5172 4993
5173 dprintk(KERN_DEBUG "nv_open: begin\n");
5174
5175 /* power up phy */ 4994 /* power up phy */
5176 mii_rw(dev, np->phyaddr, MII_BMCR, 4995 mii_rw(dev, np->phyaddr, MII_BMCR,
5177 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); 4996 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
@@ -5207,7 +5026,7 @@ static int nv_open(struct net_device *dev)
5207 5026
5208 /* give hw rings */ 5027 /* give hw rings */
5209 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); 5028 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5210 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), 5029 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5211 base + NvRegRingSizes); 5030 base + NvRegRingSizes);
5212 5031
5213 writel(np->linkspeed, base + NvRegLinkSpeed); 5032 writel(np->linkspeed, base + NvRegLinkSpeed);
@@ -5219,9 +5038,11 @@ static int nv_open(struct net_device *dev)
5219 writel(np->vlanctl_bits, base + NvRegVlanControl); 5038 writel(np->vlanctl_bits, base + NvRegVlanControl);
5220 pci_push(base); 5039 pci_push(base);
5221 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); 5040 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5222 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, 5041 if (reg_delay(dev, NvRegUnknownSetupReg5,
5223 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, 5042 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5224 KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); 5043 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5044 netdev_info(dev,
5045 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5225 5046
5226 writel(0, base + NvRegMIIMask); 5047 writel(0, base + NvRegMIIMask);
5227 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); 5048 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
@@ -5254,8 +5075,7 @@ static int nv_open(struct net_device *dev)
5254 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); 5075 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5255 else 5076 else
5256 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); 5077 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5257 } 5078 } else
5258 else
5259 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); 5079 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5260 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); 5080 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5261 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, 5081 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
@@ -5266,7 +5086,7 @@ static int nv_open(struct net_device *dev)
5266 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); 5086 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5267 5087
5268 i = readl(base + NvRegPowerState); 5088 i = readl(base + NvRegPowerState);
5269 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) 5089 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5270 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); 5090 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5271 5091
5272 pci_push(base); 5092 pci_push(base);
@@ -5279,9 +5099,8 @@ static int nv_open(struct net_device *dev)
5279 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); 5099 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5280 pci_push(base); 5100 pci_push(base);
5281 5101
5282 if (nv_request_irq(dev, 0)) { 5102 if (nv_request_irq(dev, 0))
5283 goto out_drain; 5103 goto out_drain;
5284 }
5285 5104
5286 /* ask for interrupts */ 5105 /* ask for interrupts */
5287 nv_enable_hw_interrupts(dev, np->irqmask); 5106 nv_enable_hw_interrupts(dev, np->irqmask);
@@ -5299,7 +5118,6 @@ static int nv_open(struct net_device *dev)
5299 u32 miistat; 5118 u32 miistat;
5300 miistat = readl(base + NvRegMIIStatus); 5119 miistat = readl(base + NvRegMIIStatus);
5301 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); 5120 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5302 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5303 } 5121 }
5304 /* set linkspeed to invalid value, thus force nv_update_linkspeed 5122 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5305 * to init hw */ 5123 * to init hw */
@@ -5312,7 +5130,7 @@ static int nv_open(struct net_device *dev)
5312 if (ret) { 5130 if (ret) {
5313 netif_carrier_on(dev); 5131 netif_carrier_on(dev);
5314 } else { 5132 } else {
5315 printk(KERN_INFO "%s: no link during initialization.\n", dev->name); 5133 netdev_info(dev, "no link during initialization\n");
5316 netif_carrier_off(dev); 5134 netif_carrier_off(dev);
5317 } 5135 }
5318 if (oom) 5136 if (oom)
@@ -5355,7 +5173,6 @@ static int nv_close(struct net_device *dev)
5355 base = get_hwbase(dev); 5173 base = get_hwbase(dev);
5356 nv_disable_hw_interrupts(dev, np->irqmask); 5174 nv_disable_hw_interrupts(dev, np->irqmask);
5357 pci_push(base); 5175 pci_push(base);
5358 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5359 5176
5360 spin_unlock_irq(&np->lock); 5177 spin_unlock_irq(&np->lock);
5361 5178
@@ -5386,6 +5203,8 @@ static const struct net_device_ops nv_netdev_ops = {
5386 .ndo_start_xmit = nv_start_xmit, 5203 .ndo_start_xmit = nv_start_xmit,
5387 .ndo_tx_timeout = nv_tx_timeout, 5204 .ndo_tx_timeout = nv_tx_timeout,
5388 .ndo_change_mtu = nv_change_mtu, 5205 .ndo_change_mtu = nv_change_mtu,
5206 .ndo_fix_features = nv_fix_features,
5207 .ndo_set_features = nv_set_features,
5389 .ndo_validate_addr = eth_validate_addr, 5208 .ndo_validate_addr = eth_validate_addr,
5390 .ndo_set_mac_address = nv_set_mac_address, 5209 .ndo_set_mac_address = nv_set_mac_address,
5391 .ndo_set_multicast_list = nv_set_multicast, 5210 .ndo_set_multicast_list = nv_set_multicast,
@@ -5402,6 +5221,8 @@ static const struct net_device_ops nv_netdev_ops_optimized = {
5402 .ndo_start_xmit = nv_start_xmit_optimized, 5221 .ndo_start_xmit = nv_start_xmit_optimized,
5403 .ndo_tx_timeout = nv_tx_timeout, 5222 .ndo_tx_timeout = nv_tx_timeout,
5404 .ndo_change_mtu = nv_change_mtu, 5223 .ndo_change_mtu = nv_change_mtu,
5224 .ndo_fix_features = nv_fix_features,
5225 .ndo_set_features = nv_set_features,
5405 .ndo_validate_addr = eth_validate_addr, 5226 .ndo_validate_addr = eth_validate_addr,
5406 .ndo_set_mac_address = nv_set_mac_address, 5227 .ndo_set_mac_address = nv_set_mac_address,
5407 .ndo_set_multicast_list = nv_set_multicast, 5228 .ndo_set_multicast_list = nv_set_multicast,
@@ -5424,8 +5245,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5424 static int printed_version; 5245 static int printed_version;
5425 5246
5426 if (!printed_version++) 5247 if (!printed_version++)
5427 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet" 5248 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5428 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION); 5249 FORCEDETH_VERSION);
5429 5250
5430 dev = alloc_etherdev(sizeof(struct fe_priv)); 5251 dev = alloc_etherdev(sizeof(struct fe_priv));
5431 err = -ENOMEM; 5252 err = -ENOMEM;
@@ -5440,13 +5261,13 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5440 5261
5441 init_timer(&np->oom_kick); 5262 init_timer(&np->oom_kick);
5442 np->oom_kick.data = (unsigned long) dev; 5263 np->oom_kick.data = (unsigned long) dev;
5443 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ 5264 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5444 init_timer(&np->nic_poll); 5265 init_timer(&np->nic_poll);
5445 np->nic_poll.data = (unsigned long) dev; 5266 np->nic_poll.data = (unsigned long) dev;
5446 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ 5267 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5447 init_timer(&np->stats_poll); 5268 init_timer(&np->stats_poll);
5448 np->stats_poll.data = (unsigned long) dev; 5269 np->stats_poll.data = (unsigned long) dev;
5449 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */ 5270 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5450 5271
5451 err = pci_enable_device(pci_dev); 5272 err = pci_enable_device(pci_dev);
5452 if (err) 5273 if (err)
@@ -5468,10 +5289,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5468 err = -EINVAL; 5289 err = -EINVAL;
5469 addr = 0; 5290 addr = 0;
5470 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 5291 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5471 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5472 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5473 pci_resource_len(pci_dev, i),
5474 pci_resource_flags(pci_dev, i));
5475 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && 5292 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5476 pci_resource_len(pci_dev, i) >= np->register_size) { 5293 pci_resource_len(pci_dev, i) >= np->register_size) {
5477 addr = pci_resource_start(pci_dev, i); 5294 addr = pci_resource_start(pci_dev, i);
@@ -5479,8 +5296,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5479 } 5296 }
5480 } 5297 }
5481 if (i == DEVICE_COUNT_RESOURCE) { 5298 if (i == DEVICE_COUNT_RESOURCE) {
5482 dev_printk(KERN_INFO, &pci_dev->dev, 5299 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5483 "Couldn't find register window\n");
5484 goto out_relreg; 5300 goto out_relreg;
5485 } 5301 }
5486 5302
@@ -5496,13 +5312,13 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5496 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; 5312 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5497 if (dma_64bit) { 5313 if (dma_64bit) {
5498 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39))) 5314 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5499 dev_printk(KERN_INFO, &pci_dev->dev, 5315 dev_info(&pci_dev->dev,
5500 "64-bit DMA failed, using 32-bit addressing\n"); 5316 "64-bit DMA failed, using 32-bit addressing\n");
5501 else 5317 else
5502 dev->features |= NETIF_F_HIGHDMA; 5318 dev->features |= NETIF_F_HIGHDMA;
5503 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) { 5319 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5504 dev_printk(KERN_INFO, &pci_dev->dev, 5320 dev_info(&pci_dev->dev,
5505 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); 5321 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5506 } 5322 }
5507 } 5323 }
5508 } else if (id->driver_data & DEV_HAS_LARGEDESC) { 5324 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
@@ -5520,11 +5336,10 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5520 np->pkt_limit = NV_PKTLIMIT_2; 5336 np->pkt_limit = NV_PKTLIMIT_2;
5521 5337
5522 if (id->driver_data & DEV_HAS_CHECKSUM) { 5338 if (id->driver_data & DEV_HAS_CHECKSUM) {
5523 np->rx_csum = 1;
5524 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; 5339 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5525 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 5340 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5526 dev->features |= NETIF_F_TSO; 5341 NETIF_F_TSO | NETIF_F_RXCSUM;
5527 dev->features |= NETIF_F_GRO; 5342 dev->features |= dev->hw_features;
5528 } 5343 }
5529 5344
5530 np->vlanctl_bits = 0; 5345 np->vlanctl_bits = 0;
@@ -5540,7 +5355,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5540 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; 5355 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5541 } 5356 }
5542 5357
5543
5544 err = -ENOMEM; 5358 err = -ENOMEM;
5545 np->base = ioremap(addr, np->register_size); 5359 np->base = ioremap(addr, np->register_size);
5546 if (!np->base) 5360 if (!np->base)
@@ -5623,7 +5437,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5623 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; 5437 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5624 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; 5438 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5625 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); 5439 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5626 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n"); 5440 dev_dbg(&pci_dev->dev,
5441 "%s: set workaround bit for reversed mac addr\n",
5442 __func__);
5627 } 5443 }
5628 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 5444 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5629 5445
@@ -5632,28 +5448,21 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5632 * Bad mac address. At least one bios sets the mac address 5448 * Bad mac address. At least one bios sets the mac address
5633 * to 01:23:45:67:89:ab 5449 * to 01:23:45:67:89:ab
5634 */ 5450 */
5635 dev_printk(KERN_ERR, &pci_dev->dev, 5451 dev_err(&pci_dev->dev,
5636 "Invalid Mac address detected: %pM\n", 5452 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5637 dev->dev_addr); 5453 dev->dev_addr);
5638 dev_printk(KERN_ERR, &pci_dev->dev,
5639 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5640 random_ether_addr(dev->dev_addr); 5454 random_ether_addr(dev->dev_addr);
5455 dev_err(&pci_dev->dev,
5456 "Using random MAC address: %pM\n", dev->dev_addr);
5641 } 5457 }
5642 5458
5643 dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5644 pci_name(pci_dev), dev->dev_addr);
5645
5646 /* set mac address */ 5459 /* set mac address */
5647 nv_copy_mac_to_hw(dev); 5460 nv_copy_mac_to_hw(dev);
5648 5461
5649 /* Workaround current PCI init glitch: wakeup bits aren't
5650 * being set from PCI PM capability.
5651 */
5652 device_init_wakeup(&pci_dev->dev, 1);
5653
5654 /* disable WOL */ 5462 /* disable WOL */
5655 writel(0, base + NvRegWakeUpFlags); 5463 writel(0, base + NvRegWakeUpFlags);
5656 np->wolenabled = 0; 5464 np->wolenabled = 0;
5465 device_set_wakeup_enable(&pci_dev->dev, false);
5657 5466
5658 if (id->driver_data & DEV_HAS_POWER_CNTRL) { 5467 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5659 5468
@@ -5666,16 +5475,15 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5666 writel(powerstate, base + NvRegPowerState2); 5475 writel(powerstate, base + NvRegPowerState2);
5667 } 5476 }
5668 5477
5669 if (np->desc_ver == DESC_VER_1) { 5478 if (np->desc_ver == DESC_VER_1)
5670 np->tx_flags = NV_TX_VALID; 5479 np->tx_flags = NV_TX_VALID;
5671 } else { 5480 else
5672 np->tx_flags = NV_TX2_VALID; 5481 np->tx_flags = NV_TX2_VALID;
5673 }
5674 5482
5675 np->msi_flags = 0; 5483 np->msi_flags = 0;
5676 if ((id->driver_data & DEV_HAS_MSI) && msi) { 5484 if ((id->driver_data & DEV_HAS_MSI) && msi)
5677 np->msi_flags |= NV_MSI_CAPABLE; 5485 np->msi_flags |= NV_MSI_CAPABLE;
5678 } 5486
5679 if ((id->driver_data & DEV_HAS_MSI_X) && msix) { 5487 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5680 /* msix has had reported issues when modifying irqmask 5488 /* msix has had reported issues when modifying irqmask
5681 as in the case of napi, therefore, disable for now 5489 as in the case of napi, therefore, disable for now
@@ -5705,11 +5513,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5705 if (id->driver_data & DEV_NEED_TIMERIRQ) 5513 if (id->driver_data & DEV_NEED_TIMERIRQ)
5706 np->irqmask |= NVREG_IRQ_TIMER; 5514 np->irqmask |= NVREG_IRQ_TIMER;
5707 if (id->driver_data & DEV_NEED_LINKTIMER) { 5515 if (id->driver_data & DEV_NEED_LINKTIMER) {
5708 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5709 np->need_linktimer = 1; 5516 np->need_linktimer = 1;
5710 np->link_timeout = jiffies + LINK_TIMEOUT; 5517 np->link_timeout = jiffies + LINK_TIMEOUT;
5711 } else { 5518 } else {
5712 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5713 np->need_linktimer = 0; 5519 np->need_linktimer = 0;
5714 } 5520 }
5715 5521
@@ -5738,19 +5544,14 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5738 nv_mgmt_acquire_sema(dev) && 5544 nv_mgmt_acquire_sema(dev) &&
5739 nv_mgmt_get_version(dev)) { 5545 nv_mgmt_get_version(dev)) {
5740 np->mac_in_use = 1; 5546 np->mac_in_use = 1;
5741 if (np->mgmt_version > 0) { 5547 if (np->mgmt_version > 0)
5742 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; 5548 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5743 }
5744 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5745 pci_name(pci_dev), np->mac_in_use);
5746 /* management unit setup the phy already? */ 5549 /* management unit setup the phy already? */
5747 if (np->mac_in_use && 5550 if (np->mac_in_use &&
5748 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == 5551 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5749 NVREG_XMITCTL_SYNC_PHY_INIT)) { 5552 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5750 /* phy is inited by mgmt unit */ 5553 /* phy is inited by mgmt unit */
5751 phyinitialized = 1; 5554 phyinitialized = 1;
5752 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5753 pci_name(pci_dev));
5754 } else { 5555 } else {
5755 /* we need to init the phy */ 5556 /* we need to init the phy */
5756 } 5557 }
@@ -5776,8 +5577,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5776 np->phy_model = id2 & PHYID2_MODEL_MASK; 5577 np->phy_model = id2 & PHYID2_MODEL_MASK;
5777 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; 5578 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5778 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; 5579 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5779 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5780 pci_name(pci_dev), id1, id2, phyaddr);
5781 np->phyaddr = phyaddr; 5580 np->phyaddr = phyaddr;
5782 np->phy_oui = id1 | id2; 5581 np->phy_oui = id1 | id2;
5783 5582
@@ -5791,8 +5590,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5791 break; 5590 break;
5792 } 5591 }
5793 if (i == 33) { 5592 if (i == 33) {
5794 dev_printk(KERN_INFO, &pci_dev->dev, 5593 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5795 "open: Could not find a valid PHY.\n");
5796 goto out_error; 5594 goto out_error;
5797 } 5595 }
5798 5596
@@ -5802,9 +5600,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5802 } else { 5600 } else {
5803 /* see if it is a gigabit phy */ 5601 /* see if it is a gigabit phy */
5804 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); 5602 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5805 if (mii_status & PHY_GIGABIT) { 5603 if (mii_status & PHY_GIGABIT)
5806 np->gigabit = PHY_GIGABIT; 5604 np->gigabit = PHY_GIGABIT;
5807 }
5808 } 5605 }
5809 5606
5810 /* set default link speed settings */ 5607 /* set default link speed settings */
@@ -5814,37 +5611,29 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5814 5611
5815 err = register_netdev(dev); 5612 err = register_netdev(dev);
5816 if (err) { 5613 if (err) {
5817 dev_printk(KERN_INFO, &pci_dev->dev, 5614 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5818 "unable to register netdev: %d\n", err);
5819 goto out_error; 5615 goto out_error;
5820 } 5616 }
5821 5617
5822 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, " 5618 netif_carrier_off(dev);
5823 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", 5619
5824 dev->name, 5620 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5825 np->phy_oui, 5621 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5826 np->phyaddr, 5622
5827 dev->dev_addr[0], 5623 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5828 dev->dev_addr[1], 5624 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5829 dev->dev_addr[2], 5625 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5830 dev->dev_addr[3], 5626 "csum " : "",
5831 dev->dev_addr[4], 5627 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5832 dev->dev_addr[5]); 5628 "vlan " : "",
5833 5629 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5834 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", 5630 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5835 dev->features & NETIF_F_HIGHDMA ? "highdma " : "", 5631 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5836 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? 5632 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5837 "csum " : "", 5633 np->need_linktimer ? "lnktim " : "",
5838 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? 5634 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5839 "vlan " : "", 5635 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5840 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", 5636 np->desc_ver);
5841 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5842 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5843 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5844 np->need_linktimer ? "lnktim " : "",
5845 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5846 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5847 np->desc_ver);
5848 5637
5849 return 0; 5638 return 0;
5850 5639
@@ -5925,45 +5714,38 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
5925 pci_set_drvdata(pci_dev, NULL); 5714 pci_set_drvdata(pci_dev, NULL);
5926} 5715}
5927 5716
5928#ifdef CONFIG_PM 5717#ifdef CONFIG_PM_SLEEP
5929static int nv_suspend(struct pci_dev *pdev, pm_message_t state) 5718static int nv_suspend(struct device *device)
5930{ 5719{
5720 struct pci_dev *pdev = to_pci_dev(device);
5931 struct net_device *dev = pci_get_drvdata(pdev); 5721 struct net_device *dev = pci_get_drvdata(pdev);
5932 struct fe_priv *np = netdev_priv(dev); 5722 struct fe_priv *np = netdev_priv(dev);
5933 u8 __iomem *base = get_hwbase(dev); 5723 u8 __iomem *base = get_hwbase(dev);
5934 int i; 5724 int i;
5935 5725
5936 if (netif_running(dev)) { 5726 if (netif_running(dev)) {
5937 // Gross. 5727 /* Gross. */
5938 nv_close(dev); 5728 nv_close(dev);
5939 } 5729 }
5940 netif_device_detach(dev); 5730 netif_device_detach(dev);
5941 5731
5942 /* save non-pci configuration space */ 5732 /* save non-pci configuration space */
5943 for (i = 0;i <= np->register_size/sizeof(u32); i++) 5733 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5944 np->saved_config_space[i] = readl(base + i*sizeof(u32)); 5734 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5945 5735
5946 pci_save_state(pdev);
5947 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5948 pci_disable_device(pdev);
5949 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5950 return 0; 5736 return 0;
5951} 5737}
5952 5738
5953static int nv_resume(struct pci_dev *pdev) 5739static int nv_resume(struct device *device)
5954{ 5740{
5741 struct pci_dev *pdev = to_pci_dev(device);
5955 struct net_device *dev = pci_get_drvdata(pdev); 5742 struct net_device *dev = pci_get_drvdata(pdev);
5956 struct fe_priv *np = netdev_priv(dev); 5743 struct fe_priv *np = netdev_priv(dev);
5957 u8 __iomem *base = get_hwbase(dev); 5744 u8 __iomem *base = get_hwbase(dev);
5958 int i, rc = 0; 5745 int i, rc = 0;
5959 5746
5960 pci_set_power_state(pdev, PCI_D0);
5961 pci_restore_state(pdev);
5962 /* ack any pending wake events, disable PME */
5963 pci_enable_wake(pdev, PCI_D0, 0);
5964
5965 /* restore non-pci configuration space */ 5747 /* restore non-pci configuration space */
5966 for (i = 0;i <= np->register_size/sizeof(u32); i++) 5748 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5967 writel(np->saved_config_space[i], base+i*sizeof(u32)); 5749 writel(np->saved_config_space[i], base+i*sizeof(u32));
5968 5750
5969 if (np->driver_data & DEV_NEED_MSI_FIX) 5751 if (np->driver_data & DEV_NEED_MSI_FIX)
@@ -5980,6 +5762,14 @@ static int nv_resume(struct pci_dev *pdev)
5980 return rc; 5762 return rc;
5981} 5763}
5982 5764
5765static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5766#define NV_PM_OPS (&nv_pm_ops)
5767
5768#else
5769#define NV_PM_OPS NULL
5770#endif /* CONFIG_PM_SLEEP */
5771
5772#ifdef CONFIG_PM
5983static void nv_shutdown(struct pci_dev *pdev) 5773static void nv_shutdown(struct pci_dev *pdev)
5984{ 5774{
5985 struct net_device *dev = pci_get_drvdata(pdev); 5775 struct net_device *dev = pci_get_drvdata(pdev);
@@ -5993,9 +5783,8 @@ static void nv_shutdown(struct pci_dev *pdev)
5993 * If we really go for poweroff, we must not restore the MAC, 5783 * If we really go for poweroff, we must not restore the MAC,
5994 * otherwise the MAC for WOL will be reversed at least on some boards. 5784 * otherwise the MAC for WOL will be reversed at least on some boards.
5995 */ 5785 */
5996 if (system_state != SYSTEM_POWER_OFF) { 5786 if (system_state != SYSTEM_POWER_OFF)
5997 nv_restore_mac_addr(pdev); 5787 nv_restore_mac_addr(pdev);
5998 }
5999 5788
6000 pci_disable_device(pdev); 5789 pci_disable_device(pdev);
6001 /* 5790 /*
@@ -6003,15 +5792,12 @@ static void nv_shutdown(struct pci_dev *pdev)
6003 * only put the device into D3 if we really go for poweroff. 5792 * only put the device into D3 if we really go for poweroff.
6004 */ 5793 */
6005 if (system_state == SYSTEM_POWER_OFF) { 5794 if (system_state == SYSTEM_POWER_OFF) {
6006 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled)) 5795 pci_wake_from_d3(pdev, np->wolenabled);
6007 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6008 pci_set_power_state(pdev, PCI_D3hot); 5796 pci_set_power_state(pdev, PCI_D3hot);
6009 } 5797 }
6010} 5798}
6011#else 5799#else
6012#define nv_suspend NULL
6013#define nv_shutdown NULL 5800#define nv_shutdown NULL
6014#define nv_resume NULL
6015#endif /* CONFIG_PM */ 5801#endif /* CONFIG_PM */
6016 5802
6017static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = { 5803static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
@@ -6183,9 +5969,8 @@ static struct pci_driver driver = {
6183 .id_table = pci_tbl, 5969 .id_table = pci_tbl,
6184 .probe = nv_probe, 5970 .probe = nv_probe,
6185 .remove = __devexit_p(nv_remove), 5971 .remove = __devexit_p(nv_remove),
6186 .suspend = nv_suspend,
6187 .resume = nv_resume,
6188 .shutdown = nv_shutdown, 5972 .shutdown = nv_shutdown,
5973 .driver.pm = NV_PM_OPS,
6189}; 5974};
6190 5975
6191static int __init init_nic(void) 5976static int __init init_nic(void)