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path: root/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
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Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac1000.h')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac1000.h14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
index cfcef0ea0fa5..23478bf4ed7a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
@@ -61,9 +61,11 @@ enum power_event {
61}; 61};
62 62
63/* GMAC HW ADDR regs */ 63/* GMAC HW ADDR regs */
64#define GMAC_ADDR_HIGH(reg) (0x00000040+(reg * 8)) 64#define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \
65#define GMAC_ADDR_LOW(reg) (0x00000044+(reg * 8)) 65 (reg * 8))
66#define GMAC_MAX_UNICAST_ADDRESSES 16 66#define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \
67 (reg * 8))
68#define GMAC_MAX_PERFECT_ADDRESSES 32
67 69
68#define GMAC_AN_CTRL 0x000000c0 /* AN control */ 70#define GMAC_AN_CTRL 0x000000c0 /* AN control */
69#define GMAC_AN_STATUS 0x000000c4 /* AN status */ 71#define GMAC_AN_STATUS 0x000000c4 /* AN status */
@@ -139,10 +141,11 @@ enum rx_tx_priority_ratio {
139}; 141};
140 142
141#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 143#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
144#define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */
142#define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */ 145#define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
143#define DMA_BUS_MODE_RPBL_SHIFT 17 146#define DMA_BUS_MODE_RPBL_SHIFT 17
144#define DMA_BUS_MODE_USP 0x00800000 147#define DMA_BUS_MODE_USP 0x00800000
145#define DMA_BUS_MODE_4PBL 0x01000000 148#define DMA_BUS_MODE_PBL 0x01000000
146#define DMA_BUS_MODE_AAL 0x02000000 149#define DMA_BUS_MODE_AAL 0x02000000
147 150
148/* DMA CRS Control and Status Register Mapping */ 151/* DMA CRS Control and Status Register Mapping */
@@ -205,4 +208,7 @@ enum rtc_control {
205#define GMAC_MMC_TX_INTR 0x108 208#define GMAC_MMC_TX_INTR 0x108
206#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 209#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
207 210
211/* Synopsys Core versions */
212#define DWMAC_CORE_3_40 34
213
208extern const struct stmmac_dma_ops dwmac1000_dma_ops; 214extern const struct stmmac_dma_ops dwmac1000_dma_ops;