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Diffstat (limited to 'drivers/net/ethernet/renesas/sh_eth.h')
-rw-r--r--drivers/net/ethernet/renesas/sh_eth.h15
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index 57dc26261116..0fa14afce23d 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * SuperH Ethernet device driver 2 * SuperH Ethernet device driver
3 * 3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2011 Renesas Solutions Corp. 5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License, 8 * under the terms and conditions of the GNU General Public License,
@@ -98,6 +98,8 @@ enum {
98 CEECR, 98 CEECR,
99 MAFCR, 99 MAFCR,
100 RTRATE, 100 RTRATE,
101 CSMR,
102 RMII_MII,
101 103
102 /* TSU Absolute address */ 104 /* TSU Absolute address */
103 ARSTR, 105 ARSTR,
@@ -172,6 +174,7 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
172 [RMCR] = 0x0458, 174 [RMCR] = 0x0458,
173 [RPADIR] = 0x0460, 175 [RPADIR] = 0x0460,
174 [FCFTR] = 0x0468, 176 [FCFTR] = 0x0468,
177 [CSMR] = 0x04E4,
175 178
176 [ECMR] = 0x0500, 179 [ECMR] = 0x0500,
177 [ECSR] = 0x0510, 180 [ECSR] = 0x0510,
@@ -200,6 +203,7 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
200 [CERCR] = 0x0768, 203 [CERCR] = 0x0768,
201 [CEECR] = 0x0770, 204 [CEECR] = 0x0770,
202 [MAFCR] = 0x0778, 205 [MAFCR] = 0x0778,
206 [RMII_MII] = 0x0790,
203 207
204 [ARSTR] = 0x0000, 208 [ARSTR] = 0x0000,
205 [TSU_CTRST] = 0x0004, 209 [TSU_CTRST] = 0x0004,
@@ -377,7 +381,7 @@ static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
377/* 381/*
378 * Register's bits 382 * Register's bits
379 */ 383 */
380#ifdef CONFIG_CPU_SUBTYPE_SH7763 384#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
381/* EDSR */ 385/* EDSR */
382enum EDSR_BIT { 386enum EDSR_BIT {
383 EDSR_ENT = 0x01, EDSR_ENR = 0x02, 387 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
@@ -689,7 +693,7 @@ enum TSU_FWSLC_BIT {
689 */ 693 */
690struct sh_eth_txdesc { 694struct sh_eth_txdesc {
691 u32 status; /* TD0 */ 695 u32 status; /* TD0 */
692#if defined(CONFIG_CPU_LITTLE_ENDIAN) 696#if defined(__LITTLE_ENDIAN)
693 u16 pad0; /* TD1 */ 697 u16 pad0; /* TD1 */
694 u16 buffer_length; /* TD1 */ 698 u16 buffer_length; /* TD1 */
695#else 699#else
@@ -706,7 +710,7 @@ struct sh_eth_txdesc {
706 */ 710 */
707struct sh_eth_rxdesc { 711struct sh_eth_rxdesc {
708 u32 status; /* RD0 */ 712 u32 status; /* RD0 */
709#if defined(CONFIG_CPU_LITTLE_ENDIAN) 713#if defined(__LITTLE_ENDIAN)
710 u16 frame_length; /* RD1 */ 714 u16 frame_length; /* RD1 */
711 u16 buffer_length; /* RD1 */ 715 u16 buffer_length; /* RD1 */
712#else 716#else
@@ -751,6 +755,7 @@ struct sh_eth_cpu_data {
751 unsigned rpadir:1; /* E-DMAC have RPADIR */ 755 unsigned rpadir:1; /* E-DMAC have RPADIR */
752 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */ 756 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
753 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */ 757 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
758 unsigned hw_crc:1; /* E-DMAC have CSMR */
754}; 759};
755 760
756struct sh_eth_private { 761struct sh_eth_private {