diff options
Diffstat (limited to 'drivers/net/ethernet/renesas/sh_eth.c')
-rw-r--r-- | drivers/net/ethernet/renesas/sh_eth.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 4da8bd263997..736d5d1624a1 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c | |||
@@ -508,7 +508,6 @@ static struct sh_eth_cpu_data r8a779x_data = { | |||
508 | .tpauser = 1, | 508 | .tpauser = 1, |
509 | .hw_swap = 1, | 509 | .hw_swap = 1, |
510 | .rmiimode = 1, | 510 | .rmiimode = 1, |
511 | .shift_rd0 = 1, | ||
512 | }; | 511 | }; |
513 | 512 | ||
514 | static void sh_eth_set_rate_sh7724(struct net_device *ndev) | 513 | static void sh_eth_set_rate_sh7724(struct net_device *ndev) |
@@ -1392,6 +1391,9 @@ static void sh_eth_dev_exit(struct net_device *ndev) | |||
1392 | msleep(2); /* max frame time at 10 Mbps < 1250 us */ | 1391 | msleep(2); /* max frame time at 10 Mbps < 1250 us */ |
1393 | sh_eth_get_stats(ndev); | 1392 | sh_eth_get_stats(ndev); |
1394 | sh_eth_reset(ndev); | 1393 | sh_eth_reset(ndev); |
1394 | |||
1395 | /* Set MAC address again */ | ||
1396 | update_mac_address(ndev); | ||
1395 | } | 1397 | } |
1396 | 1398 | ||
1397 | /* free Tx skb function */ | 1399 | /* free Tx skb function */ |
@@ -1407,6 +1409,8 @@ static int sh_eth_txfree(struct net_device *ndev) | |||
1407 | txdesc = &mdp->tx_ring[entry]; | 1409 | txdesc = &mdp->tx_ring[entry]; |
1408 | if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) | 1410 | if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) |
1409 | break; | 1411 | break; |
1412 | /* TACT bit must be checked before all the following reads */ | ||
1413 | rmb(); | ||
1410 | /* Free the original skb. */ | 1414 | /* Free the original skb. */ |
1411 | if (mdp->tx_skbuff[entry]) { | 1415 | if (mdp->tx_skbuff[entry]) { |
1412 | dma_unmap_single(&ndev->dev, txdesc->addr, | 1416 | dma_unmap_single(&ndev->dev, txdesc->addr, |
@@ -1444,6 +1448,8 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) | |||
1444 | limit = boguscnt; | 1448 | limit = boguscnt; |
1445 | rxdesc = &mdp->rx_ring[entry]; | 1449 | rxdesc = &mdp->rx_ring[entry]; |
1446 | while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { | 1450 | while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { |
1451 | /* RACT bit must be checked before all the following reads */ | ||
1452 | rmb(); | ||
1447 | desc_status = edmac_to_cpu(mdp, rxdesc->status); | 1453 | desc_status = edmac_to_cpu(mdp, rxdesc->status); |
1448 | pkt_len = rxdesc->frame_length; | 1454 | pkt_len = rxdesc->frame_length; |
1449 | 1455 | ||
@@ -1455,8 +1461,8 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) | |||
1455 | 1461 | ||
1456 | /* In case of almost all GETHER/ETHERs, the Receive Frame State | 1462 | /* In case of almost all GETHER/ETHERs, the Receive Frame State |
1457 | * (RFS) bits in the Receive Descriptor 0 are from bit 9 to | 1463 | * (RFS) bits in the Receive Descriptor 0 are from bit 9 to |
1458 | * bit 0. However, in case of the R8A7740, R8A779x, and | 1464 | * bit 0. However, in case of the R8A7740 and R7S72100 |
1459 | * R7S72100 the RFS bits are from bit 25 to bit 16. So, the | 1465 | * the RFS bits are from bit 25 to bit 16. So, the |
1460 | * driver needs right shifting by 16. | 1466 | * driver needs right shifting by 16. |
1461 | */ | 1467 | */ |
1462 | if (mdp->cd->shift_rd0) | 1468 | if (mdp->cd->shift_rd0) |
@@ -1523,6 +1529,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) | |||
1523 | skb_checksum_none_assert(skb); | 1529 | skb_checksum_none_assert(skb); |
1524 | rxdesc->addr = dma_addr; | 1530 | rxdesc->addr = dma_addr; |
1525 | } | 1531 | } |
1532 | wmb(); /* RACT bit must be set after all the above writes */ | ||
1526 | if (entry >= mdp->num_rx_ring - 1) | 1533 | if (entry >= mdp->num_rx_ring - 1) |
1527 | rxdesc->status |= | 1534 | rxdesc->status |= |
1528 | cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); | 1535 | cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); |
@@ -1535,7 +1542,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) | |||
1535 | /* If we don't need to check status, don't. -KDU */ | 1542 | /* If we don't need to check status, don't. -KDU */ |
1536 | if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { | 1543 | if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { |
1537 | /* fix the values for the next receiving if RDE is set */ | 1544 | /* fix the values for the next receiving if RDE is set */ |
1538 | if (intr_status & EESR_RDE) { | 1545 | if (intr_status & EESR_RDE && mdp->reg_offset[RDFAR] != 0) { |
1539 | u32 count = (sh_eth_read(ndev, RDFAR) - | 1546 | u32 count = (sh_eth_read(ndev, RDFAR) - |
1540 | sh_eth_read(ndev, RDLAR)) >> 4; | 1547 | sh_eth_read(ndev, RDLAR)) >> 4; |
1541 | 1548 | ||
@@ -2174,7 +2181,7 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |||
2174 | } | 2181 | } |
2175 | spin_unlock_irqrestore(&mdp->lock, flags); | 2182 | spin_unlock_irqrestore(&mdp->lock, flags); |
2176 | 2183 | ||
2177 | if (skb_padto(skb, ETH_ZLEN)) | 2184 | if (skb_put_padto(skb, ETH_ZLEN)) |
2178 | return NETDEV_TX_OK; | 2185 | return NETDEV_TX_OK; |
2179 | 2186 | ||
2180 | entry = mdp->cur_tx % mdp->num_tx_ring; | 2187 | entry = mdp->cur_tx % mdp->num_tx_ring; |
@@ -2192,6 +2199,7 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |||
2192 | } | 2199 | } |
2193 | txdesc->buffer_length = skb->len; | 2200 | txdesc->buffer_length = skb->len; |
2194 | 2201 | ||
2202 | wmb(); /* TACT bit must be set after all the above writes */ | ||
2195 | if (entry >= mdp->num_tx_ring - 1) | 2203 | if (entry >= mdp->num_tx_ring - 1) |
2196 | txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); | 2204 | txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); |
2197 | else | 2205 | else |