1 files changed, 121 insertions, 1 deletions
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 8a9cb209cb58..03020a48b9d4 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -44,6 +44,7 @@
 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
+#define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
 #ifdef RTL8169_DEBUG
 #define assert(expr) \
@@ -133,6 +134,7 @@ enum mac_version {
        RTL_GIGA_MAC_VER_34,
        RTL_GIGA_MAC_VER_35,
        RTL_GIGA_MAC_VER_36,
+        RTL_GIGA_MAC_VER_37,
        RTL_GIGA_MAC_NONE   = 0xff,
 };
@@ -245,6 +247,9 @@ static const struct {
        [RTL_GIGA_MAC_VER_36] =
                _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
                                                        JUMBO_9K, false),
+        [RTL_GIGA_MAC_VER_37] =
+                _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
+                                                        JUMBO_1K, true),
 };
 #undef _R
@@ -357,6 +362,9 @@ enum rtl8168_8101_registers {
 #define CSIAR_BYTE_ENABLE               0x0f
 #define CSIAR_BYTE_ENABLE_SHIFT         12
 #define CSIAR_ADDR_MASK                 0x0fff
+#define CSIAR_FUNC_CARD                 0x00000000
+#define CSIAR_FUNC_SDIO                 0x00010000
+#define CSIAR_FUNC_NIC                  0x00020000
        PMCH                    = 0x6f,
        EPHYAR                  = 0x80,
 #define EPHYAR_FLAG                     0x80000000
@@ -775,6 +783,7 @@ MODULE_FIRMWARE(FIRMWARE_8168E_3);
 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 MODULE_FIRMWARE(FIRMWARE_8168F_2);
+MODULE_FIRMWARE(FIRMWARE_8402_1);
 static void rtl_lock_work(struct rtl8169_private *tp)
 {
@@ -1289,6 +1298,16 @@ static void rtl_link_chg_patch(struct rtl8169_private *tp)
                        rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
                                      0x0000003f, ERIAR_EXGMAC);
                }
+        } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
+                if (RTL_R8(PHYstatus) & _10bps) {
+                        rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
+                                      0x4d02, ERIAR_EXGMAC);
+                        rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_0011,
+                                      0x0060, ERIAR_EXGMAC);
+                } else {
+                        rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
+                                      0x0000, ERIAR_EXGMAC);
+                }
        }
 }
@@ -1902,6 +1921,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
                { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
                /* 8101 family. */
+                { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
                { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
                { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
                { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
@@ -3136,6 +3156,25 @@ static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
+static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
+{
+        void __iomem *ioaddr = tp->mmio_addr;
+        /* Disable ALDPS before setting firmware */
+        rtl_writephy(tp, 0x1f, 0x0000);
+        rtl_writephy(tp, 0x18, 0x0310);
+        msleep(20);
+        rtl_apply_firmware(tp);
+        /* EEE setting */
+        rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+        rtl_writephy(tp, 0x1f, 0x0004);
+        rtl_writephy(tp, 0x10, 0x401f);
+        rtl_writephy(tp, 0x19, 0x7030);
+        rtl_writephy(tp, 0x1f, 0x0000);
+}
 static void rtl_hw_phy_config(struct net_device *dev)
 {
        struct rtl8169_private *tp = netdev_priv(dev);
@@ -3224,6 +3263,10 @@ static void rtl_hw_phy_config(struct net_device *dev)
                rtl8168f_2_hw_phy_config(tp);
                break;
+        case RTL_GIGA_MAC_VER_37:
+                rtl8402_hw_phy_config(tp);
+                break;
        default:
                break;
        }
@@ -3461,6 +3504,7 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
        case RTL_GIGA_MAC_VER_32:
        case RTL_GIGA_MAC_VER_33:
        case RTL_GIGA_MAC_VER_34:
+        case RTL_GIGA_MAC_VER_37:
                RTL_W32(RxConfig, RTL_R32(RxConfig) |
                        AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
                break;
@@ -3682,6 +3726,7 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
        case RTL_GIGA_MAC_VER_16:
        case RTL_GIGA_MAC_VER_29:
        case RTL_GIGA_MAC_VER_30:
+        case RTL_GIGA_MAC_VER_37:
                ops->down       = r810x_pll_power_down;
                ops->up         = r810x_pll_power_up;
                break;
@@ -3991,7 +4036,8 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
                        udelay(20);
        } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
                   tp->mac_version == RTL_GIGA_MAC_VER_35 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_36) {
+                   tp->mac_version == RTL_GIGA_MAC_VER_36 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_37) {
                RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
                while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
                        udelay(100);
@@ -4263,6 +4309,41 @@ static u32 r8169_csi_read(void __iomem *ioaddr, int addr)
        return value;
 }
+static void r8402_csi_write(void __iomem *ioaddr, int addr, int value)
+{
+        unsigned int i;
+        RTL_W32(CSIDR, value);
+        RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
+                CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
+                CSIAR_FUNC_NIC);
+        for (i = 0; i < 100; i++) {
+                if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
+                        break;
+                udelay(10);
+        }
+}
+static u32 r8402_csi_read(void __iomem *ioaddr, int addr)
+{
+        u32 value = ~0x00;
+        unsigned int i;
+        RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
+                CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
+        for (i = 0; i < 100; i++) {
+                if (RTL_R32(CSIAR) & CSIAR_FLAG) {
+                        value = RTL_R32(CSIDR);
+                        break;
+                }
+                udelay(10);
+        }
+        return value;
+}
 static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
 {
        struct csi_ops *ops = &tp->csi_ops;
@@ -4286,6 +4367,11 @@ static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
                ops->read       = NULL;
                break;
+        case RTL_GIGA_MAC_VER_37:
+                ops->write      = r8402_csi_write;
+                ops->read       = r8402_csi_read;
+                break;
        default:
                ops->write      = r8169_csi_write;
                ops->read       = r8169_csi_read;
@@ -4871,6 +4957,36 @@ static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
        rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
 }
+static void rtl_hw_start_8402(struct rtl8169_private *tp)
+{
+        void __iomem *ioaddr = tp->mmio_addr;
+        static const struct ephy_info e_info_8402[] = {
+                { 0x19, 0xffff, 0xff64 },
+                { 0x1e, 0, 0x4000 }
+        };
+        rtl_csi_access_enable_2(tp);
+        /* Force LAN exit from ASPM if Rx/Tx are not idle */
+        RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
+        RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
+        RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
+        rtl_ephy_init(ioaddr, e_info_8402, ARRAY_SIZE(e_info_8402));
+        rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
+        rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
+        rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
+        rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
+        rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
+        rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+        rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+        rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00,
+                     ERIAR_EXGMAC);
+}
 static void rtl_hw_start_8101(struct net_device *dev)
 {
        struct rtl8169_private *tp = netdev_priv(dev);
@@ -4911,6 +5027,10 @@ static void rtl_hw_start_8101(struct net_device *dev)
        case RTL_GIGA_MAC_VER_30:
                rtl_hw_start_8105e_2(tp);
                break;
+        case RTL_GIGA_MAC_VER_37:
+                rtl_hw_start_8402(tp);
+                break;
        }
        RTL_W8(Cfg9346, Cfg9346_Lock);

diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index 8a9cb209cb58..03020a48b9d4 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c
@@ -44,6 +44,7 @@
44	#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"	44	#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45	#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"	45	#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46	#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"	46	#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
		47	#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47		48
48	#ifdef RTL8169_DEBUG	49	#ifdef RTL8169_DEBUG
49	#define assert(expr) \	50	#define assert(expr) \
@@ -133,6 +134,7 @@ enum mac_version {
133	RTL_GIGA_MAC_VER_34,	134	RTL_GIGA_MAC_VER_34,
134	RTL_GIGA_MAC_VER_35,	135	RTL_GIGA_MAC_VER_35,
135	RTL_GIGA_MAC_VER_36,	136	RTL_GIGA_MAC_VER_36,
		137	RTL_GIGA_MAC_VER_37,
136	RTL_GIGA_MAC_NONE = 0xff,	138	RTL_GIGA_MAC_NONE = 0xff,
137	};	139	};
138		140
@@ -245,6 +247,9 @@ static const struct {
245	[RTL_GIGA_MAC_VER_36] =	247	[RTL_GIGA_MAC_VER_36] =
246	_R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,	248	_R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
247	JUMBO_9K, false),	249	JUMBO_9K, false),
		250	[RTL_GIGA_MAC_VER_37] =
		251	_R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
		252	JUMBO_1K, true),
248	};	253	};
249	#undef _R	254	#undef _R
250		255
@@ -357,6 +362,9 @@ enum rtl8168_8101_registers {
357	#define CSIAR_BYTE_ENABLE 0x0f	362	#define CSIAR_BYTE_ENABLE 0x0f
358	#define CSIAR_BYTE_ENABLE_SHIFT 12	363	#define CSIAR_BYTE_ENABLE_SHIFT 12
359	#define CSIAR_ADDR_MASK 0x0fff	364	#define CSIAR_ADDR_MASK 0x0fff
		365	#define CSIAR_FUNC_CARD 0x00000000
		366	#define CSIAR_FUNC_SDIO 0x00010000
		367	#define CSIAR_FUNC_NIC 0x00020000
360	PMCH = 0x6f,	368	PMCH = 0x6f,
361	EPHYAR = 0x80,	369	EPHYAR = 0x80,
362	#define EPHYAR_FLAG 0x80000000	370	#define EPHYAR_FLAG 0x80000000
@@ -775,6 +783,7 @@ MODULE_FIRMWARE(FIRMWARE_8168E_3);
775	MODULE_FIRMWARE(FIRMWARE_8105E_1);	783	MODULE_FIRMWARE(FIRMWARE_8105E_1);
776	MODULE_FIRMWARE(FIRMWARE_8168F_1);	784	MODULE_FIRMWARE(FIRMWARE_8168F_1);
777	MODULE_FIRMWARE(FIRMWARE_8168F_2);	785	MODULE_FIRMWARE(FIRMWARE_8168F_2);
		786	MODULE_FIRMWARE(FIRMWARE_8402_1);
778		787
779	static void rtl_lock_work(struct rtl8169_private *tp)	788	static void rtl_lock_work(struct rtl8169_private *tp)
780	{	789	{
@@ -1289,6 +1298,16 @@ static void rtl_link_chg_patch(struct rtl8169_private *tp)
1289	rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,	1298	rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1290	0x0000003f, ERIAR_EXGMAC);	1299	0x0000003f, ERIAR_EXGMAC);
1291	}	1300	}
		1301	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
		1302	if (RTL_R8(PHYstatus) & _10bps) {
		1303	rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
		1304	0x4d02, ERIAR_EXGMAC);
		1305	rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_0011,
		1306	0x0060, ERIAR_EXGMAC);
		1307	} else {
		1308	rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
		1309	0x0000, ERIAR_EXGMAC);
		1310	}
1292	}	1311	}
1293	}	1312	}
1294		1313
@@ -1902,6 +1921,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1902	{ 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },	1921	{ 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1903		1922
1904	/* 8101 family. */	1923	/* 8101 family. */
		1924	{ 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
1905	{ 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },	1925	{ 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1906	{ 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },	1926	{ 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1907	{ 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },	1927	{ 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
@@ -3136,6 +3156,25 @@ static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3136	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));	3156	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3137	}	3157	}
3138		3158
		3159	static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
		3160	{
		3161	void __iomem *ioaddr = tp->mmio_addr;
		3162
		3163	/* Disable ALDPS before setting firmware */
		3164	rtl_writephy(tp, 0x1f, 0x0000);
		3165	rtl_writephy(tp, 0x18, 0x0310);
		3166	msleep(20);
		3167
		3168	rtl_apply_firmware(tp);
		3169
		3170	/* EEE setting */
		3171	rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
		3172	rtl_writephy(tp, 0x1f, 0x0004);
		3173	rtl_writephy(tp, 0x10, 0x401f);
		3174	rtl_writephy(tp, 0x19, 0x7030);
		3175	rtl_writephy(tp, 0x1f, 0x0000);
		3176	}
		3177
3139	static void rtl_hw_phy_config(struct net_device *dev)	3178	static void rtl_hw_phy_config(struct net_device *dev)
3140	{	3179	{
3141	struct rtl8169_private *tp = netdev_priv(dev);	3180	struct rtl8169_private *tp = netdev_priv(dev);
@@ -3224,6 +3263,10 @@ static void rtl_hw_phy_config(struct net_device *dev)
3224	rtl8168f_2_hw_phy_config(tp);	3263	rtl8168f_2_hw_phy_config(tp);
3225	break;	3264	break;
3226		3265
		3266	case RTL_GIGA_MAC_VER_37:
		3267	rtl8402_hw_phy_config(tp);
		3268	break;
		3269
3227	default:	3270	default:
3228	break;	3271	break;
3229	}	3272	}
@@ -3461,6 +3504,7 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3461	case RTL_GIGA_MAC_VER_32:	3504	case RTL_GIGA_MAC_VER_32:
3462	case RTL_GIGA_MAC_VER_33:	3505	case RTL_GIGA_MAC_VER_33:
3463	case RTL_GIGA_MAC_VER_34:	3506	case RTL_GIGA_MAC_VER_34:
		3507	case RTL_GIGA_MAC_VER_37:
3464	RTL_W32(RxConfig, RTL_R32(RxConfig) \|	3508	RTL_W32(RxConfig, RTL_R32(RxConfig) \|
3465	AcceptBroadcast \| AcceptMulticast \| AcceptMyPhys);	3509	AcceptBroadcast \| AcceptMulticast \| AcceptMyPhys);
3466	break;	3510	break;
@@ -3682,6 +3726,7 @@ static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3682	case RTL_GIGA_MAC_VER_16:	3726	case RTL_GIGA_MAC_VER_16:
3683	case RTL_GIGA_MAC_VER_29:	3727	case RTL_GIGA_MAC_VER_29:
3684	case RTL_GIGA_MAC_VER_30:	3728	case RTL_GIGA_MAC_VER_30:
		3729	case RTL_GIGA_MAC_VER_37:
3685	ops->down = r810x_pll_power_down;	3730	ops->down = r810x_pll_power_down;
3686	ops->up = r810x_pll_power_up;	3731	ops->up = r810x_pll_power_up;
3687	break;	3732	break;
@@ -3991,7 +4036,8 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
3991	udelay(20);	4036	udelay(20);
3992	} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 \|\|	4037	} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 \|\|
3993	tp->mac_version == RTL_GIGA_MAC_VER_35 \|\|	4038	tp->mac_version == RTL_GIGA_MAC_VER_35 \|\|
3994	tp->mac_version == RTL_GIGA_MAC_VER_36) {	4039	tp->mac_version == RTL_GIGA_MAC_VER_36 \|\|
		4040	tp->mac_version == RTL_GIGA_MAC_VER_37) {
3995	RTL_W8(ChipCmd, RTL_R8(ChipCmd) \| StopReq);	4041	RTL_W8(ChipCmd, RTL_R8(ChipCmd) \| StopReq);
3996	while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))	4042	while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3997	udelay(100);	4043	udelay(100);
@@ -4263,6 +4309,41 @@ static u32 r8169_csi_read(void __iomem *ioaddr, int addr)
4263	return value;	4309	return value;
4264	}	4310	}
4265		4311
		4312	static void r8402_csi_write(void __iomem *ioaddr, int addr, int value)
		4313	{
		4314	unsigned int i;
		4315
		4316	RTL_W32(CSIDR, value);
		4317	RTL_W32(CSIAR, CSIAR_WRITE_CMD \| (addr & CSIAR_ADDR_MASK) \|
		4318	CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT \|
		4319	CSIAR_FUNC_NIC);
		4320
		4321	for (i = 0; i < 100; i++) {
		4322	if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
		4323	break;
		4324	udelay(10);
		4325	}
		4326	}
		4327
		4328	static u32 r8402_csi_read(void __iomem *ioaddr, int addr)
		4329	{
		4330	u32 value = ~0x00;
		4331	unsigned int i;
		4332
		4333	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) \| CSIAR_FUNC_NIC \|
		4334	CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
		4335
		4336	for (i = 0; i < 100; i++) {
		4337	if (RTL_R32(CSIAR) & CSIAR_FLAG) {
		4338	value = RTL_R32(CSIDR);
		4339	break;
		4340	}
		4341	udelay(10);
		4342	}
		4343
		4344	return value;
		4345	}
		4346
4266	static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)	4347	static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4267	{	4348	{
4268	struct csi_ops *ops = &tp->csi_ops;	4349	struct csi_ops *ops = &tp->csi_ops;
@@ -4286,6 +4367,11 @@ static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4286	ops->read = NULL;	4367	ops->read = NULL;
4287	break;	4368	break;
4288		4369
		4370	case RTL_GIGA_MAC_VER_37:
		4371	ops->write = r8402_csi_write;
		4372	ops->read = r8402_csi_read;
		4373	break;
		4374
4289	default:	4375	default:
4290	ops->write = r8169_csi_write;	4376	ops->write = r8169_csi_write;
4291	ops->read = r8169_csi_read;	4377	ops->read = r8169_csi_read;
@@ -4871,6 +4957,36 @@ static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4871	rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) \| 0x8000);	4957	rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) \| 0x8000);
4872	}	4958	}
4873		4959
		4960	static void rtl_hw_start_8402(struct rtl8169_private *tp)
		4961	{
		4962	void __iomem *ioaddr = tp->mmio_addr;
		4963	static const struct ephy_info e_info_8402[] = {
		4964	{ 0x19, 0xffff, 0xff64 },
		4965	{ 0x1e, 0, 0x4000 }
		4966	};
		4967
		4968	rtl_csi_access_enable_2(tp);
		4969
		4970	/* Force LAN exit from ASPM if Rx/Tx are not idle */
		4971	RTL_W32(FuncEvent, RTL_R32(FuncEvent) \| 0x002800);
		4972
		4973	RTL_W32(TxConfig, RTL_R32(TxConfig) \| TXCFG_AUTO_FIFO);
		4974	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
		4975
		4976	rtl_ephy_init(ioaddr, e_info_8402, ARRAY_SIZE(e_info_8402));
		4977
		4978	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
		4979
		4980	rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
		4981	rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
		4982	rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
		4983	rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
		4984	rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
		4985	rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
		4986	rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00,
		4987	ERIAR_EXGMAC);
		4988	}
		4989
4874	static void rtl_hw_start_8101(struct net_device *dev)	4990	static void rtl_hw_start_8101(struct net_device *dev)
4875	{	4991	{
4876	struct rtl8169_private *tp = netdev_priv(dev);	4992	struct rtl8169_private *tp = netdev_priv(dev);
@@ -4911,6 +5027,10 @@ static void rtl_hw_start_8101(struct net_device *dev)
4911	case RTL_GIGA_MAC_VER_30:	5027	case RTL_GIGA_MAC_VER_30:
4912	rtl_hw_start_8105e_2(tp);	5028	rtl_hw_start_8105e_2(tp);
4913	break;	5029	break;
		5030
		5031	case RTL_GIGA_MAC_VER_37:
		5032	rtl_hw_start_8402(tp);
		5033	break;
4914	}	5034	}
4915		5035
4916	RTL_W8(Cfg9346, Cfg9346_Lock);	5036	RTL_W8(Cfg9346, Cfg9346_Lock);