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path: root/drivers/net/ethernet/mellanox/mlx4/mcg.c
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Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx4/mcg.c')
-rw-r--r--drivers/net/ethernet/mellanox/mlx4/mcg.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx4/mcg.c b/drivers/net/ethernet/mellanox/mlx4/mcg.c
index d80e7a6fac74..ca0f98c95105 100644
--- a/drivers/net/ethernet/mellanox/mlx4/mcg.c
+++ b/drivers/net/ethernet/mellanox/mlx4/mcg.c
@@ -1020,6 +1020,44 @@ int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
1020} 1020}
1021EXPORT_SYMBOL_GPL(mlx4_flow_detach); 1021EXPORT_SYMBOL_GPL(mlx4_flow_detach);
1022 1022
1023int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1024 int port, int qpn, u16 prio, u64 *reg_id)
1025{
1026 int err;
1027 struct mlx4_spec_list spec_eth_outer = { {NULL} };
1028 struct mlx4_spec_list spec_vxlan = { {NULL} };
1029 struct mlx4_spec_list spec_eth_inner = { {NULL} };
1030
1031 struct mlx4_net_trans_rule rule = {
1032 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1033 .exclusive = 0,
1034 .allow_loopback = 1,
1035 .promisc_mode = MLX4_FS_REGULAR,
1036 };
1037
1038 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1039
1040 rule.port = port;
1041 rule.qpn = qpn;
1042 rule.priority = prio;
1043 INIT_LIST_HEAD(&rule.list);
1044
1045 spec_eth_outer.id = MLX4_NET_TRANS_RULE_ID_ETH;
1046 memcpy(spec_eth_outer.eth.dst_mac, addr, ETH_ALEN);
1047 memcpy(spec_eth_outer.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1048
1049 spec_vxlan.id = MLX4_NET_TRANS_RULE_ID_VXLAN; /* any vxlan header */
1050 spec_eth_inner.id = MLX4_NET_TRANS_RULE_ID_ETH; /* any inner eth header */
1051
1052 list_add_tail(&spec_eth_outer.list, &rule.list);
1053 list_add_tail(&spec_vxlan.list, &rule.list);
1054 list_add_tail(&spec_eth_inner.list, &rule.list);
1055
1056 err = mlx4_flow_attach(dev, &rule, reg_id);
1057 return err;
1058}
1059EXPORT_SYMBOL(mlx4_tunnel_steer_add);
1060
1023int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1061int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1024 u32 max_range_qpn) 1062 u32 max_range_qpn)
1025{ 1063{