diff options
Diffstat (limited to 'drivers/net/ethernet/marvell/mvneta.c')
-rw-r--r-- | drivers/net/ethernet/marvell/mvneta.c | 60 |
1 files changed, 20 insertions, 40 deletions
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index f418f4f20f94..8d76fca7fde7 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
23 | #include <net/ip.h> | 23 | #include <net/ip.h> |
24 | #include <net/ipv6.h> | 24 | #include <net/ipv6.h> |
25 | #include <linux/io.h> | ||
25 | #include <linux/of.h> | 26 | #include <linux/of.h> |
26 | #include <linux/of_irq.h> | 27 | #include <linux/of_irq.h> |
27 | #include <linux/of_mdio.h> | 28 | #include <linux/of_mdio.h> |
@@ -88,8 +89,9 @@ | |||
88 | #define MVNETA_TX_IN_PRGRS BIT(1) | 89 | #define MVNETA_TX_IN_PRGRS BIT(1) |
89 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | 90 | #define MVNETA_TX_FIFO_EMPTY BIT(8) |
90 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | 91 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c |
91 | #define MVNETA_SGMII_SERDES_CFG 0x24A0 | 92 | #define MVNETA_SERDES_CFG 0x24A0 |
92 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 | 93 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
94 | #define MVNETA_RGMII_SERDES_PROTO 0x0667 | ||
93 | #define MVNETA_TYPE_PRIO 0x24bc | 95 | #define MVNETA_TYPE_PRIO 0x24bc |
94 | #define MVNETA_FORCE_UNI BIT(21) | 96 | #define MVNETA_FORCE_UNI BIT(21) |
95 | #define MVNETA_TXQ_CMD_1 0x24e4 | 97 | #define MVNETA_TXQ_CMD_1 0x24e4 |
@@ -161,7 +163,7 @@ | |||
161 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | 163 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc |
162 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | 164 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) |
163 | #define MVNETA_GMAC_CTRL_2 0x2c08 | 165 | #define MVNETA_GMAC_CTRL_2 0x2c08 |
164 | #define MVNETA_GMAC2_PSC_ENABLE BIT(3) | 166 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
165 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) | 167 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
166 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | 168 | #define MVNETA_GMAC2_PORT_RESET BIT(6) |
167 | #define MVNETA_GMAC_STATUS 0x2c10 | 169 | #define MVNETA_GMAC_STATUS 0x2c10 |
@@ -710,35 +712,6 @@ static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |||
710 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | 712 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); |
711 | } | 713 | } |
712 | 714 | ||
713 | |||
714 | |||
715 | /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */ | ||
716 | static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable) | ||
717 | { | ||
718 | u32 val; | ||
719 | |||
720 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | ||
721 | |||
722 | if (enable) | ||
723 | val |= MVNETA_GMAC2_PORT_RGMII; | ||
724 | else | ||
725 | val &= ~MVNETA_GMAC2_PORT_RGMII; | ||
726 | |||
727 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | ||
728 | } | ||
729 | |||
730 | /* Config SGMII port */ | ||
731 | static void mvneta_port_sgmii_config(struct mvneta_port *pp) | ||
732 | { | ||
733 | u32 val; | ||
734 | |||
735 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | ||
736 | val |= MVNETA_GMAC2_PSC_ENABLE; | ||
737 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | ||
738 | |||
739 | mvreg_write(pp, MVNETA_SGMII_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | ||
740 | } | ||
741 | |||
742 | /* Start the Ethernet port RX and TX activity */ | 715 | /* Start the Ethernet port RX and TX activity */ |
743 | static void mvneta_port_up(struct mvneta_port *pp) | 716 | static void mvneta_port_up(struct mvneta_port *pp) |
744 | { | 717 | { |
@@ -2756,12 +2729,15 @@ static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) | |||
2756 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | 2729 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); |
2757 | 2730 | ||
2758 | if (phy_mode == PHY_INTERFACE_MODE_SGMII) | 2731 | if (phy_mode == PHY_INTERFACE_MODE_SGMII) |
2759 | mvneta_port_sgmii_config(pp); | 2732 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); |
2733 | else | ||
2734 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_RGMII_SERDES_PROTO); | ||
2735 | |||
2736 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | ||
2760 | 2737 | ||
2761 | mvneta_gmac_rgmii_set(pp, 1); | 2738 | val |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; |
2762 | 2739 | ||
2763 | /* Cancel Port Reset */ | 2740 | /* Cancel Port Reset */ |
2764 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | ||
2765 | val &= ~MVNETA_GMAC2_PORT_RESET; | 2741 | val &= ~MVNETA_GMAC2_PORT_RESET; |
2766 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | 2742 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); |
2767 | 2743 | ||
@@ -2774,6 +2750,7 @@ static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) | |||
2774 | static int mvneta_probe(struct platform_device *pdev) | 2750 | static int mvneta_probe(struct platform_device *pdev) |
2775 | { | 2751 | { |
2776 | const struct mbus_dram_target_info *dram_target_info; | 2752 | const struct mbus_dram_target_info *dram_target_info; |
2753 | struct resource *res; | ||
2777 | struct device_node *dn = pdev->dev.of_node; | 2754 | struct device_node *dn = pdev->dev.of_node; |
2778 | struct device_node *phy_node; | 2755 | struct device_node *phy_node; |
2779 | u32 phy_addr; | 2756 | u32 phy_addr; |
@@ -2838,9 +2815,15 @@ static int mvneta_probe(struct platform_device *pdev) | |||
2838 | 2815 | ||
2839 | clk_prepare_enable(pp->clk); | 2816 | clk_prepare_enable(pp->clk); |
2840 | 2817 | ||
2841 | pp->base = of_iomap(dn, 0); | 2818 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2819 | if (!res) { | ||
2820 | err = -ENODEV; | ||
2821 | goto err_clk; | ||
2822 | } | ||
2823 | |||
2824 | pp->base = devm_ioremap_resource(&pdev->dev, res); | ||
2842 | if (pp->base == NULL) { | 2825 | if (pp->base == NULL) { |
2843 | err = -ENOMEM; | 2826 | err = PTR_ERR(pp->base); |
2844 | goto err_clk; | 2827 | goto err_clk; |
2845 | } | 2828 | } |
2846 | 2829 | ||
@@ -2848,7 +2831,7 @@ static int mvneta_probe(struct platform_device *pdev) | |||
2848 | pp->stats = alloc_percpu(struct mvneta_pcpu_stats); | 2831 | pp->stats = alloc_percpu(struct mvneta_pcpu_stats); |
2849 | if (!pp->stats) { | 2832 | if (!pp->stats) { |
2850 | err = -ENOMEM; | 2833 | err = -ENOMEM; |
2851 | goto err_unmap; | 2834 | goto err_clk; |
2852 | } | 2835 | } |
2853 | 2836 | ||
2854 | for_each_possible_cpu(cpu) { | 2837 | for_each_possible_cpu(cpu) { |
@@ -2913,8 +2896,6 @@ err_deinit: | |||
2913 | mvneta_deinit(pp); | 2896 | mvneta_deinit(pp); |
2914 | err_free_stats: | 2897 | err_free_stats: |
2915 | free_percpu(pp->stats); | 2898 | free_percpu(pp->stats); |
2916 | err_unmap: | ||
2917 | iounmap(pp->base); | ||
2918 | err_clk: | 2899 | err_clk: |
2919 | clk_disable_unprepare(pp->clk); | 2900 | clk_disable_unprepare(pp->clk); |
2920 | err_free_irq: | 2901 | err_free_irq: |
@@ -2934,7 +2915,6 @@ static int mvneta_remove(struct platform_device *pdev) | |||
2934 | mvneta_deinit(pp); | 2915 | mvneta_deinit(pp); |
2935 | clk_disable_unprepare(pp->clk); | 2916 | clk_disable_unprepare(pp->clk); |
2936 | free_percpu(pp->stats); | 2917 | free_percpu(pp->stats); |
2937 | iounmap(pp->base); | ||
2938 | irq_dispose_mapping(dev->irq); | 2918 | irq_dispose_mapping(dev->irq); |
2939 | free_netdev(dev); | 2919 | free_netdev(dev); |
2940 | 2920 | ||