diff options
Diffstat (limited to 'drivers/net/ethernet/intel/igb/e1000_i210.c')
-rw-r--r-- | drivers/net/ethernet/intel/igb/e1000_i210.c | 134 |
1 files changed, 66 insertions, 68 deletions
diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.c b/drivers/net/ethernet/intel/igb/e1000_i210.c index f67f8a170b90..337161f440dd 100644 --- a/drivers/net/ethernet/intel/igb/e1000_i210.c +++ b/drivers/net/ethernet/intel/igb/e1000_i210.c | |||
@@ -1,28 +1,25 @@ | |||
1 | /******************************************************************************* | 1 | /* Intel(R) Gigabit Ethernet Linux driver |
2 | 2 | * Copyright(c) 2007-2014 Intel Corporation. | |
3 | Intel(R) Gigabit Ethernet Linux driver | 3 | * |
4 | Copyright(c) 2007-2014 Intel Corporation. | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | 5 | * under the terms and conditions of the GNU General Public License, | |
6 | This program is free software; you can redistribute it and/or modify it | 6 | * version 2, as published by the Free Software Foundation. |
7 | under the terms and conditions of the GNU General Public License, | 7 | * |
8 | version 2, as published by the Free Software Foundation. | 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
9 | 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | This program is distributed in the hope it will be useful, but WITHOUT | 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 11 | * more details. |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | 12 | * |
13 | more details. | 13 | * You should have received a copy of the GNU General Public License along with |
14 | 14 | * this program; if not, see <http://www.gnu.org/licenses/>. | |
15 | You should have received a copy of the GNU General Public License along with | 15 | * |
16 | this program; if not, see <http://www.gnu.org/licenses/>. | 16 | * The full GNU General Public License is included in this distribution in |
17 | 17 | * the file called "COPYING". | |
18 | The full GNU General Public License is included in this distribution in | 18 | * |
19 | the file called "COPYING". | 19 | * Contact Information: |
20 | 20 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
21 | Contact Information: | 21 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
22 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | 22 | */ |
23 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | ||
24 | |||
25 | ******************************************************************************/ | ||
26 | 23 | ||
27 | /* e1000_i210 | 24 | /* e1000_i210 |
28 | * e1000_i211 | 25 | * e1000_i211 |
@@ -100,7 +97,7 @@ static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw) | |||
100 | return -E1000_ERR_NVM; | 97 | return -E1000_ERR_NVM; |
101 | } | 98 | } |
102 | 99 | ||
103 | return E1000_SUCCESS; | 100 | return 0; |
104 | } | 101 | } |
105 | 102 | ||
106 | /** | 103 | /** |
@@ -142,7 +139,7 @@ s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) | |||
142 | u32 swfw_sync; | 139 | u32 swfw_sync; |
143 | u32 swmask = mask; | 140 | u32 swmask = mask; |
144 | u32 fwmask = mask << 16; | 141 | u32 fwmask = mask << 16; |
145 | s32 ret_val = E1000_SUCCESS; | 142 | s32 ret_val = 0; |
146 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ | 143 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ |
147 | 144 | ||
148 | while (i < timeout) { | 145 | while (i < timeout) { |
@@ -187,7 +184,7 @@ void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) | |||
187 | { | 184 | { |
188 | u32 swfw_sync; | 185 | u32 swfw_sync; |
189 | 186 | ||
190 | while (igb_get_hw_semaphore_i210(hw) != E1000_SUCCESS) | 187 | while (igb_get_hw_semaphore_i210(hw)) |
191 | ; /* Empty */ | 188 | ; /* Empty */ |
192 | 189 | ||
193 | swfw_sync = rd32(E1000_SW_FW_SYNC); | 190 | swfw_sync = rd32(E1000_SW_FW_SYNC); |
@@ -210,7 +207,7 @@ void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) | |||
210 | static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, | 207 | static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, |
211 | u16 *data) | 208 | u16 *data) |
212 | { | 209 | { |
213 | s32 status = E1000_SUCCESS; | 210 | s32 status = 0; |
214 | u16 i, count; | 211 | u16 i, count; |
215 | 212 | ||
216 | /* We cannot hold synchronization semaphores for too long, | 213 | /* We cannot hold synchronization semaphores for too long, |
@@ -220,7 +217,7 @@ static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, | |||
220 | for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) { | 217 | for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) { |
221 | count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ? | 218 | count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ? |
222 | E1000_EERD_EEWR_MAX_COUNT : (words - i); | 219 | E1000_EERD_EEWR_MAX_COUNT : (words - i); |
223 | if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) { | 220 | if (!(hw->nvm.ops.acquire(hw))) { |
224 | status = igb_read_nvm_eerd(hw, offset, count, | 221 | status = igb_read_nvm_eerd(hw, offset, count, |
225 | data + i); | 222 | data + i); |
226 | hw->nvm.ops.release(hw); | 223 | hw->nvm.ops.release(hw); |
@@ -228,7 +225,7 @@ static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, | |||
228 | status = E1000_ERR_SWFW_SYNC; | 225 | status = E1000_ERR_SWFW_SYNC; |
229 | } | 226 | } |
230 | 227 | ||
231 | if (status != E1000_SUCCESS) | 228 | if (status) |
232 | break; | 229 | break; |
233 | } | 230 | } |
234 | 231 | ||
@@ -253,7 +250,7 @@ static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, | |||
253 | struct e1000_nvm_info *nvm = &hw->nvm; | 250 | struct e1000_nvm_info *nvm = &hw->nvm; |
254 | u32 i, k, eewr = 0; | 251 | u32 i, k, eewr = 0; |
255 | u32 attempts = 100000; | 252 | u32 attempts = 100000; |
256 | s32 ret_val = E1000_SUCCESS; | 253 | s32 ret_val = 0; |
257 | 254 | ||
258 | /* A check for invalid values: offset too large, too many words, | 255 | /* A check for invalid values: offset too large, too many words, |
259 | * too many words for the offset, and not enough words. | 256 | * too many words for the offset, and not enough words. |
@@ -275,13 +272,13 @@ static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, | |||
275 | for (k = 0; k < attempts; k++) { | 272 | for (k = 0; k < attempts; k++) { |
276 | if (E1000_NVM_RW_REG_DONE & | 273 | if (E1000_NVM_RW_REG_DONE & |
277 | rd32(E1000_SRWR)) { | 274 | rd32(E1000_SRWR)) { |
278 | ret_val = E1000_SUCCESS; | 275 | ret_val = 0; |
279 | break; | 276 | break; |
280 | } | 277 | } |
281 | udelay(5); | 278 | udelay(5); |
282 | } | 279 | } |
283 | 280 | ||
284 | if (ret_val != E1000_SUCCESS) { | 281 | if (ret_val) { |
285 | hw_dbg("Shadow RAM write EEWR timed out\n"); | 282 | hw_dbg("Shadow RAM write EEWR timed out\n"); |
286 | break; | 283 | break; |
287 | } | 284 | } |
@@ -310,7 +307,7 @@ out: | |||
310 | static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words, | 307 | static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words, |
311 | u16 *data) | 308 | u16 *data) |
312 | { | 309 | { |
313 | s32 status = E1000_SUCCESS; | 310 | s32 status = 0; |
314 | u16 i, count; | 311 | u16 i, count; |
315 | 312 | ||
316 | /* We cannot hold synchronization semaphores for too long, | 313 | /* We cannot hold synchronization semaphores for too long, |
@@ -320,7 +317,7 @@ static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words, | |||
320 | for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) { | 317 | for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) { |
321 | count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ? | 318 | count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ? |
322 | E1000_EERD_EEWR_MAX_COUNT : (words - i); | 319 | E1000_EERD_EEWR_MAX_COUNT : (words - i); |
323 | if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) { | 320 | if (!(hw->nvm.ops.acquire(hw))) { |
324 | status = igb_write_nvm_srwr(hw, offset, count, | 321 | status = igb_write_nvm_srwr(hw, offset, count, |
325 | data + i); | 322 | data + i); |
326 | hw->nvm.ops.release(hw); | 323 | hw->nvm.ops.release(hw); |
@@ -328,7 +325,7 @@ static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words, | |||
328 | status = E1000_ERR_SWFW_SYNC; | 325 | status = E1000_ERR_SWFW_SYNC; |
329 | } | 326 | } |
330 | 327 | ||
331 | if (status != E1000_SUCCESS) | 328 | if (status) |
332 | break; | 329 | break; |
333 | } | 330 | } |
334 | 331 | ||
@@ -367,12 +364,12 @@ static s32 igb_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data) | |||
367 | *data = INVM_DWORD_TO_WORD_DATA(invm_dword); | 364 | *data = INVM_DWORD_TO_WORD_DATA(invm_dword); |
368 | hw_dbg("Read INVM Word 0x%02x = %x\n", | 365 | hw_dbg("Read INVM Word 0x%02x = %x\n", |
369 | address, *data); | 366 | address, *data); |
370 | status = E1000_SUCCESS; | 367 | status = 0; |
371 | break; | 368 | break; |
372 | } | 369 | } |
373 | } | 370 | } |
374 | } | 371 | } |
375 | if (status != E1000_SUCCESS) | 372 | if (status) |
376 | hw_dbg("Requested word 0x%02x not found in OTP\n", address); | 373 | hw_dbg("Requested word 0x%02x not found in OTP\n", address); |
377 | return status; | 374 | return status; |
378 | } | 375 | } |
@@ -388,7 +385,7 @@ static s32 igb_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data) | |||
388 | static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset, | 385 | static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset, |
389 | u16 words __always_unused, u16 *data) | 386 | u16 words __always_unused, u16 *data) |
390 | { | 387 | { |
391 | s32 ret_val = E1000_SUCCESS; | 388 | s32 ret_val = 0; |
392 | 389 | ||
393 | /* Only the MAC addr is required to be present in the iNVM */ | 390 | /* Only the MAC addr is required to be present in the iNVM */ |
394 | switch (offset) { | 391 | switch (offset) { |
@@ -398,43 +395,44 @@ static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset, | |||
398 | &data[1]); | 395 | &data[1]); |
399 | ret_val |= igb_read_invm_word_i210(hw, (u8)offset+2, | 396 | ret_val |= igb_read_invm_word_i210(hw, (u8)offset+2, |
400 | &data[2]); | 397 | &data[2]); |
401 | if (ret_val != E1000_SUCCESS) | 398 | if (ret_val) |
402 | hw_dbg("MAC Addr not found in iNVM\n"); | 399 | hw_dbg("MAC Addr not found in iNVM\n"); |
403 | break; | 400 | break; |
404 | case NVM_INIT_CTRL_2: | 401 | case NVM_INIT_CTRL_2: |
405 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); | 402 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
406 | if (ret_val != E1000_SUCCESS) { | 403 | if (ret_val) { |
407 | *data = NVM_INIT_CTRL_2_DEFAULT_I211; | 404 | *data = NVM_INIT_CTRL_2_DEFAULT_I211; |
408 | ret_val = E1000_SUCCESS; | 405 | ret_val = 0; |
409 | } | 406 | } |
410 | break; | 407 | break; |
411 | case NVM_INIT_CTRL_4: | 408 | case NVM_INIT_CTRL_4: |
412 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); | 409 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
413 | if (ret_val != E1000_SUCCESS) { | 410 | if (ret_val) { |
414 | *data = NVM_INIT_CTRL_4_DEFAULT_I211; | 411 | *data = NVM_INIT_CTRL_4_DEFAULT_I211; |
415 | ret_val = E1000_SUCCESS; | 412 | ret_val = 0; |
416 | } | 413 | } |
417 | break; | 414 | break; |
418 | case NVM_LED_1_CFG: | 415 | case NVM_LED_1_CFG: |
419 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); | 416 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
420 | if (ret_val != E1000_SUCCESS) { | 417 | if (ret_val) { |
421 | *data = NVM_LED_1_CFG_DEFAULT_I211; | 418 | *data = NVM_LED_1_CFG_DEFAULT_I211; |
422 | ret_val = E1000_SUCCESS; | 419 | ret_val = 0; |
423 | } | 420 | } |
424 | break; | 421 | break; |
425 | case NVM_LED_0_2_CFG: | 422 | case NVM_LED_0_2_CFG: |
426 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); | 423 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
427 | if (ret_val != E1000_SUCCESS) { | 424 | if (ret_val) { |
428 | *data = NVM_LED_0_2_CFG_DEFAULT_I211; | 425 | *data = NVM_LED_0_2_CFG_DEFAULT_I211; |
429 | ret_val = E1000_SUCCESS; | 426 | ret_val = 0; |
430 | } | 427 | } |
431 | break; | 428 | break; |
432 | case NVM_ID_LED_SETTINGS: | 429 | case NVM_ID_LED_SETTINGS: |
433 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); | 430 | ret_val = igb_read_invm_word_i210(hw, (u8)offset, data); |
434 | if (ret_val != E1000_SUCCESS) { | 431 | if (ret_val) { |
435 | *data = ID_LED_RESERVED_FFFF; | 432 | *data = ID_LED_RESERVED_FFFF; |
436 | ret_val = E1000_SUCCESS; | 433 | ret_val = 0; |
437 | } | 434 | } |
435 | break; | ||
438 | case NVM_SUB_DEV_ID: | 436 | case NVM_SUB_DEV_ID: |
439 | *data = hw->subsystem_device_id; | 437 | *data = hw->subsystem_device_id; |
440 | break; | 438 | break; |
@@ -488,14 +486,14 @@ s32 igb_read_invm_version(struct e1000_hw *hw, | |||
488 | /* Check if we have first version location used */ | 486 | /* Check if we have first version location used */ |
489 | if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) { | 487 | if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) { |
490 | version = 0; | 488 | version = 0; |
491 | status = E1000_SUCCESS; | 489 | status = 0; |
492 | break; | 490 | break; |
493 | } | 491 | } |
494 | /* Check if we have second version location used */ | 492 | /* Check if we have second version location used */ |
495 | else if ((i == 1) && | 493 | else if ((i == 1) && |
496 | ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) { | 494 | ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) { |
497 | version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3; | 495 | version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3; |
498 | status = E1000_SUCCESS; | 496 | status = 0; |
499 | break; | 497 | break; |
500 | } | 498 | } |
501 | /* Check if we have odd version location | 499 | /* Check if we have odd version location |
@@ -506,7 +504,7 @@ s32 igb_read_invm_version(struct e1000_hw *hw, | |||
506 | (i != 1))) { | 504 | (i != 1))) { |
507 | version = (*next_record & E1000_INVM_VER_FIELD_TWO) | 505 | version = (*next_record & E1000_INVM_VER_FIELD_TWO) |
508 | >> 13; | 506 | >> 13; |
509 | status = E1000_SUCCESS; | 507 | status = 0; |
510 | break; | 508 | break; |
511 | } | 509 | } |
512 | /* Check if we have even version location | 510 | /* Check if we have even version location |
@@ -515,12 +513,12 @@ s32 igb_read_invm_version(struct e1000_hw *hw, | |||
515 | else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) && | 513 | else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) && |
516 | ((*record & 0x3) == 0)) { | 514 | ((*record & 0x3) == 0)) { |
517 | version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3; | 515 | version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3; |
518 | status = E1000_SUCCESS; | 516 | status = 0; |
519 | break; | 517 | break; |
520 | } | 518 | } |
521 | } | 519 | } |
522 | 520 | ||
523 | if (status == E1000_SUCCESS) { | 521 | if (!status) { |
524 | invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK) | 522 | invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK) |
525 | >> E1000_INVM_MAJOR_SHIFT; | 523 | >> E1000_INVM_MAJOR_SHIFT; |
526 | invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK; | 524 | invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK; |
@@ -533,7 +531,7 @@ s32 igb_read_invm_version(struct e1000_hw *hw, | |||
533 | /* Check if we have image type in first location used */ | 531 | /* Check if we have image type in first location used */ |
534 | if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) { | 532 | if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) { |
535 | invm_ver->invm_img_type = 0; | 533 | invm_ver->invm_img_type = 0; |
536 | status = E1000_SUCCESS; | 534 | status = 0; |
537 | break; | 535 | break; |
538 | } | 536 | } |
539 | /* Check if we have image type in first location used */ | 537 | /* Check if we have image type in first location used */ |
@@ -542,7 +540,7 @@ s32 igb_read_invm_version(struct e1000_hw *hw, | |||
542 | ((((*record & 0x3) != 0) && (i != 1)))) { | 540 | ((((*record & 0x3) != 0) && (i != 1)))) { |
543 | invm_ver->invm_img_type = | 541 | invm_ver->invm_img_type = |
544 | (*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23; | 542 | (*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23; |
545 | status = E1000_SUCCESS; | 543 | status = 0; |
546 | break; | 544 | break; |
547 | } | 545 | } |
548 | } | 546 | } |
@@ -558,10 +556,10 @@ s32 igb_read_invm_version(struct e1000_hw *hw, | |||
558 | **/ | 556 | **/ |
559 | static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw) | 557 | static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw) |
560 | { | 558 | { |
561 | s32 status = E1000_SUCCESS; | 559 | s32 status = 0; |
562 | s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *); | 560 | s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *); |
563 | 561 | ||
564 | if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) { | 562 | if (!(hw->nvm.ops.acquire(hw))) { |
565 | 563 | ||
566 | /* Replace the read function with semaphore grabbing with | 564 | /* Replace the read function with semaphore grabbing with |
567 | * the one that skips this for a while. | 565 | * the one that skips this for a while. |
@@ -593,7 +591,7 @@ static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw) | |||
593 | **/ | 591 | **/ |
594 | static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw) | 592 | static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw) |
595 | { | 593 | { |
596 | s32 ret_val = E1000_SUCCESS; | 594 | s32 ret_val = 0; |
597 | u16 checksum = 0; | 595 | u16 checksum = 0; |
598 | u16 i, nvm_data; | 596 | u16 i, nvm_data; |
599 | 597 | ||
@@ -602,12 +600,12 @@ static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw) | |||
602 | * EEPROM read fails | 600 | * EEPROM read fails |
603 | */ | 601 | */ |
604 | ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data); | 602 | ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data); |
605 | if (ret_val != E1000_SUCCESS) { | 603 | if (ret_val) { |
606 | hw_dbg("EEPROM read failed\n"); | 604 | hw_dbg("EEPROM read failed\n"); |
607 | goto out; | 605 | goto out; |
608 | } | 606 | } |
609 | 607 | ||
610 | if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) { | 608 | if (!(hw->nvm.ops.acquire(hw))) { |
611 | /* Do not use hw->nvm.ops.write, hw->nvm.ops.read | 609 | /* Do not use hw->nvm.ops.write, hw->nvm.ops.read |
612 | * because we do not want to take the synchronization | 610 | * because we do not want to take the synchronization |
613 | * semaphores twice here. | 611 | * semaphores twice here. |
@@ -625,7 +623,7 @@ static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw) | |||
625 | checksum = (u16) NVM_SUM - checksum; | 623 | checksum = (u16) NVM_SUM - checksum; |
626 | ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, | 624 | ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, |
627 | &checksum); | 625 | &checksum); |
628 | if (ret_val != E1000_SUCCESS) { | 626 | if (ret_val) { |
629 | hw->nvm.ops.release(hw); | 627 | hw->nvm.ops.release(hw); |
630 | hw_dbg("NVM Write Error while updating checksum.\n"); | 628 | hw_dbg("NVM Write Error while updating checksum.\n"); |
631 | goto out; | 629 | goto out; |
@@ -654,7 +652,7 @@ static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw) | |||
654 | for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) { | 652 | for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) { |
655 | reg = rd32(E1000_EECD); | 653 | reg = rd32(E1000_EECD); |
656 | if (reg & E1000_EECD_FLUDONE_I210) { | 654 | if (reg & E1000_EECD_FLUDONE_I210) { |
657 | ret_val = E1000_SUCCESS; | 655 | ret_val = 0; |
658 | break; | 656 | break; |
659 | } | 657 | } |
660 | udelay(5); | 658 | udelay(5); |
@@ -687,7 +685,7 @@ bool igb_get_flash_presence_i210(struct e1000_hw *hw) | |||
687 | **/ | 685 | **/ |
688 | static s32 igb_update_flash_i210(struct e1000_hw *hw) | 686 | static s32 igb_update_flash_i210(struct e1000_hw *hw) |
689 | { | 687 | { |
690 | s32 ret_val = E1000_SUCCESS; | 688 | s32 ret_val = 0; |
691 | u32 flup; | 689 | u32 flup; |
692 | 690 | ||
693 | ret_val = igb_pool_flash_update_done_i210(hw); | 691 | ret_val = igb_pool_flash_update_done_i210(hw); |
@@ -700,7 +698,7 @@ static s32 igb_update_flash_i210(struct e1000_hw *hw) | |||
700 | wr32(E1000_EECD, flup); | 698 | wr32(E1000_EECD, flup); |
701 | 699 | ||
702 | ret_val = igb_pool_flash_update_done_i210(hw); | 700 | ret_val = igb_pool_flash_update_done_i210(hw); |
703 | if (ret_val == E1000_SUCCESS) | 701 | if (ret_val) |
704 | hw_dbg("Flash update complete\n"); | 702 | hw_dbg("Flash update complete\n"); |
705 | else | 703 | else |
706 | hw_dbg("Flash update time out\n"); | 704 | hw_dbg("Flash update time out\n"); |
@@ -753,7 +751,7 @@ out: | |||
753 | static s32 __igb_access_xmdio_reg(struct e1000_hw *hw, u16 address, | 751 | static s32 __igb_access_xmdio_reg(struct e1000_hw *hw, u16 address, |
754 | u8 dev_addr, u16 *data, bool read) | 752 | u8 dev_addr, u16 *data, bool read) |
755 | { | 753 | { |
756 | s32 ret_val = E1000_SUCCESS; | 754 | s32 ret_val = 0; |
757 | 755 | ||
758 | ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); | 756 | ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); |
759 | if (ret_val) | 757 | if (ret_val) |