1 files changed, 45 insertions, 55 deletions
diff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h
index b05bf925ac72..2a8bb35c2df2 100644
--- a/drivers/net/ethernet/intel/igb/e1000_defines.h
+++ b/drivers/net/ethernet/intel/igb/e1000_defines.h
@@ -1,28 +1,25 @@
-/*******************************************************************************
+/* Intel(R) Gigabit Ethernet Linux driver
+ * Copyright(c) 2007-2014 Intel Corporation.
-  Intel(R) Gigabit Ethernet Linux driver
+ *
-  Copyright(c) 2007-2014 Intel Corporation.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
-  This program is free software; you can redistribute it and/or modify it
+ * version 2, as published by the Free Software Foundation.
-  under the terms and conditions of the GNU General Public License,
+ *
-  version 2, as published by the Free Software Foundation.
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-  This program is distributed in the hope it will be useful, but WITHOUT
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * more details.
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ *
-  more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, see <http://www.gnu.org/licenses/>.
-  You should have received a copy of the GNU General Public License along with
+ *
-  this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
-  The full GNU General Public License is included in this distribution in
+ *
-  the file called "COPYING".
+ * Contact Information:
+ * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
-  Contact Information:
+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+ */
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-*******************************************************************************/
 #ifndef _E1000_DEFINES_H_
 #define _E1000_DEFINES_H_
@@ -101,11 +98,11 @@
 /* Same mask, but for extended and packet split descriptors */
 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
-    E1000_RXDEXT_STATERR_CE  |            \
+        E1000_RXDEXT_STATERR_CE  |            \
-    E1000_RXDEXT_STATERR_SE  |            \
+        E1000_RXDEXT_STATERR_SE  |            \
-    E1000_RXDEXT_STATERR_SEQ |            \
+        E1000_RXDEXT_STATERR_SEQ |            \
-    E1000_RXDEXT_STATERR_CXE |            \
+        E1000_RXDEXT_STATERR_CXE |            \
-    E1000_RXDEXT_STATERR_RXE)
+        E1000_RXDEXT_STATERR_RXE)
 #define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
 #define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
@@ -307,39 +304,34 @@
 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
 /* DMA Coalescing register fields */
-#define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coalescing
+#define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coal Watchdog Timer */
-                                                        * Watchdog Timer */
+#define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coal Rx Threshold */
-#define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coalescing Receive
-                                                        * Threshold */
 #define E1000_DMACR_DMACTHR_SHIFT       16
-#define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe
+#define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe trans */
-                                                        * transactions */
 #define E1000_DMACR_DMAC_LX_SHIFT       28
 #define E1000_DMACR_DMAC_EN             0x80000000 /* Enable DMA Coalescing */
 /* DMA Coalescing BMC-to-OS Watchdog Enable */
 #define E1000_DMACR_DC_BMC2OSW_EN       0x00008000
-#define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coalescing Transmit
+#define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coal Tx Threshold */
-                                                        * Threshold */
 #define E1000_DMCTLX_TTLX_MASK          0x00000FFF /* Time to LX request */
-#define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Receive Traffic Rate
+#define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Rx Traffic Rate Thresh */
-                                                        * Threshold */
+#define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rx pkt rate curr window */
-#define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rcv packet rate in
-                                                        * current window */
-#define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rcv Traffic
+#define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rx Current Cnt */
-                                                        * Current Cnt */
-#define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* Flow ctrl Rcv Threshold
+#define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* FC Rx Thresh High val */
-                                                        * High val */
 #define E1000_FCRTC_RTH_COAL_SHIFT      4
 #define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision */
 /* Timestamp in Rx buffer */
 #define E1000_RXPBS_CFG_TS_EN           0x80000000
+#define I210_RXPBSIZE_DEFAULT           0x000000A2 /* RXPBSIZE default */
+#define I210_TXPBSIZE_DEFAULT           0x04000014 /* TXPBSIZE default */
 /* SerDes Control */
 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
@@ -406,12 +398,12 @@
 *   o LSC    = Link Status Change
 */
 #define IMS_ENABLE_MASK ( \
-    E1000_IMS_RXT0   |    \
+        E1000_IMS_RXT0   |    \
-    E1000_IMS_TXDW   |    \
+        E1000_IMS_TXDW   |    \
-    E1000_IMS_RXDMT0 |    \
+        E1000_IMS_RXDMT0 |    \
-    E1000_IMS_RXSEQ  |    \
+        E1000_IMS_RXSEQ  |    \
-    E1000_IMS_LSC    |    \
+        E1000_IMS_LSC    |    \
-    E1000_IMS_DOUTSYNC)
+        E1000_IMS_DOUTSYNC)
 /* Interrupt Mask Set */
 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
@@ -467,7 +459,6 @@
 #define E1000_RAH_POOL_1 0x00040000
 /* Error Codes */
-#define E1000_SUCCESS      0
 #define E1000_ERR_NVM      1
 #define E1000_ERR_PHY      2
 #define E1000_ERR_CONFIG   3
@@ -1011,8 +1002,7 @@
 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
 /* DMA Coalescing register fields */
-#define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision based
+#define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power on DMA coal */
-                                                      on DMA coal */
 /* Tx Rate-Scheduler Config fields */
 #define E1000_RTTBCNRC_RS_ENA           0x80000000

diff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h index b05bf925ac72..2a8bb35c2df2 100644 --- a/drivers/net/ethernet/intel/igb/e1000_defines.h +++ b/drivers/net/ethernet/intel/igb/e1000_defines.h
@@ -1,28 +1,25 @@
1	/*******************************************************************************	1	/* Intel(R) Gigabit Ethernet Linux driver
2		2	* Copyright(c) 2007-2014 Intel Corporation.
3	Intel(R) Gigabit Ethernet Linux driver	3	*
4	Copyright(c) 2007-2014 Intel Corporation.	4	* This program is free software; you can redistribute it and/or modify it
5		5	* under the terms and conditions of the GNU General Public License,
6	This program is free software; you can redistribute it and/or modify it	6	* version 2, as published by the Free Software Foundation.
7	under the terms and conditions of the GNU General Public License,	7	*
8	version 2, as published by the Free Software Foundation.	8	* This program is distributed in the hope it will be useful, but WITHOUT
9		9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10	This program is distributed in the hope it will be useful, but WITHOUT	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or	11	* more details.
12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for	12	*
13	more details.	13	* You should have received a copy of the GNU General Public License along with
14		14	* this program; if not, see <http://www.gnu.org/licenses/>.
15	You should have received a copy of the GNU General Public License along with	15	*
16	this program; if not, see <http://www.gnu.org/licenses/>.	16	* The full GNU General Public License is included in this distribution in
17		17	* the file called "COPYING".
18	The full GNU General Public License is included in this distribution in	18	*
19	the file called "COPYING".	19	* Contact Information:
20		20	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21	Contact Information:	21	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>	22	*/
23	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25	*******************************************************************************/
26		23
27	#ifndef _E1000_DEFINES_H_	24	#ifndef _E1000_DEFINES_H_
28	#define _E1000_DEFINES_H_	25	#define _E1000_DEFINES_H_
@@ -101,11 +98,11 @@
101		98
102	/* Same mask, but for extended and packet split descriptors */	99	/* Same mask, but for extended and packet split descriptors */
103	#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \	100	#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
104	E1000_RXDEXT_STATERR_CE \| \	101	E1000_RXDEXT_STATERR_CE \| \
105	E1000_RXDEXT_STATERR_SE \| \	102	E1000_RXDEXT_STATERR_SE \| \
106	E1000_RXDEXT_STATERR_SEQ \| \	103	E1000_RXDEXT_STATERR_SEQ \| \
107	E1000_RXDEXT_STATERR_CXE \| \	104	E1000_RXDEXT_STATERR_CXE \| \
108	E1000_RXDEXT_STATERR_RXE)	105	E1000_RXDEXT_STATERR_RXE)
109		106
110	#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000	107	#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
111	#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000	108	#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
@@ -307,39 +304,34 @@
307	#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */	304	#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
308		305
309	/* DMA Coalescing register fields */	306	/* DMA Coalescing register fields */
310	#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing	307	#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coal Watchdog Timer */
311	* Watchdog Timer */	308	#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coal Rx Threshold */
312	#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive
313	* Threshold */
314	#define E1000_DMACR_DMACTHR_SHIFT 16	309	#define E1000_DMACR_DMACTHR_SHIFT 16
315	#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe	310	#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe trans */
316	* transactions */
317	#define E1000_DMACR_DMAC_LX_SHIFT 28	311	#define E1000_DMACR_DMAC_LX_SHIFT 28
318	#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */	312	#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
319	/* DMA Coalescing BMC-to-OS Watchdog Enable */	313	/* DMA Coalescing BMC-to-OS Watchdog Enable */
320	#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000	314	#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
321		315
322	#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit	316	#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coal Tx Threshold */
323	* Threshold */
324		317
325	#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */	318	#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
326		319
327	#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate	320	#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate Thresh */
328	* Threshold */	321	#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx pkt rate curr window */
329	#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in
330	* current window */
331		322
332	#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic	323	#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Current Cnt */
333	* Current Cnt */
334		324
335	#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold	325	#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* FC Rx Thresh High val */
336	* High val */
337	#define E1000_FCRTC_RTH_COAL_SHIFT 4	326	#define E1000_FCRTC_RTH_COAL_SHIFT 4
338	#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */	327	#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */
339		328
340	/* Timestamp in Rx buffer */	329	/* Timestamp in Rx buffer */
341	#define E1000_RXPBS_CFG_TS_EN 0x80000000	330	#define E1000_RXPBS_CFG_TS_EN 0x80000000
342		331
		332	#define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
		333	#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
		334
343	/* SerDes Control */	335	/* SerDes Control */
344	#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400	336	#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
345		337
@@ -406,12 +398,12 @@
406	* o LSC = Link Status Change	398	* o LSC = Link Status Change
407	*/	399	*/
408	#define IMS_ENABLE_MASK ( \	400	#define IMS_ENABLE_MASK ( \
409	E1000_IMS_RXT0 \| \	401	E1000_IMS_RXT0 \| \
410	E1000_IMS_TXDW \| \	402	E1000_IMS_TXDW \| \
411	E1000_IMS_RXDMT0 \| \	403	E1000_IMS_RXDMT0 \| \
412	E1000_IMS_RXSEQ \| \	404	E1000_IMS_RXSEQ \| \
413	E1000_IMS_LSC \| \	405	E1000_IMS_LSC \| \
414	E1000_IMS_DOUTSYNC)	406	E1000_IMS_DOUTSYNC)
415		407
416	/* Interrupt Mask Set */	408	/* Interrupt Mask Set */
417	#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */	409	#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -467,7 +459,6 @@
467	#define E1000_RAH_POOL_1 0x00040000	459	#define E1000_RAH_POOL_1 0x00040000
468		460
469	/* Error Codes */	461	/* Error Codes */
470	#define E1000_SUCCESS 0
471	#define E1000_ERR_NVM 1	462	#define E1000_ERR_NVM 1
472	#define E1000_ERR_PHY 2	463	#define E1000_ERR_PHY 2
473	#define E1000_ERR_CONFIG 3	464	#define E1000_ERR_CONFIG 3
@@ -1011,8 +1002,7 @@
1011	#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F	1002	#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
1012		1003
1013	/* DMA Coalescing register fields */	1004	/* DMA Coalescing register fields */
1014	#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based	1005	#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power on DMA coal */
1015	on DMA coal */
1016		1006
1017	/* Tx Rate-Scheduler Config fields */	1007	/* Tx Rate-Scheduler Config fields */
1018	#define E1000_RTTBCNRC_RS_ENA 0x80000000	1008	#define E1000_RTTBCNRC_RS_ENA 0x80000000