diff options
Diffstat (limited to 'drivers/net/ethernet/intel/e1000e/defines.h')
| -rw-r--r-- | drivers/net/ethernet/intel/e1000e/defines.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h index 02a12b69555f..4dab6fc265a2 100644 --- a/drivers/net/ethernet/intel/e1000e/defines.h +++ b/drivers/net/ethernet/intel/e1000e/defines.h | |||
| @@ -232,6 +232,7 @@ | |||
| 232 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | 232 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ |
| 233 | #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ | 233 | #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ |
| 234 | #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ | 234 | #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ |
| 235 | #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ | ||
| 235 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | 236 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
| 236 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | 237 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ |
| 237 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ | 238 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ |
| @@ -389,6 +390,12 @@ | |||
| 389 | 390 | ||
| 390 | #define E1000_PBS_16K E1000_PBA_16K | 391 | #define E1000_PBS_16K E1000_PBA_16K |
| 391 | 392 | ||
| 393 | /* Uncorrectable/correctable ECC Error counts and enable bits */ | ||
| 394 | #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF | ||
| 395 | #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 | ||
| 396 | #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 | ||
| 397 | #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 | ||
| 398 | |||
| 392 | #define IFS_MAX 80 | 399 | #define IFS_MAX 80 |
| 393 | #define IFS_MIN 40 | 400 | #define IFS_MIN 40 |
| 394 | #define IFS_RATIO 4 | 401 | #define IFS_RATIO 4 |
| @@ -408,6 +415,7 @@ | |||
| 408 | #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ | 415 | #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ |
| 409 | #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ | 416 | #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ |
| 410 | #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ | 417 | #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ |
| 418 | #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ | ||
| 411 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ | 419 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ |
| 412 | #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ | 420 | #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ |
| 413 | #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ | 421 | #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ |
| @@ -443,6 +451,7 @@ | |||
| 443 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ | 451 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ |
| 444 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ | 452 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ |
| 445 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ | 453 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ |
| 454 | #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ | ||
| 446 | #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ | 455 | #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ |
| 447 | #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ | 456 | #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ |
| 448 | #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ | 457 | #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ |