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path: root/drivers/net/ethernet/freescale/gianfar.c
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Diffstat (limited to 'drivers/net/ethernet/freescale/gianfar.c')
-rw-r--r--drivers/net/ethernet/freescale/gianfar.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c
index 3f07dbd01980..e28b3e6b12d9 100644
--- a/drivers/net/ethernet/freescale/gianfar.c
+++ b/drivers/net/ethernet/freescale/gianfar.c
@@ -1821,20 +1821,9 @@ void gfar_configure_coalescing(struct gfar_private *priv,
1821{ 1821{
1822 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1822 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1823 u32 __iomem *baddr; 1823 u32 __iomem *baddr;
1824 int i = 0;
1825
1826 /* Backward compatible case ---- even if we enable
1827 * multiple queues, there's only single reg to program
1828 */
1829 gfar_write(&regs->txic, 0);
1830 if (likely(priv->tx_queue[0]->txcoalescing))
1831 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1832
1833 gfar_write(&regs->rxic, 0);
1834 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1835 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1836 1824
1837 if (priv->mode == MQ_MG_MODE) { 1825 if (priv->mode == MQ_MG_MODE) {
1826 int i = 0;
1838 baddr = &regs->txic0; 1827 baddr = &regs->txic0;
1839 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 1828 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1840 gfar_write(baddr + i, 0); 1829 gfar_write(baddr + i, 0);
@@ -1848,6 +1837,17 @@ void gfar_configure_coalescing(struct gfar_private *priv,
1848 if (likely(priv->rx_queue[i]->rxcoalescing)) 1837 if (likely(priv->rx_queue[i]->rxcoalescing))
1849 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 1838 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1850 } 1839 }
1840 } else {
1841 /* Backward compatible case ---- even if we enable
1842 * multiple queues, there's only single reg to program
1843 */
1844 gfar_write(&regs->txic, 0);
1845 if (likely(priv->tx_queue[0]->txcoalescing))
1846 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1847
1848 gfar_write(&regs->rxic, 0);
1849 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1850 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1851 } 1851 }
1852} 1852}
1853 1853