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path: root/drivers/net/ethernet/emulex/benet/be_cmds.c
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Diffstat (limited to 'drivers/net/ethernet/emulex/benet/be_cmds.c')
-rw-r--r--drivers/net/ethernet/emulex/benet/be_cmds.c610
1 files changed, 335 insertions, 275 deletions
diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c
index d1ec15af0d24..f4ea3490f446 100644
--- a/drivers/net/ethernet/emulex/benet/be_cmds.c
+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c
@@ -52,8 +52,7 @@ static struct be_cmd_priv_map cmd_priv_map[] = {
52 } 52 }
53}; 53};
54 54
55static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, 55static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
56 u8 subsystem)
57{ 56{
58 int i; 57 int i;
59 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map); 58 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
@@ -120,21 +119,28 @@ static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
120 return (void *)addr; 119 return (void *)addr;
121} 120}
122 121
123static int be_mcc_compl_process(struct be_adapter *adapter, 122static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
124 struct be_mcc_compl *compl)
125{ 123{
126 u16 compl_status, extd_status; 124 if (base_status == MCC_STATUS_NOT_SUPPORTED ||
127 struct be_cmd_resp_hdr *resp_hdr; 125 base_status == MCC_STATUS_ILLEGAL_REQUEST ||
128 u8 opcode = 0, subsystem = 0; 126 addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
129 127 (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
130 /* Just swap the status to host endian; mcc tag is opaquely copied 128 (base_status == MCC_STATUS_ILLEGAL_FIELD ||
131 * from mcc_wrb */ 129 addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
132 be_dws_le_to_cpu(compl, 4); 130 return true;
133 131 else
134 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & 132 return false;
135 CQE_STATUS_COMPL_MASK; 133}
136 134
137 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1); 135/* Place holder for all the async MCC cmds wherein the caller is not in a busy
136 * loop (has not issued be_mcc_notify_wait())
137 */
138static void be_async_cmd_process(struct be_adapter *adapter,
139 struct be_mcc_compl *compl,
140 struct be_cmd_resp_hdr *resp_hdr)
141{
142 enum mcc_base_status base_status = base_status(compl->status);
143 u8 opcode = 0, subsystem = 0;
138 144
139 if (resp_hdr) { 145 if (resp_hdr) {
140 opcode = resp_hdr->opcode; 146 opcode = resp_hdr->opcode;
@@ -144,61 +150,86 @@ static int be_mcc_compl_process(struct be_adapter *adapter,
144 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST && 150 if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
145 subsystem == CMD_SUBSYSTEM_LOWLEVEL) { 151 subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
146 complete(&adapter->et_cmd_compl); 152 complete(&adapter->et_cmd_compl);
147 return 0; 153 return;
148 } 154 }
149 155
150 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) || 156 if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
151 (opcode == OPCODE_COMMON_WRITE_OBJECT)) && 157 opcode == OPCODE_COMMON_WRITE_OBJECT) &&
152 (subsystem == CMD_SUBSYSTEM_COMMON)) { 158 subsystem == CMD_SUBSYSTEM_COMMON) {
153 adapter->flash_status = compl_status; 159 adapter->flash_status = compl->status;
154 complete(&adapter->et_cmd_compl); 160 complete(&adapter->et_cmd_compl);
161 return;
155 } 162 }
156 163
157 if (compl_status == MCC_STATUS_SUCCESS) { 164 if ((opcode == OPCODE_ETH_GET_STATISTICS ||
158 if (((opcode == OPCODE_ETH_GET_STATISTICS) || 165 opcode == OPCODE_ETH_GET_PPORT_STATS) &&
159 (opcode == OPCODE_ETH_GET_PPORT_STATS)) && 166 subsystem == CMD_SUBSYSTEM_ETH &&
160 (subsystem == CMD_SUBSYSTEM_ETH)) { 167 base_status == MCC_STATUS_SUCCESS) {
161 be_parse_stats(adapter); 168 be_parse_stats(adapter);
162 adapter->stats_cmd_sent = false; 169 adapter->stats_cmd_sent = false;
163 } 170 return;
164 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES && 171 }
165 subsystem == CMD_SUBSYSTEM_COMMON) { 172
173 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
174 subsystem == CMD_SUBSYSTEM_COMMON) {
175 if (base_status == MCC_STATUS_SUCCESS) {
166 struct be_cmd_resp_get_cntl_addnl_attribs *resp = 176 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
167 (void *)resp_hdr; 177 (void *)resp_hdr;
168 adapter->drv_stats.be_on_die_temperature = 178 adapter->drv_stats.be_on_die_temperature =
169 resp->on_die_temperature; 179 resp->on_die_temperature;
170 } 180 } else {
171 } else {
172 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
173 adapter->be_get_temp_freq = 0; 181 adapter->be_get_temp_freq = 0;
182 }
183 return;
184 }
185}
186
187static int be_mcc_compl_process(struct be_adapter *adapter,
188 struct be_mcc_compl *compl)
189{
190 enum mcc_base_status base_status;
191 enum mcc_addl_status addl_status;
192 struct be_cmd_resp_hdr *resp_hdr;
193 u8 opcode = 0, subsystem = 0;
194
195 /* Just swap the status to host endian; mcc tag is opaquely copied
196 * from mcc_wrb */
197 be_dws_le_to_cpu(compl, 4);
198
199 base_status = base_status(compl->status);
200 addl_status = addl_status(compl->status);
201
202 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
203 if (resp_hdr) {
204 opcode = resp_hdr->opcode;
205 subsystem = resp_hdr->subsystem;
206 }
207
208 be_async_cmd_process(adapter, compl, resp_hdr);
174 209
175 if (compl_status == MCC_STATUS_NOT_SUPPORTED || 210 if (base_status != MCC_STATUS_SUCCESS &&
176 compl_status == MCC_STATUS_ILLEGAL_REQUEST) 211 !be_skip_err_log(opcode, base_status, addl_status)) {
177 goto done;
178 212
179 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { 213 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
180 dev_warn(&adapter->pdev->dev, 214 dev_warn(&adapter->pdev->dev,
181 "VF is not privileged to issue opcode %d-%d\n", 215 "VF is not privileged to issue opcode %d-%d\n",
182 opcode, subsystem); 216 opcode, subsystem);
183 } else { 217 } else {
184 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
185 CQE_STATUS_EXTD_MASK;
186 dev_err(&adapter->pdev->dev, 218 dev_err(&adapter->pdev->dev,
187 "opcode %d-%d failed:status %d-%d\n", 219 "opcode %d-%d failed:status %d-%d\n",
188 opcode, subsystem, compl_status, extd_status); 220 opcode, subsystem, base_status, addl_status);
189
190 if (extd_status == MCC_ADDL_STS_INSUFFICIENT_RESOURCES)
191 return extd_status;
192 } 221 }
193 } 222 }
194done: 223 return compl->status;
195 return compl_status;
196} 224}
197 225
198/* Link state evt is a string of bytes; no need for endian swapping */ 226/* Link state evt is a string of bytes; no need for endian swapping */
199static void be_async_link_state_process(struct be_adapter *adapter, 227static void be_async_link_state_process(struct be_adapter *adapter,
200 struct be_async_event_link_state *evt) 228 struct be_mcc_compl *compl)
201{ 229{
230 struct be_async_event_link_state *evt =
231 (struct be_async_event_link_state *)compl;
232
202 /* When link status changes, link speed must be re-queried from FW */ 233 /* When link status changes, link speed must be re-queried from FW */
203 adapter->phy.link_speed = -1; 234 adapter->phy.link_speed = -1;
204 235
@@ -221,8 +252,11 @@ static void be_async_link_state_process(struct be_adapter *adapter,
221 252
222/* Grp5 CoS Priority evt */ 253/* Grp5 CoS Priority evt */
223static void be_async_grp5_cos_priority_process(struct be_adapter *adapter, 254static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
224 struct be_async_event_grp5_cos_priority *evt) 255 struct be_mcc_compl *compl)
225{ 256{
257 struct be_async_event_grp5_cos_priority *evt =
258 (struct be_async_event_grp5_cos_priority *)compl;
259
226 if (evt->valid) { 260 if (evt->valid) {
227 adapter->vlan_prio_bmap = evt->available_priority_bmap; 261 adapter->vlan_prio_bmap = evt->available_priority_bmap;
228 adapter->recommended_prio &= ~VLAN_PRIO_MASK; 262 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
@@ -233,8 +267,11 @@ static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
233 267
234/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */ 268/* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
235static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, 269static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
236 struct be_async_event_grp5_qos_link_speed *evt) 270 struct be_mcc_compl *compl)
237{ 271{
272 struct be_async_event_grp5_qos_link_speed *evt =
273 (struct be_async_event_grp5_qos_link_speed *)compl;
274
238 if (adapter->phy.link_speed >= 0 && 275 if (adapter->phy.link_speed >= 0 &&
239 evt->physical_port == adapter->port_num) 276 evt->physical_port == adapter->port_num)
240 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10; 277 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
@@ -242,8 +279,11 @@ static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
242 279
243/*Grp5 PVID evt*/ 280/*Grp5 PVID evt*/
244static void be_async_grp5_pvid_state_process(struct be_adapter *adapter, 281static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
245 struct be_async_event_grp5_pvid_state *evt) 282 struct be_mcc_compl *compl)
246{ 283{
284 struct be_async_event_grp5_pvid_state *evt =
285 (struct be_async_event_grp5_pvid_state *)compl;
286
247 if (evt->enabled) { 287 if (evt->enabled) {
248 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK; 288 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
249 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid); 289 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
@@ -253,26 +293,21 @@ static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
253} 293}
254 294
255static void be_async_grp5_evt_process(struct be_adapter *adapter, 295static void be_async_grp5_evt_process(struct be_adapter *adapter,
256 u32 trailer, struct be_mcc_compl *evt) 296 struct be_mcc_compl *compl)
257{ 297{
258 u8 event_type = 0; 298 u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
259 299 ASYNC_EVENT_TYPE_MASK;
260 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
261 ASYNC_TRAILER_EVENT_TYPE_MASK;
262 300
263 switch (event_type) { 301 switch (event_type) {
264 case ASYNC_EVENT_COS_PRIORITY: 302 case ASYNC_EVENT_COS_PRIORITY:
265 be_async_grp5_cos_priority_process(adapter, 303 be_async_grp5_cos_priority_process(adapter, compl);
266 (struct be_async_event_grp5_cos_priority *)evt); 304 break;
267 break;
268 case ASYNC_EVENT_QOS_SPEED: 305 case ASYNC_EVENT_QOS_SPEED:
269 be_async_grp5_qos_speed_process(adapter, 306 be_async_grp5_qos_speed_process(adapter, compl);
270 (struct be_async_event_grp5_qos_link_speed *)evt); 307 break;
271 break;
272 case ASYNC_EVENT_PVID_STATE: 308 case ASYNC_EVENT_PVID_STATE:
273 be_async_grp5_pvid_state_process(adapter, 309 be_async_grp5_pvid_state_process(adapter, compl);
274 (struct be_async_event_grp5_pvid_state *)evt); 310 break;
275 break;
276 default: 311 default:
277 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n", 312 dev_warn(&adapter->pdev->dev, "Unknown grp5 event 0x%x!\n",
278 event_type); 313 event_type);
@@ -281,13 +316,13 @@ static void be_async_grp5_evt_process(struct be_adapter *adapter,
281} 316}
282 317
283static void be_async_dbg_evt_process(struct be_adapter *adapter, 318static void be_async_dbg_evt_process(struct be_adapter *adapter,
284 u32 trailer, struct be_mcc_compl *cmp) 319 struct be_mcc_compl *cmp)
285{ 320{
286 u8 event_type = 0; 321 u8 event_type = 0;
287 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp; 322 struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
288 323
289 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) & 324 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
290 ASYNC_TRAILER_EVENT_TYPE_MASK; 325 ASYNC_EVENT_TYPE_MASK;
291 326
292 switch (event_type) { 327 switch (event_type) {
293 case ASYNC_DEBUG_EVENT_TYPE_QNQ: 328 case ASYNC_DEBUG_EVENT_TYPE_QNQ:
@@ -302,25 +337,33 @@ static void be_async_dbg_evt_process(struct be_adapter *adapter,
302 } 337 }
303} 338}
304 339
305static inline bool is_link_state_evt(u32 trailer) 340static inline bool is_link_state_evt(u32 flags)
306{ 341{
307 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 342 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
308 ASYNC_TRAILER_EVENT_CODE_MASK) == 343 ASYNC_EVENT_CODE_LINK_STATE;
309 ASYNC_EVENT_CODE_LINK_STATE;
310} 344}
311 345
312static inline bool is_grp5_evt(u32 trailer) 346static inline bool is_grp5_evt(u32 flags)
313{ 347{
314 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 348 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
315 ASYNC_TRAILER_EVENT_CODE_MASK) == 349 ASYNC_EVENT_CODE_GRP_5;
316 ASYNC_EVENT_CODE_GRP_5);
317} 350}
318 351
319static inline bool is_dbg_evt(u32 trailer) 352static inline bool is_dbg_evt(u32 flags)
320{ 353{
321 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 354 return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
322 ASYNC_TRAILER_EVENT_CODE_MASK) == 355 ASYNC_EVENT_CODE_QNQ;
323 ASYNC_EVENT_CODE_QNQ); 356}
357
358static void be_mcc_event_process(struct be_adapter *adapter,
359 struct be_mcc_compl *compl)
360{
361 if (is_link_state_evt(compl->flags))
362 be_async_link_state_process(adapter, compl);
363 else if (is_grp5_evt(compl->flags))
364 be_async_grp5_evt_process(adapter, compl);
365 else if (is_dbg_evt(compl->flags))
366 be_async_dbg_evt_process(adapter, compl);
324} 367}
325 368
326static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) 369static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
@@ -362,21 +405,13 @@ int be_process_mcc(struct be_adapter *adapter)
362 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; 405 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
363 406
364 spin_lock(&adapter->mcc_cq_lock); 407 spin_lock(&adapter->mcc_cq_lock);
408
365 while ((compl = be_mcc_compl_get(adapter))) { 409 while ((compl = be_mcc_compl_get(adapter))) {
366 if (compl->flags & CQE_FLAGS_ASYNC_MASK) { 410 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
367 /* Interpret flags as an async trailer */ 411 be_mcc_event_process(adapter, compl);
368 if (is_link_state_evt(compl->flags))
369 be_async_link_state_process(adapter,
370 (struct be_async_event_link_state *) compl);
371 else if (is_grp5_evt(compl->flags))
372 be_async_grp5_evt_process(adapter,
373 compl->flags, compl);
374 else if (is_dbg_evt(compl->flags))
375 be_async_dbg_evt_process(adapter,
376 compl->flags, compl);
377 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 412 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
378 status = be_mcc_compl_process(adapter, compl); 413 status = be_mcc_compl_process(adapter, compl);
379 atomic_dec(&mcc_obj->q.used); 414 atomic_dec(&mcc_obj->q.used);
380 } 415 }
381 be_mcc_compl_use(compl); 416 be_mcc_compl_use(compl);
382 num++; 417 num++;
@@ -436,7 +471,9 @@ static int be_mcc_notify_wait(struct be_adapter *adapter)
436 if (status == -EIO) 471 if (status == -EIO)
437 goto out; 472 goto out;
438 473
439 status = resp->status; 474 status = (resp->base_status |
475 ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
476 CQE_ADDL_STATUS_SHIFT));
440out: 477out:
441 return status; 478 return status;
442} 479}
@@ -560,10 +597,8 @@ static bool lancer_provisioning_error(struct be_adapter *adapter)
560 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0; 597 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
561 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); 598 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
562 if (sliport_status & SLIPORT_STATUS_ERR_MASK) { 599 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
563 sliport_err1 = ioread32(adapter->db + 600 sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET);
564 SLIPORT_ERROR1_OFFSET); 601 sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET);
565 sliport_err2 = ioread32(adapter->db +
566 SLIPORT_ERROR2_OFFSET);
567 602
568 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 && 603 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
569 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2) 604 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
@@ -630,8 +665,7 @@ int be_fw_wait_ready(struct be_adapter *adapter)
630 if (stage == POST_STAGE_ARMFW_RDY) 665 if (stage == POST_STAGE_ARMFW_RDY)
631 return 0; 666 return 0;
632 667
633 dev_info(dev, "Waiting for POST, %ds elapsed\n", 668 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
634 timeout);
635 if (msleep_interruptible(2000)) { 669 if (msleep_interruptible(2000)) {
636 dev_err(dev, "Waiting for POST aborted\n"); 670 dev_err(dev, "Waiting for POST aborted\n");
637 return -EINTR; 671 return -EINTR;
@@ -649,8 +683,7 @@ static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
649 return &wrb->payload.sgl[0]; 683 return &wrb->payload.sgl[0];
650} 684}
651 685
652static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, 686static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
653 unsigned long addr)
654{ 687{
655 wrb->tag0 = addr & 0xFFFFFFFF; 688 wrb->tag0 = addr & 0xFFFFFFFF;
656 wrb->tag1 = upper_32_bits(addr); 689 wrb->tag1 = upper_32_bits(addr);
@@ -659,8 +692,9 @@ static inline void fill_wrb_tags(struct be_mcc_wrb *wrb,
659/* Don't touch the hdr after it's prepared */ 692/* Don't touch the hdr after it's prepared */
660/* mem will be NULL for embedded commands */ 693/* mem will be NULL for embedded commands */
661static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 694static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
662 u8 subsystem, u8 opcode, int cmd_len, 695 u8 subsystem, u8 opcode, int cmd_len,
663 struct be_mcc_wrb *wrb, struct be_dma_mem *mem) 696 struct be_mcc_wrb *wrb,
697 struct be_dma_mem *mem)
664{ 698{
665 struct be_sge *sge; 699 struct be_sge *sge;
666 700
@@ -683,7 +717,7 @@ static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
683} 717}
684 718
685static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 719static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
686 struct be_dma_mem *mem) 720 struct be_dma_mem *mem)
687{ 721{
688 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); 722 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
689 u64 dma = (u64)mem->dma; 723 u64 dma = (u64)mem->dma;
@@ -868,7 +902,8 @@ int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
868 req = embedded_payload(wrb); 902 req = embedded_payload(wrb);
869 903
870 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 904 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
871 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL); 905 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
906 NULL);
872 907
873 /* Support for EQ_CREATEv2 available only SH-R onwards */ 908 /* Support for EQ_CREATEv2 available only SH-R onwards */
874 if (!(BEx_chip(adapter) || lancer_chip(adapter))) 909 if (!(BEx_chip(adapter) || lancer_chip(adapter)))
@@ -917,7 +952,8 @@ int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
917 req = embedded_payload(wrb); 952 req = embedded_payload(wrb);
918 953
919 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 954 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
920 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL); 955 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
956 NULL);
921 req->type = MAC_ADDRESS_TYPE_NETWORK; 957 req->type = MAC_ADDRESS_TYPE_NETWORK;
922 if (permanent) { 958 if (permanent) {
923 req->permanent = 1; 959 req->permanent = 1;
@@ -940,7 +976,7 @@ err:
940 976
941/* Uses synchronous MCCQ */ 977/* Uses synchronous MCCQ */
942int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, 978int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
943 u32 if_id, u32 *pmac_id, u32 domain) 979 u32 if_id, u32 *pmac_id, u32 domain)
944{ 980{
945 struct be_mcc_wrb *wrb; 981 struct be_mcc_wrb *wrb;
946 struct be_cmd_req_pmac_add *req; 982 struct be_cmd_req_pmac_add *req;
@@ -956,7 +992,8 @@ int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
956 req = embedded_payload(wrb); 992 req = embedded_payload(wrb);
957 993
958 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 994 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
959 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL); 995 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
996 NULL);
960 997
961 req->hdr.domain = domain; 998 req->hdr.domain = domain;
962 req->if_id = cpu_to_le32(if_id); 999 req->if_id = cpu_to_le32(if_id);
@@ -1012,7 +1049,7 @@ err:
1012 1049
1013/* Uses Mbox */ 1050/* Uses Mbox */
1014int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 1051int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1015 struct be_queue_info *eq, bool no_delay, int coalesce_wm) 1052 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1016{ 1053{
1017 struct be_mcc_wrb *wrb; 1054 struct be_mcc_wrb *wrb;
1018 struct be_cmd_req_cq_create *req; 1055 struct be_cmd_req_cq_create *req;
@@ -1028,17 +1065,18 @@ int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1028 ctxt = &req->context; 1065 ctxt = &req->context;
1029 1066
1030 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1067 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1031 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL); 1068 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1069 NULL);
1032 1070
1033 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1071 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1034 1072
1035 if (BEx_chip(adapter)) { 1073 if (BEx_chip(adapter)) {
1036 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, 1074 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1037 coalesce_wm); 1075 coalesce_wm);
1038 AMAP_SET_BITS(struct amap_cq_context_be, nodelay, 1076 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1039 ctxt, no_delay); 1077 ctxt, no_delay);
1040 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, 1078 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1041 __ilog2_u32(cq->len/256)); 1079 __ilog2_u32(cq->len / 256));
1042 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); 1080 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1043 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1); 1081 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1044 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id); 1082 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
@@ -1053,14 +1091,12 @@ int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1053 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm, 1091 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1054 ctxt, coalesce_wm); 1092 ctxt, coalesce_wm);
1055 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt, 1093 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1056 no_delay); 1094 no_delay);
1057 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, 1095 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1058 __ilog2_u32(cq->len/256)); 1096 __ilog2_u32(cq->len / 256));
1059 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); 1097 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1060 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, 1098 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1061 ctxt, 1); 1099 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1062 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
1063 ctxt, eq->id);
1064 } 1100 }
1065 1101
1066 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1102 be_dws_cpu_to_le(ctxt, sizeof(req->context));
@@ -1088,8 +1124,8 @@ static u32 be_encoded_q_len(int q_len)
1088} 1124}
1089 1125
1090static int be_cmd_mccq_ext_create(struct be_adapter *adapter, 1126static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1091 struct be_queue_info *mccq, 1127 struct be_queue_info *mccq,
1092 struct be_queue_info *cq) 1128 struct be_queue_info *cq)
1093{ 1129{
1094 struct be_mcc_wrb *wrb; 1130 struct be_mcc_wrb *wrb;
1095 struct be_cmd_req_mcc_ext_create *req; 1131 struct be_cmd_req_mcc_ext_create *req;
@@ -1105,13 +1141,14 @@ static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1105 ctxt = &req->context; 1141 ctxt = &req->context;
1106 1142
1107 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1143 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1108 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL); 1144 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1145 NULL);
1109 1146
1110 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1147 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1111 if (BEx_chip(adapter)) { 1148 if (BEx_chip(adapter)) {
1112 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1149 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1113 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1150 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1114 be_encoded_q_len(mccq->len)); 1151 be_encoded_q_len(mccq->len));
1115 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1152 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1116 } else { 1153 } else {
1117 req->hdr.version = 1; 1154 req->hdr.version = 1;
@@ -1145,8 +1182,8 @@ static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1145} 1182}
1146 1183
1147static int be_cmd_mccq_org_create(struct be_adapter *adapter, 1184static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1148 struct be_queue_info *mccq, 1185 struct be_queue_info *mccq,
1149 struct be_queue_info *cq) 1186 struct be_queue_info *cq)
1150{ 1187{
1151 struct be_mcc_wrb *wrb; 1188 struct be_mcc_wrb *wrb;
1152 struct be_cmd_req_mcc_create *req; 1189 struct be_cmd_req_mcc_create *req;
@@ -1162,13 +1199,14 @@ static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1162 ctxt = &req->context; 1199 ctxt = &req->context;
1163 1200
1164 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1201 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1165 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL); 1202 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1203 NULL);
1166 1204
1167 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 1205 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1168 1206
1169 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1); 1207 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1170 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt, 1208 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1171 be_encoded_q_len(mccq->len)); 1209 be_encoded_q_len(mccq->len));
1172 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id); 1210 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1173 1211
1174 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1212 be_dws_cpu_to_le(ctxt, sizeof(req->context));
@@ -1187,8 +1225,7 @@ static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1187} 1225}
1188 1226
1189int be_cmd_mccq_create(struct be_adapter *adapter, 1227int be_cmd_mccq_create(struct be_adapter *adapter,
1190 struct be_queue_info *mccq, 1228 struct be_queue_info *mccq, struct be_queue_info *cq)
1191 struct be_queue_info *cq)
1192{ 1229{
1193 int status; 1230 int status;
1194 1231
@@ -1213,7 +1250,7 @@ int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1213 1250
1214 req = embedded_payload(&wrb); 1251 req = embedded_payload(&wrb);
1215 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1252 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1216 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL); 1253 OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1217 1254
1218 if (lancer_chip(adapter)) { 1255 if (lancer_chip(adapter)) {
1219 req->hdr.version = 1; 1256 req->hdr.version = 1;
@@ -1250,8 +1287,8 @@ int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1250 1287
1251/* Uses MCC */ 1288/* Uses MCC */
1252int be_cmd_rxq_create(struct be_adapter *adapter, 1289int be_cmd_rxq_create(struct be_adapter *adapter,
1253 struct be_queue_info *rxq, u16 cq_id, u16 frag_size, 1290 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1254 u32 if_id, u32 rss, u8 *rss_id) 1291 u32 if_id, u32 rss, u8 *rss_id)
1255{ 1292{
1256 struct be_mcc_wrb *wrb; 1293 struct be_mcc_wrb *wrb;
1257 struct be_cmd_req_eth_rx_create *req; 1294 struct be_cmd_req_eth_rx_create *req;
@@ -1268,7 +1305,7 @@ int be_cmd_rxq_create(struct be_adapter *adapter,
1268 req = embedded_payload(wrb); 1305 req = embedded_payload(wrb);
1269 1306
1270 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1307 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1271 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL); 1308 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1272 1309
1273 req->cq_id = cpu_to_le16(cq_id); 1310 req->cq_id = cpu_to_le16(cq_id);
1274 req->frag_size = fls(frag_size) - 1; 1311 req->frag_size = fls(frag_size) - 1;
@@ -1295,7 +1332,7 @@ err:
1295 * Uses Mbox 1332 * Uses Mbox
1296 */ 1333 */
1297int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 1334int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1298 int queue_type) 1335 int queue_type)
1299{ 1336{
1300 struct be_mcc_wrb *wrb; 1337 struct be_mcc_wrb *wrb;
1301 struct be_cmd_req_q_destroy *req; 1338 struct be_cmd_req_q_destroy *req;
@@ -1334,7 +1371,7 @@ int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1334 } 1371 }
1335 1372
1336 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb, 1373 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1337 NULL); 1374 NULL);
1338 req->id = cpu_to_le16(q->id); 1375 req->id = cpu_to_le16(q->id);
1339 1376
1340 status = be_mbox_notify_wait(adapter); 1377 status = be_mbox_notify_wait(adapter);
@@ -1361,7 +1398,7 @@ int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1361 req = embedded_payload(wrb); 1398 req = embedded_payload(wrb);
1362 1399
1363 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1400 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1364 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL); 1401 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1365 req->id = cpu_to_le16(q->id); 1402 req->id = cpu_to_le16(q->id);
1366 1403
1367 status = be_mcc_notify_wait(adapter); 1404 status = be_mcc_notify_wait(adapter);
@@ -1384,7 +1421,8 @@ int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1384 1421
1385 req = embedded_payload(&wrb); 1422 req = embedded_payload(&wrb);
1386 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1423 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1387 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), &wrb, NULL); 1424 OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1425 sizeof(*req), &wrb, NULL);
1388 req->hdr.domain = domain; 1426 req->hdr.domain = domain;
1389 req->capability_flags = cpu_to_le32(cap_flags); 1427 req->capability_flags = cpu_to_le32(cap_flags);
1390 req->enable_flags = cpu_to_le32(en_flags); 1428 req->enable_flags = cpu_to_le32(en_flags);
@@ -1422,7 +1460,8 @@ int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1422 req = embedded_payload(wrb); 1460 req = embedded_payload(wrb);
1423 1461
1424 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1462 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1425 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL); 1463 OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1464 sizeof(*req), wrb, NULL);
1426 req->hdr.domain = domain; 1465 req->hdr.domain = domain;
1427 req->interface_id = cpu_to_le32(interface_id); 1466 req->interface_id = cpu_to_le32(interface_id);
1428 1467
@@ -1452,7 +1491,8 @@ int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1452 hdr = nonemb_cmd->va; 1491 hdr = nonemb_cmd->va;
1453 1492
1454 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, 1493 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1455 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd); 1494 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1495 nonemb_cmd);
1456 1496
1457 /* version 1 of the cmd is not supported only by BE2 */ 1497 /* version 1 of the cmd is not supported only by BE2 */
1458 if (BE2_chip(adapter)) 1498 if (BE2_chip(adapter))
@@ -1472,7 +1512,7 @@ err:
1472 1512
1473/* Lancer Stats */ 1513/* Lancer Stats */
1474int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 1514int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1475 struct be_dma_mem *nonemb_cmd) 1515 struct be_dma_mem *nonemb_cmd)
1476{ 1516{
1477 1517
1478 struct be_mcc_wrb *wrb; 1518 struct be_mcc_wrb *wrb;
@@ -1493,8 +1533,8 @@ int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1493 req = nonemb_cmd->va; 1533 req = nonemb_cmd->va;
1494 1534
1495 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 1535 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1496 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb, 1536 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1497 nonemb_cmd); 1537 wrb, nonemb_cmd);
1498 1538
1499 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num); 1539 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1500 req->cmd_params.params.reset_stats = 0; 1540 req->cmd_params.params.reset_stats = 0;
@@ -1553,7 +1593,8 @@ int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1553 req = embedded_payload(wrb); 1593 req = embedded_payload(wrb);
1554 1594
1555 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1595 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1556 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL); 1596 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1597 sizeof(*req), wrb, NULL);
1557 1598
1558 /* version 1 of the cmd is not supported only by BE2 */ 1599 /* version 1 of the cmd is not supported only by BE2 */
1559 if (!BE2_chip(adapter)) 1600 if (!BE2_chip(adapter))
@@ -1598,8 +1639,8 @@ int be_cmd_get_die_temperature(struct be_adapter *adapter)
1598 req = embedded_payload(wrb); 1639 req = embedded_payload(wrb);
1599 1640
1600 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1641 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1601 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req), 1642 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1602 wrb, NULL); 1643 sizeof(*req), wrb, NULL);
1603 1644
1604 be_mcc_notify(adapter); 1645 be_mcc_notify(adapter);
1605 1646
@@ -1625,7 +1666,8 @@ int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1625 req = embedded_payload(wrb); 1666 req = embedded_payload(wrb);
1626 1667
1627 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1668 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1628 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL); 1669 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1670 NULL);
1629 req->fat_operation = cpu_to_le32(QUERY_FAT); 1671 req->fat_operation = cpu_to_le32(QUERY_FAT);
1630 status = be_mcc_notify_wait(adapter); 1672 status = be_mcc_notify_wait(adapter);
1631 if (!status) { 1673 if (!status) {
@@ -1655,8 +1697,8 @@ void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1655 1697
1656 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024; 1698 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1657 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev, 1699 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1658 get_fat_cmd.size, 1700 get_fat_cmd.size,
1659 &get_fat_cmd.dma); 1701 &get_fat_cmd.dma);
1660 if (!get_fat_cmd.va) { 1702 if (!get_fat_cmd.va) {
1661 status = -ENOMEM; 1703 status = -ENOMEM;
1662 dev_err(&adapter->pdev->dev, 1704 dev_err(&adapter->pdev->dev,
@@ -1679,8 +1721,8 @@ void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1679 1721
1680 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; 1722 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1681 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1723 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1682 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb, 1724 OPCODE_COMMON_MANAGE_FAT, payload_len,
1683 &get_fat_cmd); 1725 wrb, &get_fat_cmd);
1684 1726
1685 req->fat_operation = cpu_to_le32(RETRIEVE_FAT); 1727 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1686 req->read_log_offset = cpu_to_le32(log_offset); 1728 req->read_log_offset = cpu_to_le32(log_offset);
@@ -1691,8 +1733,8 @@ void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1691 if (!status) { 1733 if (!status) {
1692 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va; 1734 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1693 memcpy(buf + offset, 1735 memcpy(buf + offset,
1694 resp->data_buffer, 1736 resp->data_buffer,
1695 le32_to_cpu(resp->read_log_length)); 1737 le32_to_cpu(resp->read_log_length));
1696 } else { 1738 } else {
1697 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n"); 1739 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1698 goto err; 1740 goto err;
@@ -1702,14 +1744,13 @@ void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1702 } 1744 }
1703err: 1745err:
1704 pci_free_consistent(adapter->pdev, get_fat_cmd.size, 1746 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1705 get_fat_cmd.va, 1747 get_fat_cmd.va, get_fat_cmd.dma);
1706 get_fat_cmd.dma);
1707 spin_unlock_bh(&adapter->mcc_lock); 1748 spin_unlock_bh(&adapter->mcc_lock);
1708} 1749}
1709 1750
1710/* Uses synchronous mcc */ 1751/* Uses synchronous mcc */
1711int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver, 1752int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1712 char *fw_on_flash) 1753 char *fw_on_flash)
1713{ 1754{
1714 struct be_mcc_wrb *wrb; 1755 struct be_mcc_wrb *wrb;
1715 struct be_cmd_req_get_fw_version *req; 1756 struct be_cmd_req_get_fw_version *req;
@@ -1726,7 +1767,8 @@ int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1726 req = embedded_payload(wrb); 1767 req = embedded_payload(wrb);
1727 1768
1728 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1769 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1729 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL); 1770 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1771 NULL);
1730 status = be_mcc_notify_wait(adapter); 1772 status = be_mcc_notify_wait(adapter);
1731 if (!status) { 1773 if (!status) {
1732 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); 1774 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
@@ -1759,7 +1801,8 @@ int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1759 req = embedded_payload(wrb); 1801 req = embedded_payload(wrb);
1760 1802
1761 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1803 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1762 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL); 1804 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1805 NULL);
1763 1806
1764 req->num_eq = cpu_to_le32(num); 1807 req->num_eq = cpu_to_le32(num);
1765 for (i = 0; i < num; i++) { 1808 for (i = 0; i < num; i++) {
@@ -1777,7 +1820,7 @@ err:
1777 1820
1778/* Uses sycnhronous mcc */ 1821/* Uses sycnhronous mcc */
1779int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 1822int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1780 u32 num, bool promiscuous) 1823 u32 num)
1781{ 1824{
1782 struct be_mcc_wrb *wrb; 1825 struct be_mcc_wrb *wrb;
1783 struct be_cmd_req_vlan_config *req; 1826 struct be_cmd_req_vlan_config *req;
@@ -1793,19 +1836,16 @@ int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1793 req = embedded_payload(wrb); 1836 req = embedded_payload(wrb);
1794 1837
1795 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1838 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1796 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL); 1839 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1840 wrb, NULL);
1797 1841
1798 req->interface_id = if_id; 1842 req->interface_id = if_id;
1799 req->promiscuous = promiscuous;
1800 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0; 1843 req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1801 req->num_vlan = num; 1844 req->num_vlan = num;
1802 if (!promiscuous) { 1845 memcpy(req->normal_vlan, vtag_array,
1803 memcpy(req->normal_vlan, vtag_array, 1846 req->num_vlan * sizeof(vtag_array[0]));
1804 req->num_vlan * sizeof(vtag_array[0]));
1805 }
1806 1847
1807 status = be_mcc_notify_wait(adapter); 1848 status = be_mcc_notify_wait(adapter);
1808
1809err: 1849err:
1810 spin_unlock_bh(&adapter->mcc_lock); 1850 spin_unlock_bh(&adapter->mcc_lock);
1811 return status; 1851 return status;
@@ -1827,18 +1867,19 @@ int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1827 } 1867 }
1828 memset(req, 0, sizeof(*req)); 1868 memset(req, 0, sizeof(*req));
1829 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1869 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1830 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req), 1870 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1831 wrb, mem); 1871 wrb, mem);
1832 1872
1833 req->if_id = cpu_to_le32(adapter->if_handle); 1873 req->if_id = cpu_to_le32(adapter->if_handle);
1834 if (flags & IFF_PROMISC) { 1874 if (flags & IFF_PROMISC) {
1835 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1875 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1836 BE_IF_FLAGS_VLAN_PROMISCUOUS | 1876 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1837 BE_IF_FLAGS_MCAST_PROMISCUOUS); 1877 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1838 if (value == ON) 1878 if (value == ON)
1839 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS | 1879 req->if_flags =
1840 BE_IF_FLAGS_VLAN_PROMISCUOUS | 1880 cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1841 BE_IF_FLAGS_MCAST_PROMISCUOUS); 1881 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1882 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1842 } else if (flags & IFF_ALLMULTI) { 1883 } else if (flags & IFF_ALLMULTI) {
1843 req->if_flags_mask = req->if_flags = 1884 req->if_flags_mask = req->if_flags =
1844 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS); 1885 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
@@ -1867,7 +1908,7 @@ int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1867 } 1908 }
1868 1909
1869 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) != 1910 if ((req->if_flags_mask & cpu_to_le32(be_if_cap_flags(adapter))) !=
1870 req->if_flags_mask) { 1911 req->if_flags_mask) {
1871 dev_warn(&adapter->pdev->dev, 1912 dev_warn(&adapter->pdev->dev,
1872 "Cannot set rx filter flags 0x%x\n", 1913 "Cannot set rx filter flags 0x%x\n",
1873 req->if_flags_mask); 1914 req->if_flags_mask);
@@ -1905,7 +1946,8 @@ int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1905 req = embedded_payload(wrb); 1946 req = embedded_payload(wrb);
1906 1947
1907 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1948 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1908 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL); 1949 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
1950 wrb, NULL);
1909 1951
1910 req->tx_flow_control = cpu_to_le16((u16)tx_fc); 1952 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1911 req->rx_flow_control = cpu_to_le16((u16)rx_fc); 1953 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
@@ -1938,7 +1980,8 @@ int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1938 req = embedded_payload(wrb); 1980 req = embedded_payload(wrb);
1939 1981
1940 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1982 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1941 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL); 1983 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
1984 wrb, NULL);
1942 1985
1943 status = be_mcc_notify_wait(adapter); 1986 status = be_mcc_notify_wait(adapter);
1944 if (!status) { 1987 if (!status) {
@@ -1968,7 +2011,8 @@ int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1968 req = embedded_payload(wrb); 2011 req = embedded_payload(wrb);
1969 2012
1970 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2013 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1971 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL); 2014 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2015 sizeof(*req), wrb, NULL);
1972 2016
1973 status = be_mbox_notify_wait(adapter); 2017 status = be_mbox_notify_wait(adapter);
1974 if (!status) { 2018 if (!status) {
@@ -2011,7 +2055,8 @@ int be_cmd_reset_function(struct be_adapter *adapter)
2011 req = embedded_payload(wrb); 2055 req = embedded_payload(wrb);
2012 2056
2013 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, 2057 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2014 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL); 2058 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2059 NULL);
2015 2060
2016 status = be_mbox_notify_wait(adapter); 2061 status = be_mbox_notify_wait(adapter);
2017 2062
@@ -2020,47 +2065,47 @@ int be_cmd_reset_function(struct be_adapter *adapter)
2020} 2065}
2021 2066
2022int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2067int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2023 u32 rss_hash_opts, u16 table_size) 2068 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2024{ 2069{
2025 struct be_mcc_wrb *wrb; 2070 struct be_mcc_wrb *wrb;
2026 struct be_cmd_req_rss_config *req; 2071 struct be_cmd_req_rss_config *req;
2027 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
2028 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
2029 0x3ea83c02, 0x4a110304};
2030 int status; 2072 int status;
2031 2073
2032 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS)) 2074 if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2033 return 0; 2075 return 0;
2034 2076
2035 if (mutex_lock_interruptible(&adapter->mbox_lock)) 2077 spin_lock_bh(&adapter->mcc_lock);
2036 return -1;
2037 2078
2038 wrb = wrb_from_mbox(adapter); 2079 wrb = wrb_from_mccq(adapter);
2080 if (!wrb) {
2081 status = -EBUSY;
2082 goto err;
2083 }
2039 req = embedded_payload(wrb); 2084 req = embedded_payload(wrb);
2040 2085
2041 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2086 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2042 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); 2087 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2043 2088
2044 req->if_id = cpu_to_le32(adapter->if_handle); 2089 req->if_id = cpu_to_le32(adapter->if_handle);
2045 req->enable_rss = cpu_to_le16(rss_hash_opts); 2090 req->enable_rss = cpu_to_le16(rss_hash_opts);
2046 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); 2091 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2047 2092
2048 if (lancer_chip(adapter) || skyhawk_chip(adapter)) 2093 if (!BEx_chip(adapter))
2049 req->hdr.version = 1; 2094 req->hdr.version = 1;
2050 2095
2051 memcpy(req->cpu_table, rsstable, table_size); 2096 memcpy(req->cpu_table, rsstable, table_size);
2052 memcpy(req->hash, myhash, sizeof(myhash)); 2097 memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2053 be_dws_cpu_to_le(req->hash, sizeof(req->hash)); 2098 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2054 2099
2055 status = be_mbox_notify_wait(adapter); 2100 status = be_mcc_notify_wait(adapter);
2056 2101err:
2057 mutex_unlock(&adapter->mbox_lock); 2102 spin_unlock_bh(&adapter->mcc_lock);
2058 return status; 2103 return status;
2059} 2104}
2060 2105
2061/* Uses sync mcc */ 2106/* Uses sync mcc */
2062int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, 2107int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2063 u8 bcn, u8 sts, u8 state) 2108 u8 bcn, u8 sts, u8 state)
2064{ 2109{
2065 struct be_mcc_wrb *wrb; 2110 struct be_mcc_wrb *wrb;
2066 struct be_cmd_req_enable_disable_beacon *req; 2111 struct be_cmd_req_enable_disable_beacon *req;
@@ -2076,7 +2121,8 @@ int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2076 req = embedded_payload(wrb); 2121 req = embedded_payload(wrb);
2077 2122
2078 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2123 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2079 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL); 2124 OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2125 sizeof(*req), wrb, NULL);
2080 2126
2081 req->port_num = port_num; 2127 req->port_num = port_num;
2082 req->beacon_state = state; 2128 req->beacon_state = state;
@@ -2107,7 +2153,8 @@ int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2107 req = embedded_payload(wrb); 2153 req = embedded_payload(wrb);
2108 2154
2109 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2155 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2110 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL); 2156 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2157 wrb, NULL);
2111 2158
2112 req->port_num = port_num; 2159 req->port_num = port_num;
2113 2160
@@ -2146,20 +2193,20 @@ int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2146 req = embedded_payload(wrb); 2193 req = embedded_payload(wrb);
2147 2194
2148 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2195 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2149 OPCODE_COMMON_WRITE_OBJECT, 2196 OPCODE_COMMON_WRITE_OBJECT,
2150 sizeof(struct lancer_cmd_req_write_object), wrb, 2197 sizeof(struct lancer_cmd_req_write_object), wrb,
2151 NULL); 2198 NULL);
2152 2199
2153 ctxt = &req->context; 2200 ctxt = &req->context;
2154 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2201 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2155 write_length, ctxt, data_size); 2202 write_length, ctxt, data_size);
2156 2203
2157 if (data_size == 0) 2204 if (data_size == 0)
2158 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2205 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2159 eof, ctxt, 1); 2206 eof, ctxt, 1);
2160 else 2207 else
2161 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 2208 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2162 eof, ctxt, 0); 2209 eof, ctxt, 0);
2163 2210
2164 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 2211 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2165 req->write_offset = cpu_to_le32(data_offset); 2212 req->write_offset = cpu_to_le32(data_offset);
@@ -2167,8 +2214,8 @@ int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2167 req->descriptor_count = cpu_to_le32(1); 2214 req->descriptor_count = cpu_to_le32(1);
2168 req->buf_len = cpu_to_le32(data_size); 2215 req->buf_len = cpu_to_le32(data_size);
2169 req->addr_low = cpu_to_le32((cmd->dma + 2216 req->addr_low = cpu_to_le32((cmd->dma +
2170 sizeof(struct lancer_cmd_req_write_object)) 2217 sizeof(struct lancer_cmd_req_write_object))
2171 & 0xFFFFFFFF); 2218 & 0xFFFFFFFF);
2172 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma + 2219 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2173 sizeof(struct lancer_cmd_req_write_object))); 2220 sizeof(struct lancer_cmd_req_write_object)));
2174 2221
@@ -2197,8 +2244,8 @@ err_unlock:
2197} 2244}
2198 2245
2199int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2246int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2200 u32 data_size, u32 data_offset, const char *obj_name, 2247 u32 data_size, u32 data_offset, const char *obj_name,
2201 u32 *data_read, u32 *eof, u8 *addn_status) 2248 u32 *data_read, u32 *eof, u8 *addn_status)
2202{ 2249{
2203 struct be_mcc_wrb *wrb; 2250 struct be_mcc_wrb *wrb;
2204 struct lancer_cmd_req_read_object *req; 2251 struct lancer_cmd_req_read_object *req;
@@ -2216,9 +2263,9 @@ int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2216 req = embedded_payload(wrb); 2263 req = embedded_payload(wrb);
2217 2264
2218 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2265 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2219 OPCODE_COMMON_READ_OBJECT, 2266 OPCODE_COMMON_READ_OBJECT,
2220 sizeof(struct lancer_cmd_req_read_object), wrb, 2267 sizeof(struct lancer_cmd_req_read_object), wrb,
2221 NULL); 2268 NULL);
2222 2269
2223 req->desired_read_len = cpu_to_le32(data_size); 2270 req->desired_read_len = cpu_to_le32(data_size);
2224 req->read_offset = cpu_to_le32(data_offset); 2271 req->read_offset = cpu_to_le32(data_offset);
@@ -2244,7 +2291,7 @@ err_unlock:
2244} 2291}
2245 2292
2246int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 2293int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2247 u32 flash_type, u32 flash_opcode, u32 buf_size) 2294 u32 flash_type, u32 flash_opcode, u32 buf_size)
2248{ 2295{
2249 struct be_mcc_wrb *wrb; 2296 struct be_mcc_wrb *wrb;
2250 struct be_cmd_write_flashrom *req; 2297 struct be_cmd_write_flashrom *req;
@@ -2261,7 +2308,8 @@ int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2261 req = cmd->va; 2308 req = cmd->va;
2262 2309
2263 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2310 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2264 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd); 2311 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2312 cmd);
2265 2313
2266 req->params.op_type = cpu_to_le32(flash_type); 2314 req->params.op_type = cpu_to_le32(flash_type);
2267 req->params.op_code = cpu_to_le32(flash_opcode); 2315 req->params.op_code = cpu_to_le32(flash_opcode);
@@ -2284,7 +2332,7 @@ err_unlock:
2284} 2332}
2285 2333
2286int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 2334int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2287 int offset) 2335 u16 optype, int offset)
2288{ 2336{
2289 struct be_mcc_wrb *wrb; 2337 struct be_mcc_wrb *wrb;
2290 struct be_cmd_read_flash_crc *req; 2338 struct be_cmd_read_flash_crc *req;
@@ -2303,7 +2351,7 @@ int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2303 OPCODE_COMMON_READ_FLASHROM, sizeof(*req), 2351 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2304 wrb, NULL); 2352 wrb, NULL);
2305 2353
2306 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT); 2354 req->params.op_type = cpu_to_le32(optype);
2307 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); 2355 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2308 req->params.offset = cpu_to_le32(offset); 2356 req->params.offset = cpu_to_le32(offset);
2309 req->params.data_buf_size = cpu_to_le32(0x4); 2357 req->params.data_buf_size = cpu_to_le32(0x4);
@@ -2318,7 +2366,7 @@ err:
2318} 2366}
2319 2367
2320int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2368int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2321 struct be_dma_mem *nonemb_cmd) 2369 struct be_dma_mem *nonemb_cmd)
2322{ 2370{
2323 struct be_mcc_wrb *wrb; 2371 struct be_mcc_wrb *wrb;
2324 struct be_cmd_req_acpi_wol_magic_config *req; 2372 struct be_cmd_req_acpi_wol_magic_config *req;
@@ -2334,8 +2382,8 @@ int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2334 req = nonemb_cmd->va; 2382 req = nonemb_cmd->va;
2335 2383
2336 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, 2384 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2337 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb, 2385 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2338 nonemb_cmd); 2386 wrb, nonemb_cmd);
2339 memcpy(req->magic_mac, mac, ETH_ALEN); 2387 memcpy(req->magic_mac, mac, ETH_ALEN);
2340 2388
2341 status = be_mcc_notify_wait(adapter); 2389 status = be_mcc_notify_wait(adapter);
@@ -2363,8 +2411,8 @@ int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2363 req = embedded_payload(wrb); 2411 req = embedded_payload(wrb);
2364 2412
2365 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2413 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2366 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb, 2414 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2367 NULL); 2415 wrb, NULL);
2368 2416
2369 req->src_port = port_num; 2417 req->src_port = port_num;
2370 req->dest_port = port_num; 2418 req->dest_port = port_num;
@@ -2378,7 +2426,8 @@ err:
2378} 2426}
2379 2427
2380int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2428int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2381 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) 2429 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2430 u64 pattern)
2382{ 2431{
2383 struct be_mcc_wrb *wrb; 2432 struct be_mcc_wrb *wrb;
2384 struct be_cmd_req_loopback_test *req; 2433 struct be_cmd_req_loopback_test *req;
@@ -2396,7 +2445,8 @@ int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2396 req = embedded_payload(wrb); 2445 req = embedded_payload(wrb);
2397 2446
2398 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2447 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2399 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL); 2448 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2449 NULL);
2400 2450
2401 req->hdr.timeout = cpu_to_le32(15); 2451 req->hdr.timeout = cpu_to_le32(15);
2402 req->pattern = cpu_to_le64(pattern); 2452 req->pattern = cpu_to_le64(pattern);
@@ -2421,7 +2471,7 @@ err:
2421} 2471}
2422 2472
2423int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, 2473int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2424 u32 byte_cnt, struct be_dma_mem *cmd) 2474 u32 byte_cnt, struct be_dma_mem *cmd)
2425{ 2475{
2426 struct be_mcc_wrb *wrb; 2476 struct be_mcc_wrb *wrb;
2427 struct be_cmd_req_ddrdma_test *req; 2477 struct be_cmd_req_ddrdma_test *req;
@@ -2437,7 +2487,8 @@ int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2437 } 2487 }
2438 req = cmd->va; 2488 req = cmd->va;
2439 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, 2489 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2440 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd); 2490 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2491 cmd);
2441 2492
2442 req->pattern = cpu_to_le64(pattern); 2493 req->pattern = cpu_to_le64(pattern);
2443 req->byte_count = cpu_to_le32(byte_cnt); 2494 req->byte_count = cpu_to_le32(byte_cnt);
@@ -2465,7 +2516,7 @@ err:
2465} 2516}
2466 2517
2467int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2518int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2468 struct be_dma_mem *nonemb_cmd) 2519 struct be_dma_mem *nonemb_cmd)
2469{ 2520{
2470 struct be_mcc_wrb *wrb; 2521 struct be_mcc_wrb *wrb;
2471 struct be_cmd_req_seeprom_read *req; 2522 struct be_cmd_req_seeprom_read *req;
@@ -2481,8 +2532,8 @@ int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2481 req = nonemb_cmd->va; 2532 req = nonemb_cmd->va;
2482 2533
2483 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2534 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2484 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb, 2535 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2485 nonemb_cmd); 2536 nonemb_cmd);
2486 2537
2487 status = be_mcc_notify_wait(adapter); 2538 status = be_mcc_notify_wait(adapter);
2488 2539
@@ -2510,8 +2561,7 @@ int be_cmd_get_phy_info(struct be_adapter *adapter)
2510 goto err; 2561 goto err;
2511 } 2562 }
2512 cmd.size = sizeof(struct be_cmd_req_get_phy_info); 2563 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2513 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 2564 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2514 &cmd.dma);
2515 if (!cmd.va) { 2565 if (!cmd.va) {
2516 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 2566 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2517 status = -ENOMEM; 2567 status = -ENOMEM;
@@ -2521,8 +2571,8 @@ int be_cmd_get_phy_info(struct be_adapter *adapter)
2521 req = cmd.va; 2571 req = cmd.va;
2522 2572
2523 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2573 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2524 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req), 2574 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2525 wrb, &cmd); 2575 wrb, &cmd);
2526 2576
2527 status = be_mcc_notify_wait(adapter); 2577 status = be_mcc_notify_wait(adapter);
2528 if (!status) { 2578 if (!status) {
@@ -2544,8 +2594,7 @@ int be_cmd_get_phy_info(struct be_adapter *adapter)
2544 BE_SUPPORTED_SPEED_1GBPS; 2594 BE_SUPPORTED_SPEED_1GBPS;
2545 } 2595 }
2546 } 2596 }
2547 pci_free_consistent(adapter->pdev, cmd.size, 2597 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2548 cmd.va, cmd.dma);
2549err: 2598err:
2550 spin_unlock_bh(&adapter->mcc_lock); 2599 spin_unlock_bh(&adapter->mcc_lock);
2551 return status; 2600 return status;
@@ -2568,7 +2617,7 @@ int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2568 req = embedded_payload(wrb); 2617 req = embedded_payload(wrb);
2569 2618
2570 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2619 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2571 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL); 2620 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2572 2621
2573 req->hdr.domain = domain; 2622 req->hdr.domain = domain;
2574 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); 2623 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
@@ -2597,10 +2646,9 @@ int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2597 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem)); 2646 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2598 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs); 2647 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2599 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size, 2648 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2600 &attribs_cmd.dma); 2649 &attribs_cmd.dma);
2601 if (!attribs_cmd.va) { 2650 if (!attribs_cmd.va) {
2602 dev_err(&adapter->pdev->dev, 2651 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
2603 "Memory allocation failure\n");
2604 status = -ENOMEM; 2652 status = -ENOMEM;
2605 goto err; 2653 goto err;
2606 } 2654 }
@@ -2613,8 +2661,8 @@ int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2613 req = attribs_cmd.va; 2661 req = attribs_cmd.va;
2614 2662
2615 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2663 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2616 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb, 2664 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2617 &attribs_cmd); 2665 wrb, &attribs_cmd);
2618 2666
2619 status = be_mbox_notify_wait(adapter); 2667 status = be_mbox_notify_wait(adapter);
2620 if (!status) { 2668 if (!status) {
@@ -2649,7 +2697,8 @@ int be_cmd_req_native_mode(struct be_adapter *adapter)
2649 req = embedded_payload(wrb); 2697 req = embedded_payload(wrb);
2650 2698
2651 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2699 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2652 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL); 2700 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2701 sizeof(*req), wrb, NULL);
2653 2702
2654 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | 2703 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2655 CAPABILITY_BE3_NATIVE_ERX_API); 2704 CAPABILITY_BE3_NATIVE_ERX_API);
@@ -2762,12 +2811,12 @@ int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2762 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem)); 2811 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2763 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list); 2812 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2764 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev, 2813 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2765 get_mac_list_cmd.size, 2814 get_mac_list_cmd.size,
2766 &get_mac_list_cmd.dma); 2815 &get_mac_list_cmd.dma);
2767 2816
2768 if (!get_mac_list_cmd.va) { 2817 if (!get_mac_list_cmd.va) {
2769 dev_err(&adapter->pdev->dev, 2818 dev_err(&adapter->pdev->dev,
2770 "Memory allocation failure during GET_MAC_LIST\n"); 2819 "Memory allocation failure during GET_MAC_LIST\n");
2771 return -ENOMEM; 2820 return -ENOMEM;
2772 } 2821 }
2773 2822
@@ -2831,18 +2880,18 @@ int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2831 /* If no active mac_id found, return first mac addr */ 2880 /* If no active mac_id found, return first mac addr */
2832 *pmac_id_valid = false; 2881 *pmac_id_valid = false;
2833 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr, 2882 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2834 ETH_ALEN); 2883 ETH_ALEN);
2835 } 2884 }
2836 2885
2837out: 2886out:
2838 spin_unlock_bh(&adapter->mcc_lock); 2887 spin_unlock_bh(&adapter->mcc_lock);
2839 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size, 2888 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2840 get_mac_list_cmd.va, get_mac_list_cmd.dma); 2889 get_mac_list_cmd.va, get_mac_list_cmd.dma);
2841 return status; 2890 return status;
2842} 2891}
2843 2892
2844int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac, 2893int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
2845 u32 if_handle, bool active, u32 domain) 2894 u8 *mac, u32 if_handle, bool active, u32 domain)
2846{ 2895{
2847 2896
2848 if (!active) 2897 if (!active)
@@ -2892,7 +2941,7 @@ int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2892 memset(&cmd, 0, sizeof(struct be_dma_mem)); 2941 memset(&cmd, 0, sizeof(struct be_dma_mem));
2893 cmd.size = sizeof(struct be_cmd_req_set_mac_list); 2942 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2894 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, 2943 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2895 &cmd.dma, GFP_KERNEL); 2944 &cmd.dma, GFP_KERNEL);
2896 if (!cmd.va) 2945 if (!cmd.va)
2897 return -ENOMEM; 2946 return -ENOMEM;
2898 2947
@@ -2906,8 +2955,8 @@ int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2906 2955
2907 req = cmd.va; 2956 req = cmd.va;
2908 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2957 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2909 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req), 2958 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2910 wrb, &cmd); 2959 wrb, &cmd);
2911 2960
2912 req->hdr.domain = domain; 2961 req->hdr.domain = domain;
2913 req->mac_count = mac_count; 2962 req->mac_count = mac_count;
@@ -2917,8 +2966,7 @@ int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2917 status = be_mcc_notify_wait(adapter); 2966 status = be_mcc_notify_wait(adapter);
2918 2967
2919err: 2968err:
2920 dma_free_coherent(&adapter->pdev->dev, cmd.size, 2969 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2921 cmd.va, cmd.dma);
2922 spin_unlock_bh(&adapter->mcc_lock); 2970 spin_unlock_bh(&adapter->mcc_lock);
2923 return status; 2971 return status;
2924} 2972}
@@ -2963,7 +3011,8 @@ int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2963 ctxt = &req->context; 3011 ctxt = &req->context;
2964 3012
2965 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3013 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2966 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL); 3014 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3015 NULL);
2967 3016
2968 req->hdr.domain = domain; 3017 req->hdr.domain = domain;
2969 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id); 3018 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
@@ -3009,7 +3058,8 @@ int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3009 ctxt = &req->context; 3058 ctxt = &req->context;
3010 3059
3011 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 3060 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3012 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL); 3061 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3062 NULL);
3013 3063
3014 req->hdr.domain = domain; 3064 req->hdr.domain = domain;
3015 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, 3065 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
@@ -3027,10 +3077,9 @@ int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3027 if (!status) { 3077 if (!status) {
3028 struct be_cmd_resp_get_hsw_config *resp = 3078 struct be_cmd_resp_get_hsw_config *resp =
3029 embedded_payload(wrb); 3079 embedded_payload(wrb);
3030 be_dws_le_to_cpu(&resp->context, 3080 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3031 sizeof(resp->context));
3032 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context, 3081 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3033 pvid, &resp->context); 3082 pvid, &resp->context);
3034 if (pvid) 3083 if (pvid)
3035 *pvid = le16_to_cpu(vid); 3084 *pvid = le16_to_cpu(vid);
3036 if (mode) 3085 if (mode)
@@ -3062,11 +3111,9 @@ int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3062 3111
3063 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3112 memset(&cmd, 0, sizeof(struct be_dma_mem));
3064 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1); 3113 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3065 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 3114 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3066 &cmd.dma);
3067 if (!cmd.va) { 3115 if (!cmd.va) {
3068 dev_err(&adapter->pdev->dev, 3116 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3069 "Memory allocation failure\n");
3070 status = -ENOMEM; 3117 status = -ENOMEM;
3071 goto err; 3118 goto err;
3072 } 3119 }
@@ -3349,8 +3396,7 @@ int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3349 3396
3350 memset(&cmd, 0, sizeof(struct be_dma_mem)); 3397 memset(&cmd, 0, sizeof(struct be_dma_mem));
3351 cmd.size = sizeof(struct be_cmd_resp_get_func_config); 3398 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3352 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, 3399 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3353 &cmd.dma);
3354 if (!cmd.va) { 3400 if (!cmd.va) {
3355 dev_err(&adapter->pdev->dev, "Memory alloc failure\n"); 3401 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3356 status = -ENOMEM; 3402 status = -ENOMEM;
@@ -3396,7 +3442,7 @@ err:
3396 3442
3397/* Uses mbox */ 3443/* Uses mbox */
3398static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter, 3444static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3399 u8 domain, struct be_dma_mem *cmd) 3445 u8 domain, struct be_dma_mem *cmd)
3400{ 3446{
3401 struct be_mcc_wrb *wrb; 3447 struct be_mcc_wrb *wrb;
3402 struct be_cmd_req_get_profile_config *req; 3448 struct be_cmd_req_get_profile_config *req;
@@ -3424,7 +3470,7 @@ static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3424 3470
3425/* Uses sync mcc */ 3471/* Uses sync mcc */
3426static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter, 3472static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3427 u8 domain, struct be_dma_mem *cmd) 3473 u8 domain, struct be_dma_mem *cmd)
3428{ 3474{
3429 struct be_mcc_wrb *wrb; 3475 struct be_mcc_wrb *wrb;
3430 struct be_cmd_req_get_profile_config *req; 3476 struct be_cmd_req_get_profile_config *req;
@@ -3484,8 +3530,8 @@ int be_cmd_get_profile_config(struct be_adapter *adapter,
3484 resp = cmd.va; 3530 resp = cmd.va;
3485 desc_count = le32_to_cpu(resp->desc_count); 3531 desc_count = le32_to_cpu(resp->desc_count);
3486 3532
3487 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param, 3533 pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3488 desc_count); 3534 desc_count);
3489 if (pcie) 3535 if (pcie)
3490 res->max_vfs = le16_to_cpu(pcie->num_vfs); 3536 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3491 3537
@@ -3548,33 +3594,47 @@ void be_reset_nic_desc(struct be_nic_res_desc *nic)
3548 nic->cq_count = 0xFFFF; 3594 nic->cq_count = 0xFFFF;
3549 nic->toe_conn_count = 0xFFFF; 3595 nic->toe_conn_count = 0xFFFF;
3550 nic->eq_count = 0xFFFF; 3596 nic->eq_count = 0xFFFF;
3597 nic->iface_count = 0xFFFF;
3551 nic->link_param = 0xFF; 3598 nic->link_param = 0xFF;
3599 nic->channel_id_param = cpu_to_le16(0xF000);
3552 nic->acpi_params = 0xFF; 3600 nic->acpi_params = 0xFF;
3553 nic->wol_param = 0x0F; 3601 nic->wol_param = 0x0F;
3554 nic->bw_min = 0xFFFFFFFF; 3602 nic->tunnel_iface_count = 0xFFFF;
3603 nic->direct_tenant_iface_count = 0xFFFF;
3555 nic->bw_max = 0xFFFFFFFF; 3604 nic->bw_max = 0xFFFFFFFF;
3556} 3605}
3557 3606
3558int be_cmd_config_qos(struct be_adapter *adapter, u32 bps, u8 domain) 3607int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3608 u8 domain)
3559{ 3609{
3560 if (lancer_chip(adapter)) { 3610 struct be_nic_res_desc nic_desc;
3561 struct be_nic_res_desc nic_desc; 3611 u32 bw_percent;
3612 u16 version = 0;
3613
3614 if (BE3_chip(adapter))
3615 return be_cmd_set_qos(adapter, max_rate / 10, domain);
3562 3616
3563 be_reset_nic_desc(&nic_desc); 3617 be_reset_nic_desc(&nic_desc);
3618 nic_desc.pf_num = adapter->pf_number;
3619 nic_desc.vf_num = domain;
3620 if (lancer_chip(adapter)) {
3564 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0; 3621 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3565 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0; 3622 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3566 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) | 3623 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3567 (1 << NOSV_SHIFT); 3624 (1 << NOSV_SHIFT);
3568 nic_desc.pf_num = adapter->pf_number; 3625 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
3569 nic_desc.vf_num = domain;
3570 nic_desc.bw_max = cpu_to_le32(bps);
3571
3572 return be_cmd_set_profile_config(adapter, &nic_desc,
3573 RESOURCE_DESC_SIZE_V0,
3574 0, domain);
3575 } else { 3626 } else {
3576 return be_cmd_set_qos(adapter, bps, domain); 3627 version = 1;
3628 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3629 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3630 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3631 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3632 nic_desc.bw_max = cpu_to_le32(bw_percent);
3577 } 3633 }
3634
3635 return be_cmd_set_profile_config(adapter, &nic_desc,
3636 nic_desc.hdr.desc_len,
3637 version, domain);
3578} 3638}
3579 3639
3580int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op) 3640int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
@@ -3859,7 +3919,7 @@ err:
3859} 3919}
3860 3920
3861int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload, 3921int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3862 int wrb_payload_size, u16 *cmd_status, u16 *ext_status) 3922 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3863{ 3923{
3864 struct be_adapter *adapter = netdev_priv(netdev_handle); 3924 struct be_adapter *adapter = netdev_priv(netdev_handle);
3865 struct be_mcc_wrb *wrb; 3925 struct be_mcc_wrb *wrb;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 02:35:09 -0500