diff options
Diffstat (limited to 'drivers/net/ethernet/dlink/dl2k.h')
-rw-r--r-- | drivers/net/ethernet/dlink/dl2k.h | 110 |
1 files changed, 2 insertions, 108 deletions
diff --git a/drivers/net/ethernet/dlink/dl2k.h b/drivers/net/ethernet/dlink/dl2k.h index 7caab3d26a9e..ba0adcafa55a 100644 --- a/drivers/net/ethernet/dlink/dl2k.h +++ b/drivers/net/ethernet/dlink/dl2k.h | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/init.h> | 28 | #include <linux/init.h> |
29 | #include <linux/crc32.h> | 29 | #include <linux/crc32.h> |
30 | #include <linux/ethtool.h> | 30 | #include <linux/ethtool.h> |
31 | #include <linux/mii.h> | ||
31 | #include <linux/bitops.h> | 32 | #include <linux/bitops.h> |
32 | #include <asm/processor.h> /* Processor type for cache alignment. */ | 33 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
33 | #include <asm/io.h> | 34 | #include <asm/io.h> |
@@ -271,20 +272,9 @@ enum RFS_bits { | |||
271 | #define MII_RESET_TIME_OUT 10000 | 272 | #define MII_RESET_TIME_OUT 10000 |
272 | /* MII register */ | 273 | /* MII register */ |
273 | enum _mii_reg { | 274 | enum _mii_reg { |
274 | MII_BMCR = 0, | ||
275 | MII_BMSR = 1, | ||
276 | MII_PHY_ID1 = 2, | ||
277 | MII_PHY_ID2 = 3, | ||
278 | MII_ANAR = 4, | ||
279 | MII_ANLPAR = 5, | ||
280 | MII_ANER = 6, | ||
281 | MII_ANNPT = 7, | ||
282 | MII_ANLPRNP = 8, | ||
283 | MII_MSCR = 9, | ||
284 | MII_MSSR = 10, | ||
285 | MII_ESR = 15, | ||
286 | MII_PHY_SCR = 16, | 275 | MII_PHY_SCR = 16, |
287 | }; | 276 | }; |
277 | |||
288 | /* PCS register */ | 278 | /* PCS register */ |
289 | enum _pcs_reg { | 279 | enum _pcs_reg { |
290 | PCS_BMCR = 0, | 280 | PCS_BMCR = 0, |
@@ -297,102 +287,6 @@ enum _pcs_reg { | |||
297 | PCS_ESR = 15, | 287 | PCS_ESR = 15, |
298 | }; | 288 | }; |
299 | 289 | ||
300 | /* Basic Mode Control Register */ | ||
301 | enum _mii_bmcr { | ||
302 | MII_BMCR_RESET = 0x8000, | ||
303 | MII_BMCR_LOOP_BACK = 0x4000, | ||
304 | MII_BMCR_SPEED_LSB = 0x2000, | ||
305 | MII_BMCR_AN_ENABLE = 0x1000, | ||
306 | MII_BMCR_POWER_DOWN = 0x0800, | ||
307 | MII_BMCR_ISOLATE = 0x0400, | ||
308 | MII_BMCR_RESTART_AN = 0x0200, | ||
309 | MII_BMCR_DUPLEX_MODE = 0x0100, | ||
310 | MII_BMCR_COL_TEST = 0x0080, | ||
311 | MII_BMCR_SPEED_MSB = 0x0040, | ||
312 | MII_BMCR_SPEED_RESERVED = 0x003f, | ||
313 | MII_BMCR_SPEED_10 = 0, | ||
314 | MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB, | ||
315 | MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB, | ||
316 | }; | ||
317 | |||
318 | /* Basic Mode Status Register */ | ||
319 | enum _mii_bmsr { | ||
320 | MII_BMSR_100BT4 = 0x8000, | ||
321 | MII_BMSR_100BX_FD = 0x4000, | ||
322 | MII_BMSR_100BX_HD = 0x2000, | ||
323 | MII_BMSR_10BT_FD = 0x1000, | ||
324 | MII_BMSR_10BT_HD = 0x0800, | ||
325 | MII_BMSR_100BT2_FD = 0x0400, | ||
326 | MII_BMSR_100BT2_HD = 0x0200, | ||
327 | MII_BMSR_EXT_STATUS = 0x0100, | ||
328 | MII_BMSR_PREAMBLE_SUPP = 0x0040, | ||
329 | MII_BMSR_AN_COMPLETE = 0x0020, | ||
330 | MII_BMSR_REMOTE_FAULT = 0x0010, | ||
331 | MII_BMSR_AN_ABILITY = 0x0008, | ||
332 | MII_BMSR_LINK_STATUS = 0x0004, | ||
333 | MII_BMSR_JABBER_DETECT = 0x0002, | ||
334 | MII_BMSR_EXT_CAP = 0x0001, | ||
335 | }; | ||
336 | |||
337 | /* ANAR */ | ||
338 | enum _mii_anar { | ||
339 | MII_ANAR_NEXT_PAGE = 0x8000, | ||
340 | MII_ANAR_REMOTE_FAULT = 0x4000, | ||
341 | MII_ANAR_ASYMMETRIC = 0x0800, | ||
342 | MII_ANAR_PAUSE = 0x0400, | ||
343 | MII_ANAR_100BT4 = 0x0200, | ||
344 | MII_ANAR_100BX_FD = 0x0100, | ||
345 | MII_ANAR_100BX_HD = 0x0080, | ||
346 | MII_ANAR_10BT_FD = 0x0020, | ||
347 | MII_ANAR_10BT_HD = 0x0010, | ||
348 | MII_ANAR_SELECTOR = 0x001f, | ||
349 | MII_IEEE8023_CSMACD = 0x0001, | ||
350 | }; | ||
351 | |||
352 | /* ANLPAR */ | ||
353 | enum _mii_anlpar { | ||
354 | MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE, | ||
355 | MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT, | ||
356 | MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC, | ||
357 | MII_ANLPAR_PAUSE = MII_ANAR_PAUSE, | ||
358 | MII_ANLPAR_100BT4 = MII_ANAR_100BT4, | ||
359 | MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD, | ||
360 | MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD, | ||
361 | MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD, | ||
362 | MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD, | ||
363 | MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR, | ||
364 | }; | ||
365 | |||
366 | /* Auto-Negotiation Expansion Register */ | ||
367 | enum _mii_aner { | ||
368 | MII_ANER_PAR_DETECT_FAULT = 0x0010, | ||
369 | MII_ANER_LP_NEXTPAGABLE = 0x0008, | ||
370 | MII_ANER_NETXTPAGABLE = 0x0004, | ||
371 | MII_ANER_PAGE_RECEIVED = 0x0002, | ||
372 | MII_ANER_LP_NEGOTIABLE = 0x0001, | ||
373 | }; | ||
374 | |||
375 | /* MASTER-SLAVE Control Register */ | ||
376 | enum _mii_mscr { | ||
377 | MII_MSCR_TEST_MODE = 0xe000, | ||
378 | MII_MSCR_CFG_ENABLE = 0x1000, | ||
379 | MII_MSCR_CFG_VALUE = 0x0800, | ||
380 | MII_MSCR_PORT_VALUE = 0x0400, | ||
381 | MII_MSCR_1000BT_FD = 0x0200, | ||
382 | MII_MSCR_1000BT_HD = 0X0100, | ||
383 | }; | ||
384 | |||
385 | /* MASTER-SLAVE Status Register */ | ||
386 | enum _mii_mssr { | ||
387 | MII_MSSR_CFG_FAULT = 0x8000, | ||
388 | MII_MSSR_CFG_RES = 0x4000, | ||
389 | MII_MSSR_LOCAL_RCV_STATUS = 0x2000, | ||
390 | MII_MSSR_REMOTE_RCVR = 0x1000, | ||
391 | MII_MSSR_LP_1000BT_FD = 0x0800, | ||
392 | MII_MSSR_LP_1000BT_HD = 0x0400, | ||
393 | MII_MSSR_IDLE_ERR_COUNT = 0x00ff, | ||
394 | }; | ||
395 | |||
396 | /* IEEE Extened Status Register */ | 290 | /* IEEE Extened Status Register */ |
397 | enum _mii_esr { | 291 | enum _mii_esr { |
398 | MII_ESR_1000BX_FD = 0x8000, | 292 | MII_ESR_1000BX_FD = 0x8000, |