diff options
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/t4_hw.c')
-rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 106 |
1 files changed, 106 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c index d3c2a516fa88..fb2fe65903c2 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | |||
@@ -2597,6 +2597,112 @@ int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, | |||
2597 | } | 2597 | } |
2598 | 2598 | ||
2599 | /** | 2599 | /** |
2600 | * t4_sge_decode_idma_state - decode the idma state | ||
2601 | * @adap: the adapter | ||
2602 | * @state: the state idma is stuck in | ||
2603 | */ | ||
2604 | void t4_sge_decode_idma_state(struct adapter *adapter, int state) | ||
2605 | { | ||
2606 | static const char * const t4_decode[] = { | ||
2607 | "IDMA_IDLE", | ||
2608 | "IDMA_PUSH_MORE_CPL_FIFO", | ||
2609 | "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", | ||
2610 | "Not used", | ||
2611 | "IDMA_PHYSADDR_SEND_PCIEHDR", | ||
2612 | "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", | ||
2613 | "IDMA_PHYSADDR_SEND_PAYLOAD", | ||
2614 | "IDMA_SEND_FIFO_TO_IMSG", | ||
2615 | "IDMA_FL_REQ_DATA_FL_PREP", | ||
2616 | "IDMA_FL_REQ_DATA_FL", | ||
2617 | "IDMA_FL_DROP", | ||
2618 | "IDMA_FL_H_REQ_HEADER_FL", | ||
2619 | "IDMA_FL_H_SEND_PCIEHDR", | ||
2620 | "IDMA_FL_H_PUSH_CPL_FIFO", | ||
2621 | "IDMA_FL_H_SEND_CPL", | ||
2622 | "IDMA_FL_H_SEND_IP_HDR_FIRST", | ||
2623 | "IDMA_FL_H_SEND_IP_HDR", | ||
2624 | "IDMA_FL_H_REQ_NEXT_HEADER_FL", | ||
2625 | "IDMA_FL_H_SEND_NEXT_PCIEHDR", | ||
2626 | "IDMA_FL_H_SEND_IP_HDR_PADDING", | ||
2627 | "IDMA_FL_D_SEND_PCIEHDR", | ||
2628 | "IDMA_FL_D_SEND_CPL_AND_IP_HDR", | ||
2629 | "IDMA_FL_D_REQ_NEXT_DATA_FL", | ||
2630 | "IDMA_FL_SEND_PCIEHDR", | ||
2631 | "IDMA_FL_PUSH_CPL_FIFO", | ||
2632 | "IDMA_FL_SEND_CPL", | ||
2633 | "IDMA_FL_SEND_PAYLOAD_FIRST", | ||
2634 | "IDMA_FL_SEND_PAYLOAD", | ||
2635 | "IDMA_FL_REQ_NEXT_DATA_FL", | ||
2636 | "IDMA_FL_SEND_NEXT_PCIEHDR", | ||
2637 | "IDMA_FL_SEND_PADDING", | ||
2638 | "IDMA_FL_SEND_COMPLETION_TO_IMSG", | ||
2639 | "IDMA_FL_SEND_FIFO_TO_IMSG", | ||
2640 | "IDMA_FL_REQ_DATAFL_DONE", | ||
2641 | "IDMA_FL_REQ_HEADERFL_DONE", | ||
2642 | }; | ||
2643 | static const char * const t5_decode[] = { | ||
2644 | "IDMA_IDLE", | ||
2645 | "IDMA_ALMOST_IDLE", | ||
2646 | "IDMA_PUSH_MORE_CPL_FIFO", | ||
2647 | "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", | ||
2648 | "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", | ||
2649 | "IDMA_PHYSADDR_SEND_PCIEHDR", | ||
2650 | "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", | ||
2651 | "IDMA_PHYSADDR_SEND_PAYLOAD", | ||
2652 | "IDMA_SEND_FIFO_TO_IMSG", | ||
2653 | "IDMA_FL_REQ_DATA_FL", | ||
2654 | "IDMA_FL_DROP", | ||
2655 | "IDMA_FL_DROP_SEND_INC", | ||
2656 | "IDMA_FL_H_REQ_HEADER_FL", | ||
2657 | "IDMA_FL_H_SEND_PCIEHDR", | ||
2658 | "IDMA_FL_H_PUSH_CPL_FIFO", | ||
2659 | "IDMA_FL_H_SEND_CPL", | ||
2660 | "IDMA_FL_H_SEND_IP_HDR_FIRST", | ||
2661 | "IDMA_FL_H_SEND_IP_HDR", | ||
2662 | "IDMA_FL_H_REQ_NEXT_HEADER_FL", | ||
2663 | "IDMA_FL_H_SEND_NEXT_PCIEHDR", | ||
2664 | "IDMA_FL_H_SEND_IP_HDR_PADDING", | ||
2665 | "IDMA_FL_D_SEND_PCIEHDR", | ||
2666 | "IDMA_FL_D_SEND_CPL_AND_IP_HDR", | ||
2667 | "IDMA_FL_D_REQ_NEXT_DATA_FL", | ||
2668 | "IDMA_FL_SEND_PCIEHDR", | ||
2669 | "IDMA_FL_PUSH_CPL_FIFO", | ||
2670 | "IDMA_FL_SEND_CPL", | ||
2671 | "IDMA_FL_SEND_PAYLOAD_FIRST", | ||
2672 | "IDMA_FL_SEND_PAYLOAD", | ||
2673 | "IDMA_FL_REQ_NEXT_DATA_FL", | ||
2674 | "IDMA_FL_SEND_NEXT_PCIEHDR", | ||
2675 | "IDMA_FL_SEND_PADDING", | ||
2676 | "IDMA_FL_SEND_COMPLETION_TO_IMSG", | ||
2677 | }; | ||
2678 | static const u32 sge_regs[] = { | ||
2679 | SGE_DEBUG_DATA_LOW_INDEX_2, | ||
2680 | SGE_DEBUG_DATA_LOW_INDEX_3, | ||
2681 | SGE_DEBUG_DATA_HIGH_INDEX_10, | ||
2682 | }; | ||
2683 | const char **sge_idma_decode; | ||
2684 | int sge_idma_decode_nstates; | ||
2685 | int i; | ||
2686 | |||
2687 | if (is_t4(adapter->params.chip)) { | ||
2688 | sge_idma_decode = (const char **)t4_decode; | ||
2689 | sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); | ||
2690 | } else { | ||
2691 | sge_idma_decode = (const char **)t5_decode; | ||
2692 | sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); | ||
2693 | } | ||
2694 | |||
2695 | if (state < sge_idma_decode_nstates) | ||
2696 | CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); | ||
2697 | else | ||
2698 | CH_WARN(adapter, "idma state %d unknown\n", state); | ||
2699 | |||
2700 | for (i = 0; i < ARRAY_SIZE(sge_regs); i++) | ||
2701 | CH_WARN(adapter, "SGE register %#x value %#x\n", | ||
2702 | sge_regs[i], t4_read_reg(adapter, sge_regs[i])); | ||
2703 | } | ||
2704 | |||
2705 | /** | ||
2600 | * t4_fw_hello - establish communication with FW | 2706 | * t4_fw_hello - establish communication with FW |
2601 | * @adap: the adapter | 2707 | * @adap: the adapter |
2602 | * @mbox: mailbox to use for the FW command | 2708 | * @mbox: mailbox to use for the FW command |