diff options
Diffstat (limited to 'drivers/net/ethernet/broadcom')
-rw-r--r-- | drivers/net/ethernet/broadcom/Kconfig | 2 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h | 7 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 74 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h | 5 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 57 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/cnic.c | 4 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/tg3.c | 16 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/tg3.h | 1 |
8 files changed, 109 insertions, 57 deletions
diff --git a/drivers/net/ethernet/broadcom/Kconfig b/drivers/net/ethernet/broadcom/Kconfig index a5ea416133a8..c3e260c21734 100644 --- a/drivers/net/ethernet/broadcom/Kconfig +++ b/drivers/net/ethernet/broadcom/Kconfig | |||
@@ -84,7 +84,7 @@ config BNX2 | |||
84 | 84 | ||
85 | config CNIC | 85 | config CNIC |
86 | tristate "QLogic CNIC support" | 86 | tristate "QLogic CNIC support" |
87 | depends on PCI | 87 | depends on PCI && (IPV6 || IPV6=n) |
88 | select BNX2 | 88 | select BNX2 |
89 | select UIO | 89 | select UIO |
90 | ---help--- | 90 | ---help--- |
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h index 5579d4bdbaac..3e0621acdf05 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h | |||
@@ -2233,7 +2233,12 @@ struct shmem2_region { | |||
2233 | u32 reserved3; /* Offset 0x14C */ | 2233 | u32 reserved3; /* Offset 0x14C */ |
2234 | u32 reserved4; /* Offset 0x150 */ | 2234 | u32 reserved4; /* Offset 0x150 */ |
2235 | u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ | 2235 | u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ |
2236 | #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) | 2236 | #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001 |
2237 | #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00 | ||
2238 | #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8 | ||
2239 | #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000 | ||
2240 | #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000 | ||
2241 | #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000 | ||
2237 | 2242 | ||
2238 | u32 reserved5[2]; | 2243 | u32 reserved5[2]; |
2239 | u32 reserved6[PORT_MAX]; | 2244 | u32 reserved6[PORT_MAX]; |
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c index 53fb4fa61b40..549549eaf580 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | |||
@@ -154,15 +154,22 @@ typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, | |||
154 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) | 154 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) |
155 | 155 | ||
156 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 | 156 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
157 | #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 | ||
157 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 | 158 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
158 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 | 159 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
159 | #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 | 160 | #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 |
160 | 161 | ||
161 | 162 | ||
162 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | 163 | #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 |
163 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | 164 | #define SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4) |
164 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | 165 | #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) |
165 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | 166 | #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6) |
167 | |||
168 | #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 | ||
169 | #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0) | ||
170 | #define SFP_EEPROM_1G_COMP_CODE_LX (1<<1) | ||
171 | #define SFP_EEPROM_1G_COMP_CODE_CX (1<<2) | ||
172 | #define SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3) | ||
166 | 173 | ||
167 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 | 174 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
168 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | 175 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 |
@@ -3633,8 +3640,8 @@ static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy, | |||
3633 | reg_set[i].val); | 3640 | reg_set[i].val); |
3634 | 3641 | ||
3635 | /* Start KR2 work-around timer which handles BCM8073 link-parner */ | 3642 | /* Start KR2 work-around timer which handles BCM8073 link-parner */ |
3636 | vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; | 3643 | params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; |
3637 | bnx2x_update_link_attr(params, vars->link_attr_sync); | 3644 | bnx2x_update_link_attr(params, params->link_attr_sync); |
3638 | } | 3645 | } |
3639 | 3646 | ||
3640 | static void bnx2x_disable_kr2(struct link_params *params, | 3647 | static void bnx2x_disable_kr2(struct link_params *params, |
@@ -3666,8 +3673,8 @@ static void bnx2x_disable_kr2(struct link_params *params, | |||
3666 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) | 3673 | for (i = 0; i < ARRAY_SIZE(reg_set); i++) |
3667 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | 3674 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, |
3668 | reg_set[i].val); | 3675 | reg_set[i].val); |
3669 | vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; | 3676 | params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; |
3670 | bnx2x_update_link_attr(params, vars->link_attr_sync); | 3677 | bnx2x_update_link_attr(params, params->link_attr_sync); |
3671 | 3678 | ||
3672 | vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; | 3679 | vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; |
3673 | } | 3680 | } |
@@ -4810,7 +4817,7 @@ void bnx2x_link_status_update(struct link_params *params, | |||
4810 | ~FEATURE_CONFIG_PFC_ENABLED; | 4817 | ~FEATURE_CONFIG_PFC_ENABLED; |
4811 | 4818 | ||
4812 | if (SHMEM2_HAS(bp, link_attr_sync)) | 4819 | if (SHMEM2_HAS(bp, link_attr_sync)) |
4813 | vars->link_attr_sync = SHMEM2_RD(bp, | 4820 | params->link_attr_sync = SHMEM2_RD(bp, |
4814 | link_attr_sync[params->port]); | 4821 | link_attr_sync[params->port]); |
4815 | 4822 | ||
4816 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", | 4823 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", |
@@ -8057,21 +8064,24 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, | |||
8057 | { | 8064 | { |
8058 | struct bnx2x *bp = params->bp; | 8065 | struct bnx2x *bp = params->bp; |
8059 | u32 sync_offset = 0, phy_idx, media_types; | 8066 | u32 sync_offset = 0, phy_idx, media_types; |
8060 | u8 gport, val[2], check_limiting_mode = 0; | 8067 | u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; |
8061 | *edc_mode = EDC_MODE_LIMITING; | 8068 | *edc_mode = EDC_MODE_LIMITING; |
8062 | phy->media_type = ETH_PHY_UNSPECIFIED; | 8069 | phy->media_type = ETH_PHY_UNSPECIFIED; |
8063 | /* First check for copper cable */ | 8070 | /* First check for copper cable */ |
8064 | if (bnx2x_read_sfp_module_eeprom(phy, | 8071 | if (bnx2x_read_sfp_module_eeprom(phy, |
8065 | params, | 8072 | params, |
8066 | I2C_DEV_ADDR_A0, | 8073 | I2C_DEV_ADDR_A0, |
8067 | SFP_EEPROM_CON_TYPE_ADDR, | 8074 | 0, |
8068 | 2, | 8075 | SFP_EEPROM_FC_TX_TECH_ADDR + 1, |
8069 | (u8 *)val) != 0) { | 8076 | (u8 *)val) != 0) { |
8070 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); | 8077 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); |
8071 | return -EINVAL; | 8078 | return -EINVAL; |
8072 | } | 8079 | } |
8073 | 8080 | params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; | |
8074 | switch (val[0]) { | 8081 | params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] << |
8082 | LINK_SFP_EEPROM_COMP_CODE_SHIFT; | ||
8083 | bnx2x_update_link_attr(params, params->link_attr_sync); | ||
8084 | switch (val[SFP_EEPROM_CON_TYPE_ADDR]) { | ||
8075 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: | 8085 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: |
8076 | { | 8086 | { |
8077 | u8 copper_module_type; | 8087 | u8 copper_module_type; |
@@ -8079,17 +8089,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, | |||
8079 | /* Check if its active cable (includes SFP+ module) | 8089 | /* Check if its active cable (includes SFP+ module) |
8080 | * of passive cable | 8090 | * of passive cable |
8081 | */ | 8091 | */ |
8082 | if (bnx2x_read_sfp_module_eeprom(phy, | 8092 | copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR]; |
8083 | params, | ||
8084 | I2C_DEV_ADDR_A0, | ||
8085 | SFP_EEPROM_FC_TX_TECH_ADDR, | ||
8086 | 1, | ||
8087 | &copper_module_type) != 0) { | ||
8088 | DP(NETIF_MSG_LINK, | ||
8089 | "Failed to read copper-cable-type" | ||
8090 | " from SFP+ EEPROM\n"); | ||
8091 | return -EINVAL; | ||
8092 | } | ||
8093 | 8093 | ||
8094 | if (copper_module_type & | 8094 | if (copper_module_type & |
8095 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | 8095 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { |
@@ -8115,16 +8115,18 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, | |||
8115 | } | 8115 | } |
8116 | break; | 8116 | break; |
8117 | } | 8117 | } |
8118 | case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: | ||
8118 | case SFP_EEPROM_CON_TYPE_VAL_LC: | 8119 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
8119 | case SFP_EEPROM_CON_TYPE_VAL_RJ45: | 8120 | case SFP_EEPROM_CON_TYPE_VAL_RJ45: |
8120 | check_limiting_mode = 1; | 8121 | check_limiting_mode = 1; |
8121 | if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | | 8122 | if ((val[SFP_EEPROM_10G_COMP_CODE_ADDR] & |
8122 | SFP_EEPROM_COMP_CODE_LR_MASK | | 8123 | (SFP_EEPROM_10G_COMP_CODE_SR_MASK | |
8123 | SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { | 8124 | SFP_EEPROM_10G_COMP_CODE_LR_MASK | |
8125 | SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) { | ||
8124 | DP(NETIF_MSG_LINK, "1G SFP module detected\n"); | 8126 | DP(NETIF_MSG_LINK, "1G SFP module detected\n"); |
8125 | gport = params->port; | ||
8126 | phy->media_type = ETH_PHY_SFP_1G_FIBER; | 8127 | phy->media_type = ETH_PHY_SFP_1G_FIBER; |
8127 | if (phy->req_line_speed != SPEED_1000) { | 8128 | if (phy->req_line_speed != SPEED_1000) { |
8129 | u8 gport = params->port; | ||
8128 | phy->req_line_speed = SPEED_1000; | 8130 | phy->req_line_speed = SPEED_1000; |
8129 | if (!CHIP_IS_E1x(bp)) { | 8131 | if (!CHIP_IS_E1x(bp)) { |
8130 | gport = BP_PATH(bp) + | 8132 | gport = BP_PATH(bp) + |
@@ -8134,6 +8136,12 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, | |||
8134 | "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", | 8136 | "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n", |
8135 | gport); | 8137 | gport); |
8136 | } | 8138 | } |
8139 | if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] & | ||
8140 | SFP_EEPROM_1G_COMP_CODE_BASE_T) { | ||
8141 | bnx2x_sfp_set_transmitter(params, phy, 0); | ||
8142 | msleep(40); | ||
8143 | bnx2x_sfp_set_transmitter(params, phy, 1); | ||
8144 | } | ||
8137 | } else { | 8145 | } else { |
8138 | int idx, cfg_idx = 0; | 8146 | int idx, cfg_idx = 0; |
8139 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); | 8147 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); |
@@ -8149,7 +8157,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, | |||
8149 | break; | 8157 | break; |
8150 | default: | 8158 | default: |
8151 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", | 8159 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", |
8152 | val[0]); | 8160 | val[SFP_EEPROM_CON_TYPE_ADDR]); |
8153 | return -EINVAL; | 8161 | return -EINVAL; |
8154 | } | 8162 | } |
8155 | sync_offset = params->shmem_base + | 8163 | sync_offset = params->shmem_base + |
@@ -13507,7 +13515,7 @@ static void bnx2x_check_kr2_wa(struct link_params *params, | |||
13507 | 13515 | ||
13508 | sigdet = bnx2x_warpcore_get_sigdet(phy, params); | 13516 | sigdet = bnx2x_warpcore_get_sigdet(phy, params); |
13509 | if (!sigdet) { | 13517 | if (!sigdet) { |
13510 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | 13518 | if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { |
13511 | bnx2x_kr2_recovery(params, vars, phy); | 13519 | bnx2x_kr2_recovery(params, vars, phy); |
13512 | DP(NETIF_MSG_LINK, "No sigdet\n"); | 13520 | DP(NETIF_MSG_LINK, "No sigdet\n"); |
13513 | } | 13521 | } |
@@ -13525,7 +13533,7 @@ static void bnx2x_check_kr2_wa(struct link_params *params, | |||
13525 | 13533 | ||
13526 | /* CL73 has not begun yet */ | 13534 | /* CL73 has not begun yet */ |
13527 | if (base_page == 0) { | 13535 | if (base_page == 0) { |
13528 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | 13536 | if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { |
13529 | bnx2x_kr2_recovery(params, vars, phy); | 13537 | bnx2x_kr2_recovery(params, vars, phy); |
13530 | DP(NETIF_MSG_LINK, "No BP\n"); | 13538 | DP(NETIF_MSG_LINK, "No BP\n"); |
13531 | } | 13539 | } |
@@ -13541,7 +13549,7 @@ static void bnx2x_check_kr2_wa(struct link_params *params, | |||
13541 | ((next_page & 0xe0) == 0x20)))); | 13549 | ((next_page & 0xe0) == 0x20)))); |
13542 | 13550 | ||
13543 | /* In case KR2 is already disabled, check if we need to re-enable it */ | 13551 | /* In case KR2 is already disabled, check if we need to re-enable it */ |
13544 | if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { | 13552 | if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { |
13545 | if (!not_kr2_device) { | 13553 | if (!not_kr2_device) { |
13546 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, | 13554 | DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, |
13547 | next_page); | 13555 | next_page); |
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h index 389f5f8cb0a3..d9cce4c3899b 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h | |||
@@ -323,6 +323,9 @@ struct link_params { | |||
323 | #define LINK_FLAGS_INT_DISABLED (1<<0) | 323 | #define LINK_FLAGS_INT_DISABLED (1<<0) |
324 | #define PHY_INITIALIZED (1<<1) | 324 | #define PHY_INITIALIZED (1<<1) |
325 | u32 lfa_base; | 325 | u32 lfa_base; |
326 | |||
327 | /* The same definitions as the shmem2 parameter */ | ||
328 | u32 link_attr_sync; | ||
326 | }; | 329 | }; |
327 | 330 | ||
328 | /* Output parameters */ | 331 | /* Output parameters */ |
@@ -364,8 +367,6 @@ struct link_vars { | |||
364 | u8 rx_tx_asic_rst; | 367 | u8 rx_tx_asic_rst; |
365 | u8 turn_to_run_wc_rt; | 368 | u8 turn_to_run_wc_rt; |
366 | u16 rsrv2; | 369 | u16 rsrv2; |
367 | /* The same definitions as the shmem2 parameter */ | ||
368 | u32 link_attr_sync; | ||
369 | }; | 370 | }; |
370 | 371 | ||
371 | /***********************************************************/ | 372 | /***********************************************************/ |
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index 93132d8fec67..32e2444ab5e1 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | |||
@@ -6868,6 +6868,37 @@ static void bnx2x__common_init_phy(struct bnx2x *bp) | |||
6868 | bnx2x_release_phy_lock(bp); | 6868 | bnx2x_release_phy_lock(bp); |
6869 | } | 6869 | } |
6870 | 6870 | ||
6871 | static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) | ||
6872 | { | ||
6873 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); | ||
6874 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); | ||
6875 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); | ||
6876 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); | ||
6877 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); | ||
6878 | |||
6879 | /* make sure this value is 0 */ | ||
6880 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | ||
6881 | |||
6882 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); | ||
6883 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); | ||
6884 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); | ||
6885 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); | ||
6886 | } | ||
6887 | |||
6888 | static void bnx2x_set_endianity(struct bnx2x *bp) | ||
6889 | { | ||
6890 | #ifdef __BIG_ENDIAN | ||
6891 | bnx2x_config_endianity(bp, 1); | ||
6892 | #else | ||
6893 | bnx2x_config_endianity(bp, 0); | ||
6894 | #endif | ||
6895 | } | ||
6896 | |||
6897 | static void bnx2x_reset_endianity(struct bnx2x *bp) | ||
6898 | { | ||
6899 | bnx2x_config_endianity(bp, 0); | ||
6900 | } | ||
6901 | |||
6871 | /** | 6902 | /** |
6872 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. | 6903 | * bnx2x_init_hw_common - initialize the HW at the COMMON phase. |
6873 | * | 6904 | * |
@@ -6934,23 +6965,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp) | |||
6934 | 6965 | ||
6935 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); | 6966 | bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); |
6936 | bnx2x_init_pxp(bp); | 6967 | bnx2x_init_pxp(bp); |
6937 | 6968 | bnx2x_set_endianity(bp); | |
6938 | #ifdef __BIG_ENDIAN | ||
6939 | REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1); | ||
6940 | REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1); | ||
6941 | REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1); | ||
6942 | REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1); | ||
6943 | REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1); | ||
6944 | /* make sure this value is 0 */ | ||
6945 | REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); | ||
6946 | |||
6947 | /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */ | ||
6948 | REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1); | ||
6949 | REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1); | ||
6950 | REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1); | ||
6951 | REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); | ||
6952 | #endif | ||
6953 | |||
6954 | bnx2x_ilt_init_page_size(bp, INITOP_SET); | 6969 | bnx2x_ilt_init_page_size(bp, INITOP_SET); |
6955 | 6970 | ||
6956 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) | 6971 | if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) |
@@ -13440,9 +13455,15 @@ static void __bnx2x_remove(struct pci_dev *pdev, | |||
13440 | bnx2x_iov_remove_one(bp); | 13455 | bnx2x_iov_remove_one(bp); |
13441 | 13456 | ||
13442 | /* Power on: we can't let PCI layer write to us while we are in D3 */ | 13457 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
13443 | if (IS_PF(bp)) | 13458 | if (IS_PF(bp)) { |
13444 | bnx2x_set_power_state(bp, PCI_D0); | 13459 | bnx2x_set_power_state(bp, PCI_D0); |
13445 | 13460 | ||
13461 | /* Set endianity registers to reset values in case next driver | ||
13462 | * boots in different endianty environment. | ||
13463 | */ | ||
13464 | bnx2x_reset_endianity(bp); | ||
13465 | } | ||
13466 | |||
13446 | /* Disable MSI/MSI-X */ | 13467 | /* Disable MSI/MSI-X */ |
13447 | bnx2x_disable_msi(bp); | 13468 | bnx2x_disable_msi(bp); |
13448 | 13469 | ||
diff --git a/drivers/net/ethernet/broadcom/cnic.c b/drivers/net/ethernet/broadcom/cnic.c index eef63a8508e6..23f23c97c2ad 100644 --- a/drivers/net/ethernet/broadcom/cnic.c +++ b/drivers/net/ethernet/broadcom/cnic.c | |||
@@ -31,7 +31,7 @@ | |||
31 | #include <linux/if_vlan.h> | 31 | #include <linux/if_vlan.h> |
32 | #include <linux/prefetch.h> | 32 | #include <linux/prefetch.h> |
33 | #include <linux/random.h> | 33 | #include <linux/random.h> |
34 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | 34 | #if IS_ENABLED(CONFIG_VLAN_8021Q) |
35 | #define BCM_VLAN 1 | 35 | #define BCM_VLAN 1 |
36 | #endif | 36 | #endif |
37 | #include <net/ip.h> | 37 | #include <net/ip.h> |
@@ -3685,7 +3685,7 @@ static int cnic_get_v4_route(struct sockaddr_in *dst_addr, | |||
3685 | static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr, | 3685 | static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr, |
3686 | struct dst_entry **dst) | 3686 | struct dst_entry **dst) |
3687 | { | 3687 | { |
3688 | #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE)) | 3688 | #if IS_ENABLED(CONFIG_IPV6) |
3689 | struct flowi6 fl6; | 3689 | struct flowi6 fl6; |
3690 | 3690 | ||
3691 | memset(&fl6, 0, sizeof(fl6)); | 3691 | memset(&fl6, 0, sizeof(fl6)); |
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 3ac5d23454a8..cb77ae93d89a 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c | |||
@@ -11617,6 +11617,12 @@ static int tg3_open(struct net_device *dev) | |||
11617 | struct tg3 *tp = netdev_priv(dev); | 11617 | struct tg3 *tp = netdev_priv(dev); |
11618 | int err; | 11618 | int err; |
11619 | 11619 | ||
11620 | if (tp->pcierr_recovery) { | ||
11621 | netdev_err(dev, "Failed to open device. PCI error recovery " | ||
11622 | "in progress\n"); | ||
11623 | return -EAGAIN; | ||
11624 | } | ||
11625 | |||
11620 | if (tp->fw_needed) { | 11626 | if (tp->fw_needed) { |
11621 | err = tg3_request_firmware(tp); | 11627 | err = tg3_request_firmware(tp); |
11622 | if (tg3_asic_rev(tp) == ASIC_REV_57766) { | 11628 | if (tg3_asic_rev(tp) == ASIC_REV_57766) { |
@@ -11674,6 +11680,12 @@ static int tg3_close(struct net_device *dev) | |||
11674 | { | 11680 | { |
11675 | struct tg3 *tp = netdev_priv(dev); | 11681 | struct tg3 *tp = netdev_priv(dev); |
11676 | 11682 | ||
11683 | if (tp->pcierr_recovery) { | ||
11684 | netdev_err(dev, "Failed to close device. PCI error recovery " | ||
11685 | "in progress\n"); | ||
11686 | return -EAGAIN; | ||
11687 | } | ||
11688 | |||
11677 | tg3_ptp_fini(tp); | 11689 | tg3_ptp_fini(tp); |
11678 | 11690 | ||
11679 | tg3_stop(tp); | 11691 | tg3_stop(tp); |
@@ -17561,6 +17573,7 @@ static int tg3_init_one(struct pci_dev *pdev, | |||
17561 | tp->rx_mode = TG3_DEF_RX_MODE; | 17573 | tp->rx_mode = TG3_DEF_RX_MODE; |
17562 | tp->tx_mode = TG3_DEF_TX_MODE; | 17574 | tp->tx_mode = TG3_DEF_TX_MODE; |
17563 | tp->irq_sync = 1; | 17575 | tp->irq_sync = 1; |
17576 | tp->pcierr_recovery = false; | ||
17564 | 17577 | ||
17565 | if (tg3_debug > 0) | 17578 | if (tg3_debug > 0) |
17566 | tp->msg_enable = tg3_debug; | 17579 | tp->msg_enable = tg3_debug; |
@@ -18071,6 +18084,8 @@ static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |||
18071 | 18084 | ||
18072 | rtnl_lock(); | 18085 | rtnl_lock(); |
18073 | 18086 | ||
18087 | tp->pcierr_recovery = true; | ||
18088 | |||
18074 | /* We probably don't have netdev yet */ | 18089 | /* We probably don't have netdev yet */ |
18075 | if (!netdev || !netif_running(netdev)) | 18090 | if (!netdev || !netif_running(netdev)) |
18076 | goto done; | 18091 | goto done; |
@@ -18195,6 +18210,7 @@ static void tg3_io_resume(struct pci_dev *pdev) | |||
18195 | tg3_phy_start(tp); | 18210 | tg3_phy_start(tp); |
18196 | 18211 | ||
18197 | done: | 18212 | done: |
18213 | tp->pcierr_recovery = false; | ||
18198 | rtnl_unlock(); | 18214 | rtnl_unlock(); |
18199 | } | 18215 | } |
18200 | 18216 | ||
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index 461accaf0aa4..31c9f8295953 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h | |||
@@ -3407,6 +3407,7 @@ struct tg3 { | |||
3407 | 3407 | ||
3408 | struct device *hwmon_dev; | 3408 | struct device *hwmon_dev; |
3409 | bool link_up; | 3409 | bool link_up; |
3410 | bool pcierr_recovery; | ||
3410 | }; | 3411 | }; |
3411 | 3412 | ||
3412 | /* Accessor macros for chip and asic attributes | 3413 | /* Accessor macros for chip and asic attributes |