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-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x.h7
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c41
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h3
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h110
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h3
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c148
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h2
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c464
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h12
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c2
-rw-r--r--drivers/net/ethernet/broadcom/tg3.c5
11 files changed, 596 insertions, 201 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
index e37161f19250..2c9ee552dffc 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
@@ -1173,6 +1173,13 @@ enum {
1173}; 1173};
1174 1174
1175 1175
1176struct bnx2x_prev_path_list {
1177 u8 bus;
1178 u8 slot;
1179 u8 path;
1180 struct list_head list;
1181};
1182
1176struct bnx2x { 1183struct bnx2x {
1177 /* Fields used in the tx and intr/napi performance paths 1184 /* Fields used in the tx and intr/napi performance paths
1178 * are grouped together in the beginning of the structure 1185 * are grouped together in the beginning of the structure
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index f1f3ca65667a..4b054812713a 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -1721,6 +1721,29 @@ static void bnx2x_squeeze_objects(struct bnx2x *bp)
1721 } while (0) 1721 } while (0)
1722#endif 1722#endif
1723 1723
1724bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err)
1725{
1726 /* build FW version dword */
1727 u32 my_fw = (BCM_5710_FW_MAJOR_VERSION) +
1728 (BCM_5710_FW_MINOR_VERSION << 8) +
1729 (BCM_5710_FW_REVISION_VERSION << 16) +
1730 (BCM_5710_FW_ENGINEERING_VERSION << 24);
1731
1732 /* read loaded FW from chip */
1733 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
1734
1735 DP(NETIF_MSG_IFUP, "loaded fw %x, my fw %x\n", loaded_fw, my_fw);
1736
1737 if (loaded_fw != my_fw) {
1738 if (is_err)
1739 BNX2X_ERR("bnx2x with FW %x was already loaded, which mismatches my %x FW. aborting\n",
1740 loaded_fw, my_fw);
1741 return false;
1742 }
1743
1744 return true;
1745}
1746
1724/* must be called with rtnl_lock */ 1747/* must be called with rtnl_lock */
1725int bnx2x_nic_load(struct bnx2x *bp, int load_mode) 1748int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1726{ 1749{
@@ -1815,23 +1838,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1815 } 1838 }
1816 if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP && 1839 if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
1817 load_code != FW_MSG_CODE_DRV_LOAD_COMMON) { 1840 load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
1818 /* build FW version dword */
1819 u32 my_fw = (BCM_5710_FW_MAJOR_VERSION) +
1820 (BCM_5710_FW_MINOR_VERSION << 8) +
1821 (BCM_5710_FW_REVISION_VERSION << 16) +
1822 (BCM_5710_FW_ENGINEERING_VERSION << 24);
1823
1824 /* read loaded FW from chip */
1825 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
1826
1827 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x",
1828 loaded_fw, my_fw);
1829
1830 /* abort nic load if version mismatch */ 1841 /* abort nic load if version mismatch */
1831 if (my_fw != loaded_fw) { 1842 if (!bnx2x_test_firmware_version(bp, true)) {
1832 BNX2X_ERR("bnx2x with FW %x already loaded, "
1833 "which mismatches my %x FW. aborting",
1834 loaded_fw, my_fw);
1835 rc = -EBUSY; 1843 rc = -EBUSY;
1836 LOAD_ERROR_EXIT(bp, load_error2); 1844 LOAD_ERROR_EXIT(bp, load_error2);
1837 } 1845 }
@@ -1866,7 +1874,6 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1866 * bnx2x_periodic_task(). 1874 * bnx2x_periodic_task().
1867 */ 1875 */
1868 smp_mb(); 1876 smp_mb();
1869 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
1870 } else 1877 } else
1871 bp->port.pmf = 0; 1878 bp->port.pmf = 0;
1872 1879
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
index 8b163388659a..5c27454d2ec2 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
@@ -431,6 +431,9 @@ void bnx2x_panic_dump(struct bnx2x *bp);
431 431
432void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 432void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
433 433
434/* validate currect fw is loaded */
435bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err);
436
434/* dev_close main block */ 437/* dev_close main block */
435int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); 438int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
436 439
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
index cd6dfa9eaa3a..b9b263323436 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
@@ -25,31 +25,31 @@
25 (IRO[149].base + ((funcId) * IRO[149].m1)) 25 (IRO[149].base + ((funcId) * IRO[149].m1))
26#define CSTORM_IGU_MODE_OFFSET (IRO[157].base) 26#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
27#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 27#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
28 (IRO[315].base + ((pfId) * IRO[315].m1))
29#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
30 (IRO[316].base + ((pfId) * IRO[316].m1)) 28 (IRO[316].base + ((pfId) * IRO[316].m1))
29#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
30 (IRO[317].base + ((pfId) * IRO[317].m1))
31#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ 31#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
32 (IRO[308].base + ((pfId) * IRO[308].m1) + ((iscsiEqId) * IRO[308].m2)) 32 (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
33#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ 33#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
34 (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2)) 34 (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))
35#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ 35#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
36 (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2)) 36 (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))
37#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ 37#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
38 (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2)) 38 (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))
39#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ 39#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
40 (IRO[307].base + ((pfId) * IRO[307].m1) + ((iscsiEqId) * IRO[307].m2)) 40 (IRO[308].base + ((pfId) * IRO[308].m1) + ((iscsiEqId) * IRO[308].m2))
41#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ 41#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
42 (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2)) 42 (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))
43#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ 43#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
44 (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2)) 44 (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))
45#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 45#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
46 (IRO[314].base + ((pfId) * IRO[314].m1)) 46 (IRO[315].base + ((pfId) * IRO[315].m1))
47#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 47#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
48 (IRO[306].base + ((pfId) * IRO[306].m1)) 48 (IRO[307].base + ((pfId) * IRO[307].m1))
49#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 49#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
50 (IRO[305].base + ((pfId) * IRO[305].m1)) 50 (IRO[306].base + ((pfId) * IRO[306].m1))
51#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 51#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
52 (IRO[304].base + ((pfId) * IRO[304].m1)) 52 (IRO[305].base + ((pfId) * IRO[305].m1))
53#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 53#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
54 (IRO[151].base + ((funcId) * IRO[151].m1)) 54 (IRO[151].base + ((funcId) * IRO[151].m1))
55#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ 55#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
@@ -96,37 +96,37 @@
96#define TSTORM_FUNC_EN_OFFSET(funcId) \ 96#define TSTORM_FUNC_EN_OFFSET(funcId) \
97 (IRO[103].base + ((funcId) * IRO[103].m1)) 97 (IRO[103].base + ((funcId) * IRO[103].m1))
98#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 98#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
99 (IRO[271].base + ((pfId) * IRO[271].m1))
100#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
101 (IRO[272].base + ((pfId) * IRO[272].m1)) 99 (IRO[272].base + ((pfId) * IRO[272].m1))
102#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \ 100#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
103 (IRO[273].base + ((pfId) * IRO[273].m1)) 101 (IRO[273].base + ((pfId) * IRO[273].m1))
104#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \ 102#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
105 (IRO[274].base + ((pfId) * IRO[274].m1)) 103 (IRO[274].base + ((pfId) * IRO[274].m1))
104#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
105 (IRO[275].base + ((pfId) * IRO[275].m1))
106#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 106#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
107 (IRO[270].base + ((pfId) * IRO[270].m1)) 107 (IRO[271].base + ((pfId) * IRO[271].m1))
108#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 108#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
109 (IRO[269].base + ((pfId) * IRO[269].m1)) 109 (IRO[270].base + ((pfId) * IRO[270].m1))
110#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 110#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
111 (IRO[268].base + ((pfId) * IRO[268].m1)) 111 (IRO[269].base + ((pfId) * IRO[269].m1))
112#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 112#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
113 (IRO[267].base + ((pfId) * IRO[267].m1)) 113 (IRO[268].base + ((pfId) * IRO[268].m1))
114#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ 114#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
115 (IRO[276].base + ((pfId) * IRO[276].m1)) 115 (IRO[277].base + ((pfId) * IRO[277].m1))
116#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 116#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
117 (IRO[263].base + ((pfId) * IRO[263].m1))
118#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
119 (IRO[264].base + ((pfId) * IRO[264].m1)) 117 (IRO[264].base + ((pfId) * IRO[264].m1))
120#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \ 118#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
121 (IRO[265].base + ((pfId) * IRO[265].m1)) 119 (IRO[265].base + ((pfId) * IRO[265].m1))
122#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 120#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
123 (IRO[266].base + ((pfId) * IRO[266].m1)) 121 (IRO[266].base + ((pfId) * IRO[266].m1))
122#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
123 (IRO[267].base + ((pfId) * IRO[267].m1))
124#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ 124#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
125 (IRO[202].base + ((pfId) * IRO[202].m1)) 125 (IRO[202].base + ((pfId) * IRO[202].m1))
126#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 126#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
127 (IRO[105].base + ((funcId) * IRO[105].m1)) 127 (IRO[105].base + ((funcId) * IRO[105].m1))
128#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ 128#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
129 (IRO[216].base + ((pfId) * IRO[216].m1)) 129 (IRO[217].base + ((pfId) * IRO[217].m1))
130#define TSTORM_VF_TO_PF_OFFSET(funcId) \ 130#define TSTORM_VF_TO_PF_OFFSET(funcId) \
131 (IRO[104].base + ((funcId) * IRO[104].m1)) 131 (IRO[104].base + ((funcId) * IRO[104].m1))
132#define USTORM_AGG_DATA_OFFSET (IRO[206].base) 132#define USTORM_AGG_DATA_OFFSET (IRO[206].base)
@@ -140,29 +140,29 @@
140#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ 140#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
141 (IRO[183].base + ((portId) * IRO[183].m1)) 141 (IRO[183].base + ((portId) * IRO[183].m1))
142#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ 142#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
143 (IRO[317].base + ((pfId) * IRO[317].m1)) 143 (IRO[318].base + ((pfId) * IRO[318].m1))
144#define USTORM_FUNC_EN_OFFSET(funcId) \ 144#define USTORM_FUNC_EN_OFFSET(funcId) \
145 (IRO[178].base + ((funcId) * IRO[178].m1)) 145 (IRO[178].base + ((funcId) * IRO[178].m1))
146#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 146#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
147 (IRO[281].base + ((pfId) * IRO[281].m1))
148#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
149 (IRO[282].base + ((pfId) * IRO[282].m1)) 147 (IRO[282].base + ((pfId) * IRO[282].m1))
148#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
149 (IRO[283].base + ((pfId) * IRO[283].m1))
150#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 150#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
151 (IRO[286].base + ((pfId) * IRO[286].m1)) 151 (IRO[287].base + ((pfId) * IRO[287].m1))
152#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ 152#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
153 (IRO[283].base + ((pfId) * IRO[283].m1)) 153 (IRO[284].base + ((pfId) * IRO[284].m1))
154#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 154#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
155 (IRO[279].base + ((pfId) * IRO[279].m1)) 155 (IRO[280].base + ((pfId) * IRO[280].m1))
156#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 156#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
157 (IRO[278].base + ((pfId) * IRO[278].m1)) 157 (IRO[279].base + ((pfId) * IRO[279].m1))
158#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 158#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
159 (IRO[277].base + ((pfId) * IRO[277].m1)) 159 (IRO[278].base + ((pfId) * IRO[278].m1))
160#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 160#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
161 (IRO[280].base + ((pfId) * IRO[280].m1)) 161 (IRO[281].base + ((pfId) * IRO[281].m1))
162#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ 162#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
163 (IRO[284].base + ((pfId) * IRO[284].m1))
164#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
165 (IRO[285].base + ((pfId) * IRO[285].m1)) 163 (IRO[285].base + ((pfId) * IRO[285].m1))
164#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
165 (IRO[286].base + ((pfId) * IRO[286].m1))
166#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ 166#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
167 (IRO[182].base + ((pfId) * IRO[182].m1)) 167 (IRO[182].base + ((pfId) * IRO[182].m1))
168#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 168#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
@@ -188,39 +188,39 @@
188#define XSTORM_FUNC_EN_OFFSET(funcId) \ 188#define XSTORM_FUNC_EN_OFFSET(funcId) \
189 (IRO[47].base + ((funcId) * IRO[47].m1)) 189 (IRO[47].base + ((funcId) * IRO[47].m1))
190#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 190#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
191 (IRO[294].base + ((pfId) * IRO[294].m1)) 191 (IRO[295].base + ((pfId) * IRO[295].m1))
192#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ 192#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
193 (IRO[297].base + ((pfId) * IRO[297].m1))
194#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
195 (IRO[298].base + ((pfId) * IRO[298].m1)) 193 (IRO[298].base + ((pfId) * IRO[298].m1))
196#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ 194#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
197 (IRO[299].base + ((pfId) * IRO[299].m1)) 195 (IRO[299].base + ((pfId) * IRO[299].m1))
198#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ 196#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
199 (IRO[300].base + ((pfId) * IRO[300].m1)) 197 (IRO[300].base + ((pfId) * IRO[300].m1))
200#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ 198#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
201 (IRO[301].base + ((pfId) * IRO[301].m1)) 199 (IRO[301].base + ((pfId) * IRO[301].m1))
202#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ 200#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
203 (IRO[302].base + ((pfId) * IRO[302].m1)) 201 (IRO[302].base + ((pfId) * IRO[302].m1))
204#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ 202#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
205 (IRO[303].base + ((pfId) * IRO[303].m1)) 203 (IRO[303].base + ((pfId) * IRO[303].m1))
204#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
205 (IRO[304].base + ((pfId) * IRO[304].m1))
206#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 206#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
207 (IRO[293].base + ((pfId) * IRO[293].m1)) 207 (IRO[294].base + ((pfId) * IRO[294].m1))
208#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 208#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
209 (IRO[292].base + ((pfId) * IRO[292].m1)) 209 (IRO[293].base + ((pfId) * IRO[293].m1))
210#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 210#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
211 (IRO[291].base + ((pfId) * IRO[291].m1)) 211 (IRO[292].base + ((pfId) * IRO[292].m1))
212#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 212#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
213 (IRO[296].base + ((pfId) * IRO[296].m1)) 213 (IRO[297].base + ((pfId) * IRO[297].m1))
214#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ 214#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
215 (IRO[295].base + ((pfId) * IRO[295].m1)) 215 (IRO[296].base + ((pfId) * IRO[296].m1))
216#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ 216#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
217 (IRO[290].base + ((pfId) * IRO[290].m1)) 217 (IRO[291].base + ((pfId) * IRO[291].m1))
218#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 218#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
219 (IRO[289].base + ((pfId) * IRO[289].m1)) 219 (IRO[290].base + ((pfId) * IRO[290].m1))
220#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ 220#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
221 (IRO[288].base + ((pfId) * IRO[288].m1)) 221 (IRO[289].base + ((pfId) * IRO[289].m1))
222#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ 222#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
223 (IRO[287].base + ((pfId) * IRO[287].m1)) 223 (IRO[288].base + ((pfId) * IRO[288].m1))
224#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ 224#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
225 (IRO[44].base + ((pfId) * IRO[44].m1)) 225 (IRO[44].base + ((pfId) * IRO[44].m1))
226#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 226#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
index 5d71b7d43237..dbff5915b81a 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
@@ -1251,6 +1251,9 @@ struct drv_func_mb {
1251 1251
1252 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1252 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1253 1253
1254 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1255 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1256
1254 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1257 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1255 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1258 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1256 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1259 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index beb4cdbdb6e1..ad95324dc042 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -35,7 +35,6 @@
35#define ETH_MAX_PACKET_SIZE 1500 35#define ETH_MAX_PACKET_SIZE 1500
36#define ETH_MAX_JUMBO_PACKET_SIZE 9600 36#define ETH_MAX_JUMBO_PACKET_SIZE 9600
37#define MDIO_ACCESS_TIMEOUT 1000 37#define MDIO_ACCESS_TIMEOUT 1000
38#define BMAC_CONTROL_RX_ENABLE 2
39#define WC_LANE_MAX 4 38#define WC_LANE_MAX 4
40#define I2C_SWITCH_WIDTH 2 39#define I2C_SWITCH_WIDTH 2
41#define I2C_BSC0 0 40#define I2C_BSC0 0
@@ -1372,7 +1371,14 @@ static void bnx2x_update_pfc_xmac(struct link_params *params,
1372 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1371 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1373 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1372 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1374 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1373 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1375 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN; 1374 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1375 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1376 /* Write pause and PFC registers */
1377 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1378 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1379 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1380 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1381
1376 } 1382 }
1377 1383
1378 /* Write pause and PFC registers */ 1384 /* Write pause and PFC registers */
@@ -3649,6 +3655,33 @@ static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3649 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3655 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3650 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); 3656 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3651 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); 3657 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3658 } else if (CHIP_IS_E3(bp) &&
3659 SINGLE_MEDIA_DIRECT(params)) {
3660 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3661 u16 gp_status, gp_mask;
3662 bnx2x_cl45_read(bp, phy,
3663 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3664 &gp_status);
3665 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3666 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3667 lane;
3668 if ((gp_status & gp_mask) == gp_mask) {
3669 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3670 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3671 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3672 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3673 } else {
3674 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3675 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3676 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3677 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3678 ld_pause = ((ld_pause &
3679 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3680 << 3);
3681 lp_pause = ((lp_pause &
3682 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3683 << 3);
3684 }
3652 } else { 3685 } else {
3653 bnx2x_cl45_read(bp, phy, 3686 bnx2x_cl45_read(bp, phy,
3654 MDIO_AN_DEVAD, 3687 MDIO_AN_DEVAD,
@@ -3699,7 +3732,23 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3699 u16 val16 = 0, lane, bam37 = 0; 3732 u16 val16 = 0, lane, bam37 = 0;
3700 struct bnx2x *bp = params->bp; 3733 struct bnx2x *bp = params->bp;
3701 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3734 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3702 3735 /* Set to default registers that may be overriden by 10G force */
3736 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3737 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3738 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3739 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3740 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3741 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0);
3742 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3743 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff);
3744 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3745 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555);
3746 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3747 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0);
3748 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3749 MDIO_WC_REG_RX66_CONTROL, 0x7415);
3750 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3751 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190);
3703 /* Disable Autoneg: re-enable it after adv is done. */ 3752 /* Disable Autoneg: re-enable it after adv is done. */
3704 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3753 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3705 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0); 3754 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
@@ -3945,13 +3994,13 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3945 3994
3946 } else { 3995 } else {
3947 misc1_val |= 0x9; 3996 misc1_val |= 0x9;
3948 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | 3997 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3949 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | 3998 (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3950 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); 3999 (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3951 tx_driver_val = 4000 tx_driver_val =
3952 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | 4001 ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3953 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | 4002 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3954 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); 4003 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3955 } 4004 }
3956 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 4005 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3957 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4006 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
@@ -4369,7 +4418,7 @@ static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4369 switch (serdes_net_if) { 4418 switch (serdes_net_if) {
4370 case PORT_HW_CFG_NET_SERDES_IF_KR: 4419 case PORT_HW_CFG_NET_SERDES_IF_KR:
4371 /* Enable KR Auto Neg */ 4420 /* Enable KR Auto Neg */
4372 if (params->loopback_mode == LOOPBACK_NONE) 4421 if (params->loopback_mode != LOOPBACK_EXT)
4373 bnx2x_warpcore_enable_AN_KR(phy, params, vars); 4422 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4374 else { 4423 else {
4375 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); 4424 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
@@ -6167,12 +6216,14 @@ int bnx2x_set_led(struct link_params *params,
6167 6216
6168 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6217 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6169 if (params->phy[EXT_PHY1].type == 6218 if (params->phy[EXT_PHY1].type ==
6170 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6219 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6171 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp & 0xfff1); 6220 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6172 else { 6221 EMAC_LED_100MB_OVERRIDE |
6173 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6222 EMAC_LED_10MB_OVERRIDE);
6174 (tmp | EMAC_LED_OVERRIDE)); 6223 else
6175 } 6224 tmp |= EMAC_LED_OVERRIDE;
6225
6226 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6176 break; 6227 break;
6177 6228
6178 case LED_MODE_OPER: 6229 case LED_MODE_OPER:
@@ -6227,10 +6278,15 @@ int bnx2x_set_led(struct link_params *params,
6227 hw_led_mode); 6278 hw_led_mode);
6228 } else if ((params->phy[EXT_PHY1].type == 6279 } else if ((params->phy[EXT_PHY1].type ==
6229 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6280 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6230 (mode != LED_MODE_OPER)) { 6281 (mode == LED_MODE_ON)) {
6231 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6282 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6232 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6283 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6233 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 0x3); 6284 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6285 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6286 /* Break here; otherwise, it'll disable the
6287 * intended override.
6288 */
6289 break;
6234 } else 6290 } else
6235 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6291 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6236 hw_led_mode); 6292 hw_led_mode);
@@ -6245,13 +6301,9 @@ int bnx2x_set_led(struct link_params *params,
6245 LED_BLINK_RATE_VAL_E1X_E2); 6301 LED_BLINK_RATE_VAL_E1X_E2);
6246 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6302 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6247 port*4, 1); 6303 port*4, 1);
6248 if ((params->phy[EXT_PHY1].type != 6304 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6249 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 6305 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6250 (mode != LED_MODE_OPER)) { 6306 (tmp & (~EMAC_LED_OVERRIDE)));
6251 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6252 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6253 (tmp & (~EMAC_LED_OVERRIDE)));
6254 }
6255 6307
6256 if (CHIP_IS_E1(bp) && 6308 if (CHIP_IS_E1(bp) &&
6257 ((speed == SPEED_2500) || 6309 ((speed == SPEED_2500) ||
@@ -6844,6 +6896,12 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6844 SINGLE_MEDIA_DIRECT(params)) && 6896 SINGLE_MEDIA_DIRECT(params)) &&
6845 (phy_vars[active_external_phy].fault_detected == 0)); 6897 (phy_vars[active_external_phy].fault_detected == 0));
6846 6898
6899 /* Update the PFC configuration in case it was changed */
6900 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6901 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6902 else
6903 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6904
6847 if (vars->link_up) 6905 if (vars->link_up)
6848 rc = bnx2x_update_link_up(params, vars, link_10g_plus); 6906 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6849 else 6907 else
@@ -8031,7 +8089,9 @@ static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8031 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," 8089 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8032 " Port %d from %s part number %s\n", 8090 " Port %d from %s part number %s\n",
8033 params->port, vendor_name, vendor_pn); 8091 params->port, vendor_name, vendor_pn);
8034 phy->flags |= FLAGS_SFP_NOT_APPROVED; 8092 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8093 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8094 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8035 return -EINVAL; 8095 return -EINVAL;
8036} 8096}
8037 8097
@@ -9091,6 +9151,12 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9091 tmp2 &= 0xFFEF; 9151 tmp2 &= 0xFFEF;
9092 bnx2x_cl45_write(bp, phy, 9152 bnx2x_cl45_write(bp, phy,
9093 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 9153 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9154 bnx2x_cl45_read(bp, phy,
9155 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9156 &tmp2);
9157 bnx2x_cl45_write(bp, phy,
9158 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9159 (tmp2 & 0x7fff));
9094 } 9160 }
9095 9161
9096 return 0; 9162 return 0;
@@ -9271,12 +9337,11 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9271 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9337 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9272 ((1<<5) | (1<<2))); 9338 ((1<<5) | (1<<2)));
9273 } 9339 }
9274 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n"); 9340
9275 bnx2x_8727_specific_func(phy, params, ENABLE_TX); 9341 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9276 /* If transmitter is disabled, ignore false link up indication */ 9342 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9277 bnx2x_cl45_read(bp, phy, 9343 bnx2x_sfp_set_transmitter(params, phy, 1);
9278 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 9344 } else {
9279 if (val1 & (1<<15)) {
9280 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 9345 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9281 return 0; 9346 return 0;
9282 } 9347 }
@@ -9370,8 +9435,7 @@ static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9370 9435
9371 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9436 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9372 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 9437 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9373 bnx2x_save_spirom_version(bp, port, 9438 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9374 ((fw_ver1 & 0xf000)>>5) | (fw_ver1 & 0x7f),
9375 phy->ver_addr); 9439 phy->ver_addr);
9376 } else { 9440 } else {
9377 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 9441 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
@@ -9794,6 +9858,15 @@ static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9794 other_shmem_base_addr)); 9858 other_shmem_base_addr));
9795 9859
9796 u32 shmem_base_path[2]; 9860 u32 shmem_base_path[2];
9861
9862 /* Work around for 84833 LED failure inside RESET status */
9863 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9864 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9865 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9866 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9867 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9868 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9869
9797 shmem_base_path[0] = params->shmem_base; 9870 shmem_base_path[0] = params->shmem_base;
9798 shmem_base_path[1] = other_shmem_base_addr; 9871 shmem_base_path[1] = other_shmem_base_addr;
9799 9872
@@ -10104,7 +10177,7 @@ static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10104 u8 port; 10177 u8 port;
10105 u16 val16; 10178 u16 val16;
10106 10179
10107 if (!(CHIP_IS_E1(bp))) 10180 if (!(CHIP_IS_E1x(bp)))
10108 port = BP_PATH(bp); 10181 port = BP_PATH(bp);
10109 else 10182 else
10110 port = params->port; 10183 port = params->port;
@@ -10131,7 +10204,7 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10131 u16 val; 10204 u16 val;
10132 u8 port; 10205 u8 port;
10133 10206
10134 if (!(CHIP_IS_E1(bp))) 10207 if (!(CHIP_IS_E1x(bp)))
10135 port = BP_PATH(bp); 10208 port = BP_PATH(bp);
10136 else 10209 else
10137 port = params->port; 10210 port = params->port;
@@ -12050,6 +12123,9 @@ int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12050 12123
12051 bnx2x_emac_init(params, vars); 12124 bnx2x_emac_init(params, vars);
12052 12125
12126 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12127 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12128
12053 if (params->num_phys == 0) { 12129 if (params->num_phys == 0) {
12054 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); 12130 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12055 return -EINVAL; 12131 return -EINVAL;
@@ -12129,10 +12205,10 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12129 * Hold it as vars low 12205 * Hold it as vars low
12130 */ 12206 */
12131 /* clear link led */ 12207 /* clear link led */
12208 bnx2x_set_mdio_clk(bp, params->chip_id, port);
12132 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); 12209 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12133 12210
12134 if (reset_ext_phy) { 12211 if (reset_ext_phy) {
12135 bnx2x_set_mdio_clk(bp, params->chip_id, port);
12136 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 12212 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12137 phy_index++) { 12213 phy_index++) {
12138 if (params->phy[phy_index].link_reset) { 12214 if (params->phy[phy_index].link_reset) {
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h
index 7ba557a610da..763535ee4832 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h
@@ -89,6 +89,8 @@
89#define PFC_BRB_FULL_LB_XON_THRESHOLD 250 89#define PFC_BRB_FULL_LB_XON_THRESHOLD 250
90 90
91#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) 91#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
92
93#define BMAC_CONTROL_RX_ENABLE 2
92/***********************************************************/ 94/***********************************************************/
93/* Structs */ 95/* Structs */
94/***********************************************************/ 96/***********************************************************/
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index f7f9aa807264..e077d2508727 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -52,6 +52,7 @@
52#include <linux/prefetch.h> 52#include <linux/prefetch.h>
53#include <linux/zlib.h> 53#include <linux/zlib.h>
54#include <linux/io.h> 54#include <linux/io.h>
55#include <linux/semaphore.h>
55#include <linux/stringify.h> 56#include <linux/stringify.h>
56#include <linux/vmalloc.h> 57#include <linux/vmalloc.h>
57 58
@@ -211,6 +212,10 @@ static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
211 212
212MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 213MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
213 214
215/* Global resources for unloading a previously loaded device */
216#define BNX2X_PREV_WAIT_NEEDED 1
217static DEFINE_SEMAPHORE(bnx2x_prev_sem);
218static LIST_HEAD(bnx2x_prev_list);
214/**************************************************************************** 219/****************************************************************************
215* General service functions 220* General service functions
216****************************************************************************/ 221****************************************************************************/
@@ -8812,109 +8817,371 @@ static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8812 bnx2x_undi_int_disable_e1h(bp); 8817 bnx2x_undi_int_disable_e1h(bp);
8813} 8818}
8814 8819
8815static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 8820static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
8816{ 8821{
8817 u32 val; 8822 u32 val, base_addr, offset, mask, reset_reg;
8823 bool mac_stopped = false;
8824 u8 port = BP_PORT(bp);
8818 8825
8819 /* possibly another driver is trying to reset the chip */ 8826 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
8820 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8821 8827
8822 /* check if doorbell queue is reset */ 8828 if (!CHIP_IS_E3(bp)) {
8823 if (REG_RD(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET) 8829 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
8824 & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 8830 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
8831 if ((mask & reset_reg) && val) {
8832 u32 wb_data[2];
8833 BNX2X_DEV_INFO("Disable bmac Rx\n");
8834 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
8835 : NIG_REG_INGRESS_BMAC0_MEM;
8836 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
8837 : BIGMAC_REGISTER_BMAC_CONTROL;
8825 8838
8826 /* 8839 /*
8827 * Check if it is the UNDI driver 8840 * use rd/wr since we cannot use dmae. This is safe
8841 * since MCP won't access the bus due to the request
8842 * to unload, and no function on the path can be
8843 * loaded at this time.
8844 */
8845 wb_data[0] = REG_RD(bp, base_addr + offset);
8846 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
8847 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
8848 REG_WR(bp, base_addr + offset, wb_data[0]);
8849 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
8850
8851 }
8852 BNX2X_DEV_INFO("Disable emac Rx\n");
8853 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
8854
8855 mac_stopped = true;
8856 } else {
8857 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
8858 BNX2X_DEV_INFO("Disable xmac Rx\n");
8859 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
8860 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
8861 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
8862 val & ~(1 << 1));
8863 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
8864 val | (1 << 1));
8865 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
8866 mac_stopped = true;
8867 }
8868 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
8869 if (mask & reset_reg) {
8870 BNX2X_DEV_INFO("Disable umac Rx\n");
8871 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
8872 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
8873 mac_stopped = true;
8874 }
8875 }
8876
8877 if (mac_stopped)
8878 msleep(20);
8879
8880}
8881
8882#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
8883#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
8884#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
8885#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
8886
8887static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
8888 u8 inc)
8889{
8890 u16 rcq, bd;
8891 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
8892
8893 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
8894 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
8895
8896 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
8897 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
8898
8899 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
8900 port, bd, rcq);
8901}
8902
8903static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
8904{
8905 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8906 if (!rc) {
8907 BNX2X_ERR("MCP response failure, aborting\n");
8908 return -EBUSY;
8909 }
8910
8911 return 0;
8912}
8913
8914static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
8915{
8916 struct bnx2x_prev_path_list *tmp_list;
8917 int rc = false;
8918
8919 if (down_trylock(&bnx2x_prev_sem))
8920 return false;
8921
8922 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
8923 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
8924 bp->pdev->bus->number == tmp_list->bus &&
8925 BP_PATH(bp) == tmp_list->path) {
8926 rc = true;
8927 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
8928 BP_PATH(bp));
8929 break;
8930 }
8931 }
8932
8933 up(&bnx2x_prev_sem);
8934
8935 return rc;
8936}
8937
8938static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
8939{
8940 struct bnx2x_prev_path_list *tmp_list;
8941 int rc;
8942
8943 tmp_list = (struct bnx2x_prev_path_list *)
8944 kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
8945 if (!tmp_list) {
8946 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
8947 return -ENOMEM;
8948 }
8949
8950 tmp_list->bus = bp->pdev->bus->number;
8951 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
8952 tmp_list->path = BP_PATH(bp);
8953
8954 rc = down_interruptible(&bnx2x_prev_sem);
8955 if (rc) {
8956 BNX2X_ERR("Received %d when tried to take lock\n", rc);
8957 kfree(tmp_list);
8958 } else {
8959 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
8960 BP_PATH(bp));
8961 list_add(&tmp_list->list, &bnx2x_prev_list);
8962 up(&bnx2x_prev_sem);
8963 }
8964
8965 return rc;
8966}
8967
8968static bool __devinit bnx2x_can_flr(struct bnx2x *bp)
8969{
8970 int pos;
8971 u32 cap;
8972 struct pci_dev *dev = bp->pdev;
8973
8974 pos = pci_pcie_cap(dev);
8975 if (!pos)
8976 return false;
8977
8978 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
8979 if (!(cap & PCI_EXP_DEVCAP_FLR))
8980 return false;
8981
8982 return true;
8983}
8984
8985static int __devinit bnx2x_do_flr(struct bnx2x *bp)
8986{
8987 int i, pos;
8988 u16 status;
8989 struct pci_dev *dev = bp->pdev;
8990
8991 /* probe the capability first */
8992 if (bnx2x_can_flr(bp))
8993 return -ENOTTY;
8994
8995 pos = pci_pcie_cap(dev);
8996 if (!pos)
8997 return -ENOTTY;
8998
8999 /* Wait for Transaction Pending bit clean */
9000 for (i = 0; i < 4; i++) {
9001 if (i)
9002 msleep((1 << (i - 1)) * 100);
9003
9004 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
9005 if (!(status & PCI_EXP_DEVSTA_TRPND))
9006 goto clear;
9007 }
9008
9009 dev_err(&dev->dev,
9010 "transaction is not cleared; proceeding with reset anyway\n");
9011
9012clear:
9013 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9014 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9015 bp->common.bc_ver);
9016 return -EINVAL;
9017 }
9018
9019 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9020
9021 return 0;
9022}
9023
9024static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9025{
9026 int rc;
9027
9028 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9029
9030 /* Test if previous unload process was already finished for this path */
9031 if (bnx2x_prev_is_path_marked(bp))
9032 return bnx2x_prev_mcp_done(bp);
9033
9034 /* If function has FLR capabilities, and existing FW version matches
9035 * the one required, then FLR will be sufficient to clean any residue
9036 * left by previous driver
9037 */
9038 if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp))
9039 return bnx2x_do_flr(bp);
9040
9041 /* Close the MCP request, return failure*/
9042 rc = bnx2x_prev_mcp_done(bp);
9043 if (!rc)
9044 rc = BNX2X_PREV_WAIT_NEEDED;
9045
9046 return rc;
9047}
9048
9049static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
9050{
9051 u32 reset_reg, tmp_reg = 0, rc;
9052 /* It is possible a previous function received 'common' answer,
9053 * but hasn't loaded yet, therefore creating a scenario of
9054 * multiple functions receiving 'common' on the same path.
9055 */
9056 BNX2X_DEV_INFO("Common unload Flow\n");
9057
9058 if (bnx2x_prev_is_path_marked(bp))
9059 return bnx2x_prev_mcp_done(bp);
9060
9061 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9062
9063 /* Reset should be performed after BRB is emptied */
9064 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9065 u32 timer_count = 1000;
9066 bool prev_undi = false;
9067
9068 /* Close the MAC Rx to prevent BRB from filling up */
9069 bnx2x_prev_unload_close_mac(bp);
9070
9071 /* Check if the UNDI driver was previously loaded
8828 * UNDI driver initializes CID offset for normal bell to 0x7 9072 * UNDI driver initializes CID offset for normal bell to 0x7
8829 */ 9073 */
8830 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 9074 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
8831 if (val == 0x7) { 9075 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
8832 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 9076 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8833 /* save our pf_num */ 9077 if (tmp_reg == 0x7) {
8834 int orig_pf_num = bp->pf_num; 9078 BNX2X_DEV_INFO("UNDI previously loaded\n");
8835 int port; 9079 prev_undi = true;
8836 u32 swap_en, swap_val, value; 9080 /* clear the UNDI indication */
8837 9081 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8838 /* clear the UNDI indication */
8839 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8840
8841 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8842
8843 /* try unload UNDI on port 0 */
8844 bp->pf_num = 0;
8845 bp->fw_seq =
8846 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8847 DRV_MSG_SEQ_NUMBER_MASK);
8848 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8849
8850 /* if UNDI is loaded on the other port */
8851 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8852
8853 /* send "DONE" for previous unload */
8854 bnx2x_fw_command(bp,
8855 DRV_MSG_CODE_UNLOAD_DONE, 0);
8856
8857 /* unload UNDI on port 1 */
8858 bp->pf_num = 1;
8859 bp->fw_seq =
8860 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8861 DRV_MSG_SEQ_NUMBER_MASK);
8862 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8863
8864 bnx2x_fw_command(bp, reset_code, 0);
8865 } 9082 }
9083 }
9084 /* wait until BRB is empty */
9085 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9086 while (timer_count) {
9087 u32 prev_brb = tmp_reg;
8866 9088
8867 bnx2x_undi_int_disable(bp); 9089 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
8868 port = BP_PORT(bp); 9090 if (!tmp_reg)
8869 9091 break;
8870 /* close input traffic and wait for it */
8871 /* Do not rcv packets to BRB */
8872 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8873 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8874 /* Do not direct rcv packets that are not for MCP to
8875 * the BRB */
8876 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8877 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8878 /* clear AEU */
8879 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8880 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8881 msleep(10);
8882
8883 /* save NIG port swap info */
8884 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8885 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8886 /* reset device */
8887 REG_WR(bp,
8888 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8889 0xd3ffffff);
8890
8891 value = 0x1400;
8892 if (CHIP_IS_E3(bp)) {
8893 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8894 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8895 }
8896 9092
8897 REG_WR(bp, 9093 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
8898 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8899 value);
8900 9094
8901 /* take the NIG out of reset and restore swap values */ 9095 /* reset timer as long as BRB actually gets emptied */
8902 REG_WR(bp, 9096 if (prev_brb > tmp_reg)
8903 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 9097 timer_count = 1000;
8904 MISC_REGISTERS_RESET_REG_1_RST_NIG); 9098 else
8905 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); 9099 timer_count--;
8906 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8907 9100
8908 /* send unload done to the MCP */ 9101 /* If UNDI resides in memory, manually increment it */
8909 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 9102 if (prev_undi)
9103 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
8910 9104
8911 /* restore our func and fw_seq */ 9105 udelay(10);
8912 bp->pf_num = orig_pf_num;
8913 } 9106 }
9107
9108 if (!timer_count)
9109 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9110
8914 } 9111 }
8915 9112
8916 /* now it's safe to release the lock */ 9113 /* No packets are in the pipeline, path is ready for reset */
8917 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 9114 bnx2x_reset_common(bp);
9115
9116 rc = bnx2x_prev_mark_path(bp);
9117 if (rc) {
9118 bnx2x_prev_mcp_done(bp);
9119 return rc;
9120 }
9121
9122 return bnx2x_prev_mcp_done(bp);
9123}
9124
9125static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
9126{
9127 int time_counter = 10;
9128 u32 rc, fw, hw_lock_reg, hw_lock_val;
9129 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9130
9131 /* Release previously held locks */
9132 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9133 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9134 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9135
9136 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9137 if (hw_lock_val) {
9138 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9139 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9140 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9141 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9142 }
9143
9144 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9145 REG_WR(bp, hw_lock_reg, 0xffffffff);
9146 } else
9147 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9148
9149 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9150 BNX2X_DEV_INFO("Release previously held alr\n");
9151 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9152 }
9153
9154
9155 do {
9156 /* Lock MCP using an unload request */
9157 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9158 if (!fw) {
9159 BNX2X_ERR("MCP response failure, aborting\n");
9160 rc = -EBUSY;
9161 break;
9162 }
9163
9164 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9165 rc = bnx2x_prev_unload_common(bp);
9166 break;
9167 }
9168
9169 /* non-common reply from MCP night require looping */
9170 rc = bnx2x_prev_unload_uncommon(bp);
9171 if (rc != BNX2X_PREV_WAIT_NEEDED)
9172 break;
9173
9174 msleep(20);
9175 } while (--time_counter);
9176
9177 if (!time_counter || rc) {
9178 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9179 rc = -EBUSY;
9180 }
9181
9182 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9183
9184 return rc;
8918} 9185}
8919 9186
8920static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) 9187static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
@@ -10100,8 +10367,16 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10100 func = BP_FUNC(bp); 10367 func = BP_FUNC(bp);
10101 10368
10102 /* need to reset chip if undi was active */ 10369 /* need to reset chip if undi was active */
10103 if (!BP_NOMCP(bp)) 10370 if (!BP_NOMCP(bp)) {
10104 bnx2x_undi_unload(bp); 10371 /* init fw_seq */
10372 bp->fw_seq =
10373 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10374 DRV_MSG_SEQ_NUMBER_MASK;
10375 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10376
10377 bnx2x_prev_unload(bp);
10378 }
10379
10105 10380
10106 if (CHIP_REV_IS_FPGA(bp)) 10381 if (CHIP_REV_IS_FPGA(bp))
10107 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10382 dev_err(&bp->pdev->dev, "FPGA detected\n");
@@ -11431,9 +11706,18 @@ static int __init bnx2x_init(void)
11431 11706
11432static void __exit bnx2x_cleanup(void) 11707static void __exit bnx2x_cleanup(void)
11433{ 11708{
11709 struct list_head *pos, *q;
11434 pci_unregister_driver(&bnx2x_pci_driver); 11710 pci_unregister_driver(&bnx2x_pci_driver);
11435 11711
11436 destroy_workqueue(bnx2x_wq); 11712 destroy_workqueue(bnx2x_wq);
11713
11714 /* Free globablly allocated resources */
11715 list_for_each_safe(pos, q, &bnx2x_prev_list) {
11716 struct bnx2x_prev_path_list *tmp =
11717 list_entry(pos, struct bnx2x_prev_path_list, list);
11718 list_del(pos);
11719 kfree(tmp);
11720 }
11437} 11721}
11438 11722
11439void bnx2x_notify_link_changed(struct bnx2x *bp) 11723void bnx2x_notify_link_changed(struct bnx2x *bp)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
index fd7fb4581849..c25803b9c0ca 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
@@ -987,6 +987,7 @@
987 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */ 987 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
988#define IGU_REG_WRITE_DONE_PENDING 0x130480 988#define IGU_REG_WRITE_DONE_PENDING 0x130480
989#define MCP_A_REG_MCPR_SCRATCH 0x3a0000 989#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
990#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
990#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 991#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
991#define MCP_REG_MCPR_GP_INPUTS 0x800c0 992#define MCP_REG_MCPR_GP_INPUTS 0x800c0
992#define MCP_REG_MCPR_GP_OENABLE 0x800c8 993#define MCP_REG_MCPR_GP_OENABLE 0x800c8
@@ -1686,6 +1687,7 @@
1686 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] 1687 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1687 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] 1688 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1688 rst_pxp_rq_rd_wr; 31:17] reserved */ 1689 rst_pxp_rq_rd_wr; 31:17] reserved */
1690#define MISC_REG_RESET_REG_1 0xa580
1689#define MISC_REG_RESET_REG_2 0xa590 1691#define MISC_REG_RESET_REG_2 0xa590
1690/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1692/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1691 shared with the driver resides */ 1693 shared with the driver resides */
@@ -5352,6 +5354,7 @@
5352#define XMAC_CTRL_REG_TX_EN (0x1<<0) 5354#define XMAC_CTRL_REG_TX_EN (0x1<<0)
5353#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18) 5355#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5354#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17) 5356#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5357#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1)
5355#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0) 5358#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5356#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3) 5359#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5357#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4) 5360#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
@@ -5606,6 +5609,7 @@
5606/* [RC 32] Parity register #0 read clear */ 5609/* [RC 32] Parity register #0 read clear */
5607#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128 5610#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5608#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138 5611#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
5612#define MCPR_ACCESS_LOCK_LOCK (1L<<31)
5609#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 5613#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5610#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 5614#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5611#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 5615#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
@@ -5732,6 +5736,7 @@
5732#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 5736#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5733#define MISC_REGISTERS_GPIO_SET_POS 8 5737#define MISC_REGISTERS_GPIO_SET_POS 8
5734#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 5738#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5739#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
5735#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19) 5740#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
5736#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29) 5741#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
5737#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) 5742#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
@@ -6816,10 +6821,13 @@ Theotherbitsarereservedandshouldbezero*/
6816 6821
6817#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 6822#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
6818#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 6823#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
6824#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
6819#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 6825#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
6820#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 6826#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
6821#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 6827#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
6822#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 6828#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
6829#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
6830#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
6823#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 6831#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
6824#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 6832#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
6825#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 6833#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
@@ -6939,6 +6947,10 @@ Theotherbitsarereservedandshouldbezero*/
6939#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 6947#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
6940#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 6948#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
6941#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 6949#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
6950#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
6951#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
6952#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
6953#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
6942#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 6954#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
6943#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 6955#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
6944#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 6956#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
index 3f52fadee3ed..513573321625 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
@@ -3847,7 +3847,7 @@ static bool bnx2x_credit_pool_get_entry(
3847 continue; 3847 continue;
3848 3848
3849 /* If we've got here we are going to find a free entry */ 3849 /* If we've got here we are going to find a free entry */
3850 for (idx = vec * BNX2X_POOL_VEC_SIZE, i = 0; 3850 for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0;
3851 i < BIT_VEC64_ELEM_SZ; idx++, i++) 3851 i < BIT_VEC64_ELEM_SZ; idx++, i++)
3852 3852
3853 if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) { 3853 if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) {
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 7b71387cf93c..062ac333fde6 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -48,7 +48,6 @@
48#include <net/checksum.h> 48#include <net/checksum.h>
49#include <net/ip.h> 49#include <net/ip.h>
50 50
51#include <asm/system.h>
52#include <linux/io.h> 51#include <linux/io.h>
53#include <asm/byteorder.h> 52#include <asm/byteorder.h>
54#include <linux/uaccess.h> 53#include <linux/uaccess.h>
@@ -2779,7 +2778,9 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 2778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2780 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || 2779 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2781 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && 2780 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2782 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) 2781 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2782 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2783 !tp->pci_fn))
2783 return; 2784 return;
2784 2785
2785 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || 2786 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 13:01:56 -0500