1 files changed, 49 insertions, 12 deletions

diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 728d42ab2a76..1f2dd928888a 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -94,10 +94,10 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
 
 #define DRV_MODULE_NAME         "tg3"
 #define TG3_MAJ_NUM                     3
-#define TG3_MIN_NUM                     131
+#define TG3_MIN_NUM                     132
 #define DRV_MODULE_VERSION      \
         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
-#define DRV_MODULE_RELDATE      "April 09, 2013"
+#define DRV_MODULE_RELDATE      "May 21, 2013"
 
 #define RESET_KIND_SHUTDOWN     0
 #define RESET_KIND_INIT         1
@@ -2957,6 +2957,31 @@ static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
         return 0;
 }
 
+static bool tg3_phy_power_bug(struct tg3 *tp)
+{
+        switch (tg3_asic_rev(tp)) {
+        case ASIC_REV_5700:
+        case ASIC_REV_5704:
+                return true;
+        case ASIC_REV_5780:
+                if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
+                        return true;
+                return false;
+        case ASIC_REV_5717:
+                if (!tp->pci_fn)
+                        return true;
+                return false;
+        case ASIC_REV_5719:
+        case ASIC_REV_5720:
+                if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
+                    !tp->pci_fn)
+                        return true;
+                return false;
+        }
+
+        return false;
+}
+
 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
 {
         u32 val;
@@ -3016,12 +3041,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
         /* The PHY should not be powered down on some chips because
          * of bugs.
          */
-        if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
-            tg3_asic_rev(tp) == ASIC_REV_5704 ||
-            (tg3_asic_rev(tp) == ASIC_REV_5780 &&
-             (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
-            (tg3_asic_rev(tp) == ASIC_REV_5717 &&
-             !tp->pci_fn))
+        if (tg3_phy_power_bug(tp))
                 return;
 
         if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
@@ -7428,6 +7448,20 @@ static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
         return (base > 0xffffdcc0) && (base + len + 8 < base);
 }
 
+/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
+ * of any 4GB boundaries: 4G, 8G, etc
+ */
+static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
+                                           u32 len, u32 mss)
+{
+        if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
+                u32 base = (u32) mapping & 0xffffffff;
+
+                return ((base + len + (mss & 0x3fff)) < base);
+        }
+        return 0;
+}
+
 /* Test for DMA addresses > 40-bit */
 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
                                           int len)
@@ -7464,6 +7498,9 @@ static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
         if (tg3_4g_overflow_test(map, len))
                 hwbug = true;
 
+        if (tg3_4g_tso_overflow_test(tp, map, len, mss))
+                hwbug = true;
+
         if (tg3_40bit_overflow_test(tp, map, len))
                 hwbug = true;
 
@@ -8874,6 +8911,10 @@ static int tg3_chip_reset(struct tg3 *tp)
                 tg3_halt_cpu(tp, RX_CPU_BASE);
         }
 
+        err = tg3_poll_fw(tp);
+        if (err)
+                return err;
+
         tw32(GRC_MODE, tp->grc_mode);
 
         if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
@@ -8904,10 +8945,6 @@ static int tg3_chip_reset(struct tg3 *tp)
 
         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
 
-        err = tg3_poll_fw(tp);
-        if (err)
-                return err;
-
         tg3_mdio_start(tp);
 
         if (tg3_flag(tp, PCI_EXPRESS) &&