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path: root/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
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Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c')
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c388
1 files changed, 212 insertions, 176 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index 04b9177f46bf..bb2f20291509 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -503,9 +503,9 @@ void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
503} 503}
504 504
505/* issue a dmae command over the init-channel and wait for completion */ 505/* issue a dmae command over the init-channel and wait for completion */
506int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae) 506int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
507 u32 *comp)
507{ 508{
508 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
509 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 509 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
510 int rc = 0; 510 int rc = 0;
511 511
@@ -518,14 +518,14 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
518 spin_lock_bh(&bp->dmae_lock); 518 spin_lock_bh(&bp->dmae_lock);
519 519
520 /* reset completion */ 520 /* reset completion */
521 *wb_comp = 0; 521 *comp = 0;
522 522
523 /* post the command on the channel used for initializations */ 523 /* post the command on the channel used for initializations */
524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
525 525
526 /* wait for completion */ 526 /* wait for completion */
527 udelay(5); 527 udelay(5);
528 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 528 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
529 529
530 if (!cnt || 530 if (!cnt ||
531 (bp->recovery_state != BNX2X_RECOVERY_DONE && 531 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
@@ -537,7 +537,7 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
537 cnt--; 537 cnt--;
538 udelay(50); 538 udelay(50);
539 } 539 }
540 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 540 if (*comp & DMAE_PCI_ERR_FLAG) {
541 BNX2X_ERR("DMAE PCI error!\n"); 541 BNX2X_ERR("DMAE PCI error!\n");
542 rc = DMAE_PCI_ERROR; 542 rc = DMAE_PCI_ERROR;
543 } 543 }
@@ -574,7 +574,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
574 dmae.len = len32; 574 dmae.len = len32;
575 575
576 /* issue the command and wait for completion */ 576 /* issue the command and wait for completion */
577 rc = bnx2x_issue_dmae_with_comp(bp, &dmae); 577 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
578 if (rc) { 578 if (rc) {
579 BNX2X_ERR("DMAE returned failure %d\n", rc); 579 BNX2X_ERR("DMAE returned failure %d\n", rc);
580 bnx2x_panic(); 580 bnx2x_panic();
@@ -611,7 +611,7 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
611 dmae.len = len32; 611 dmae.len = len32;
612 612
613 /* issue the command and wait for completion */ 613 /* issue the command and wait for completion */
614 rc = bnx2x_issue_dmae_with_comp(bp, &dmae); 614 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
615 if (rc) { 615 if (rc) {
616 BNX2X_ERR("DMAE returned failure %d\n", rc); 616 BNX2X_ERR("DMAE returned failure %d\n", rc);
617 bnx2x_panic(); 617 bnx2x_panic();
@@ -751,6 +751,10 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
751 return rc; 751 return rc;
752} 752}
753 753
754#define MCPR_TRACE_BUFFER_SIZE (0x800)
755#define SCRATCH_BUFFER_SIZE(bp) \
756 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
757
754void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 758void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
755{ 759{
756 u32 addr, val; 760 u32 addr, val;
@@ -775,7 +779,17 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
775 trace_shmem_base = bp->common.shmem_base; 779 trace_shmem_base = bp->common.shmem_base;
776 else 780 else
777 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 781 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
778 addr = trace_shmem_base - 0x800; 782
783 /* sanity */
784 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
785 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
786 SCRATCH_BUFFER_SIZE(bp)) {
787 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
788 trace_shmem_base);
789 return;
790 }
791
792 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
779 793
780 /* validate TRCB signature */ 794 /* validate TRCB signature */
781 mark = REG_RD(bp, addr); 795 mark = REG_RD(bp, addr);
@@ -787,14 +801,17 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
787 /* read cyclic buffer pointer */ 801 /* read cyclic buffer pointer */
788 addr += 4; 802 addr += 4;
789 mark = REG_RD(bp, addr); 803 mark = REG_RD(bp, addr);
790 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 804 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
791 + ((mark + 0x3) & ~0x3) - 0x08000000; 805 if (mark >= trace_shmem_base || mark < addr + 4) {
806 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
807 return;
808 }
792 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 809 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
793 810
794 printk("%s", lvl); 811 printk("%s", lvl);
795 812
796 /* dump buffer after the mark */ 813 /* dump buffer after the mark */
797 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) { 814 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
798 for (word = 0; word < 8; word++) 815 for (word = 0; word < 8; word++)
799 data[word] = htonl(REG_RD(bp, offset + 4*word)); 816 data[word] = htonl(REG_RD(bp, offset + 4*word));
800 data[8] = 0x0; 817 data[8] = 0x0;
@@ -4280,65 +4297,60 @@ static void _print_next_block(int idx, const char *blk)
4280 pr_cont("%s%s", idx ? ", " : "", blk); 4297 pr_cont("%s%s", idx ? ", " : "", blk);
4281} 4298}
4282 4299
4283static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, 4300static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4284 int par_num, bool print) 4301 int *par_num, bool print)
4285{ 4302{
4286 int i = 0; 4303 u32 cur_bit;
4287 u32 cur_bit = 0; 4304 bool res;
4305 int i;
4306
4307 res = false;
4308
4288 for (i = 0; sig; i++) { 4309 for (i = 0; sig; i++) {
4289 cur_bit = ((u32)0x1 << i); 4310 cur_bit = (0x1UL << i);
4290 if (sig & cur_bit) { 4311 if (sig & cur_bit) {
4291 switch (cur_bit) { 4312 res |= true; /* Each bit is real error! */
4292 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 4313
4293 if (print) { 4314 if (print) {
4294 _print_next_block(par_num++, "BRB"); 4315 switch (cur_bit) {
4316 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4317 _print_next_block((*par_num)++, "BRB");
4295 _print_parity(bp, 4318 _print_parity(bp,
4296 BRB1_REG_BRB1_PRTY_STS); 4319 BRB1_REG_BRB1_PRTY_STS);
4297 } 4320 break;
4298 break; 4321 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4299 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 4322 _print_next_block((*par_num)++,
4300 if (print) { 4323 "PARSER");
4301 _print_next_block(par_num++, "PARSER");
4302 _print_parity(bp, PRS_REG_PRS_PRTY_STS); 4324 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4303 } 4325 break;
4304 break; 4326 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4305 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 4327 _print_next_block((*par_num)++, "TSDM");
4306 if (print) {
4307 _print_next_block(par_num++, "TSDM");
4308 _print_parity(bp, 4328 _print_parity(bp,
4309 TSDM_REG_TSDM_PRTY_STS); 4329 TSDM_REG_TSDM_PRTY_STS);
4310 } 4330 break;
4311 break; 4331 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4312 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 4332 _print_next_block((*par_num)++,
4313 if (print) {
4314 _print_next_block(par_num++,
4315 "SEARCHER"); 4333 "SEARCHER");
4316 _print_parity(bp, SRC_REG_SRC_PRTY_STS); 4334 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4317 } 4335 break;
4318 break; 4336 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4319 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 4337 _print_next_block((*par_num)++, "TCM");
4320 if (print) { 4338 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4321 _print_next_block(par_num++, "TCM"); 4339 break;
4322 _print_parity(bp, 4340 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4323 TCM_REG_TCM_PRTY_STS); 4341 _print_next_block((*par_num)++,
4324 } 4342 "TSEMI");
4325 break;
4326 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4327 if (print) {
4328 _print_next_block(par_num++, "TSEMI");
4329 _print_parity(bp, 4343 _print_parity(bp,
4330 TSEM_REG_TSEM_PRTY_STS_0); 4344 TSEM_REG_TSEM_PRTY_STS_0);
4331 _print_parity(bp, 4345 _print_parity(bp,
4332 TSEM_REG_TSEM_PRTY_STS_1); 4346 TSEM_REG_TSEM_PRTY_STS_1);
4333 } 4347 break;
4334 break; 4348 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4335 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 4349 _print_next_block((*par_num)++, "XPB");
4336 if (print) {
4337 _print_next_block(par_num++, "XPB");
4338 _print_parity(bp, GRCBASE_XPB + 4350 _print_parity(bp, GRCBASE_XPB +
4339 PB_REG_PB_PRTY_STS); 4351 PB_REG_PB_PRTY_STS);
4352 break;
4340 } 4353 }
4341 break;
4342 } 4354 }
4343 4355
4344 /* Clear the bit */ 4356 /* Clear the bit */
@@ -4346,53 +4358,59 @@ static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4346 } 4358 }
4347 } 4359 }
4348 4360
4349 return par_num; 4361 return res;
4350} 4362}
4351 4363
4352static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, 4364static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4353 int par_num, bool *global, 4365 int *par_num, bool *global,
4354 bool print) 4366 bool print)
4355{ 4367{
4356 int i = 0; 4368 u32 cur_bit;
4357 u32 cur_bit = 0; 4369 bool res;
4370 int i;
4371
4372 res = false;
4373
4358 for (i = 0; sig; i++) { 4374 for (i = 0; sig; i++) {
4359 cur_bit = ((u32)0x1 << i); 4375 cur_bit = (0x1UL << i);
4360 if (sig & cur_bit) { 4376 if (sig & cur_bit) {
4377 res |= true; /* Each bit is real error! */
4361 switch (cur_bit) { 4378 switch (cur_bit) {
4362 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 4379 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4363 if (print) { 4380 if (print) {
4364 _print_next_block(par_num++, "PBF"); 4381 _print_next_block((*par_num)++, "PBF");
4365 _print_parity(bp, PBF_REG_PBF_PRTY_STS); 4382 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4366 } 4383 }
4367 break; 4384 break;
4368 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 4385 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4369 if (print) { 4386 if (print) {
4370 _print_next_block(par_num++, "QM"); 4387 _print_next_block((*par_num)++, "QM");
4371 _print_parity(bp, QM_REG_QM_PRTY_STS); 4388 _print_parity(bp, QM_REG_QM_PRTY_STS);
4372 } 4389 }
4373 break; 4390 break;
4374 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 4391 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4375 if (print) { 4392 if (print) {
4376 _print_next_block(par_num++, "TM"); 4393 _print_next_block((*par_num)++, "TM");
4377 _print_parity(bp, TM_REG_TM_PRTY_STS); 4394 _print_parity(bp, TM_REG_TM_PRTY_STS);
4378 } 4395 }
4379 break; 4396 break;
4380 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4397 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4381 if (print) { 4398 if (print) {
4382 _print_next_block(par_num++, "XSDM"); 4399 _print_next_block((*par_num)++, "XSDM");
4383 _print_parity(bp, 4400 _print_parity(bp,
4384 XSDM_REG_XSDM_PRTY_STS); 4401 XSDM_REG_XSDM_PRTY_STS);
4385 } 4402 }
4386 break; 4403 break;
4387 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4404 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4388 if (print) { 4405 if (print) {
4389 _print_next_block(par_num++, "XCM"); 4406 _print_next_block((*par_num)++, "XCM");
4390 _print_parity(bp, XCM_REG_XCM_PRTY_STS); 4407 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4391 } 4408 }
4392 break; 4409 break;
4393 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4410 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4394 if (print) { 4411 if (print) {
4395 _print_next_block(par_num++, "XSEMI"); 4412 _print_next_block((*par_num)++,
4413 "XSEMI");
4396 _print_parity(bp, 4414 _print_parity(bp,
4397 XSEM_REG_XSEM_PRTY_STS_0); 4415 XSEM_REG_XSEM_PRTY_STS_0);
4398 _print_parity(bp, 4416 _print_parity(bp,
@@ -4401,7 +4419,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4401 break; 4419 break;
4402 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4420 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4403 if (print) { 4421 if (print) {
4404 _print_next_block(par_num++, 4422 _print_next_block((*par_num)++,
4405 "DOORBELLQ"); 4423 "DOORBELLQ");
4406 _print_parity(bp, 4424 _print_parity(bp,
4407 DORQ_REG_DORQ_PRTY_STS); 4425 DORQ_REG_DORQ_PRTY_STS);
@@ -4409,7 +4427,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4409 break; 4427 break;
4410 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4428 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4411 if (print) { 4429 if (print) {
4412 _print_next_block(par_num++, "NIG"); 4430 _print_next_block((*par_num)++, "NIG");
4413 if (CHIP_IS_E1x(bp)) { 4431 if (CHIP_IS_E1x(bp)) {
4414 _print_parity(bp, 4432 _print_parity(bp,
4415 NIG_REG_NIG_PRTY_STS); 4433 NIG_REG_NIG_PRTY_STS);
@@ -4423,32 +4441,34 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4423 break; 4441 break;
4424 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4442 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4425 if (print) 4443 if (print)
4426 _print_next_block(par_num++, 4444 _print_next_block((*par_num)++,
4427 "VAUX PCI CORE"); 4445 "VAUX PCI CORE");
4428 *global = true; 4446 *global = true;
4429 break; 4447 break;
4430 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4448 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4431 if (print) { 4449 if (print) {
4432 _print_next_block(par_num++, "DEBUG"); 4450 _print_next_block((*par_num)++,
4451 "DEBUG");
4433 _print_parity(bp, DBG_REG_DBG_PRTY_STS); 4452 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4434 } 4453 }
4435 break; 4454 break;
4436 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4455 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4437 if (print) { 4456 if (print) {
4438 _print_next_block(par_num++, "USDM"); 4457 _print_next_block((*par_num)++, "USDM");
4439 _print_parity(bp, 4458 _print_parity(bp,
4440 USDM_REG_USDM_PRTY_STS); 4459 USDM_REG_USDM_PRTY_STS);
4441 } 4460 }
4442 break; 4461 break;
4443 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4462 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4444 if (print) { 4463 if (print) {
4445 _print_next_block(par_num++, "UCM"); 4464 _print_next_block((*par_num)++, "UCM");
4446 _print_parity(bp, UCM_REG_UCM_PRTY_STS); 4465 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4447 } 4466 }
4448 break; 4467 break;
4449 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4468 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4450 if (print) { 4469 if (print) {
4451 _print_next_block(par_num++, "USEMI"); 4470 _print_next_block((*par_num)++,
4471 "USEMI");
4452 _print_parity(bp, 4472 _print_parity(bp,
4453 USEM_REG_USEM_PRTY_STS_0); 4473 USEM_REG_USEM_PRTY_STS_0);
4454 _print_parity(bp, 4474 _print_parity(bp,
@@ -4457,21 +4477,21 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4457 break; 4477 break;
4458 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4478 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4459 if (print) { 4479 if (print) {
4460 _print_next_block(par_num++, "UPB"); 4480 _print_next_block((*par_num)++, "UPB");
4461 _print_parity(bp, GRCBASE_UPB + 4481 _print_parity(bp, GRCBASE_UPB +
4462 PB_REG_PB_PRTY_STS); 4482 PB_REG_PB_PRTY_STS);
4463 } 4483 }
4464 break; 4484 break;
4465 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4485 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4466 if (print) { 4486 if (print) {
4467 _print_next_block(par_num++, "CSDM"); 4487 _print_next_block((*par_num)++, "CSDM");
4468 _print_parity(bp, 4488 _print_parity(bp,
4469 CSDM_REG_CSDM_PRTY_STS); 4489 CSDM_REG_CSDM_PRTY_STS);
4470 } 4490 }
4471 break; 4491 break;
4472 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4492 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4473 if (print) { 4493 if (print) {
4474 _print_next_block(par_num++, "CCM"); 4494 _print_next_block((*par_num)++, "CCM");
4475 _print_parity(bp, CCM_REG_CCM_PRTY_STS); 4495 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4476 } 4496 }
4477 break; 4497 break;
@@ -4482,80 +4502,73 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4482 } 4502 }
4483 } 4503 }
4484 4504
4485 return par_num; 4505 return res;
4486} 4506}
4487 4507
4488static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, 4508static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4489 int par_num, bool print) 4509 int *par_num, bool print)
4490{ 4510{
4491 int i = 0; 4511 u32 cur_bit;
4492 u32 cur_bit = 0; 4512 bool res;
4513 int i;
4514
4515 res = false;
4516
4493 for (i = 0; sig; i++) { 4517 for (i = 0; sig; i++) {
4494 cur_bit = ((u32)0x1 << i); 4518 cur_bit = (0x1UL << i);
4495 if (sig & cur_bit) { 4519 if (sig & cur_bit) {
4496 switch (cur_bit) { 4520 res |= true; /* Each bit is real error! */
4497 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4521 if (print) {
4498 if (print) { 4522 switch (cur_bit) {
4499 _print_next_block(par_num++, "CSEMI"); 4523 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4524 _print_next_block((*par_num)++,
4525 "CSEMI");
4500 _print_parity(bp, 4526 _print_parity(bp,
4501 CSEM_REG_CSEM_PRTY_STS_0); 4527 CSEM_REG_CSEM_PRTY_STS_0);
4502 _print_parity(bp, 4528 _print_parity(bp,
4503 CSEM_REG_CSEM_PRTY_STS_1); 4529 CSEM_REG_CSEM_PRTY_STS_1);
4504 } 4530 break;
4505 break; 4531 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4506 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4532 _print_next_block((*par_num)++, "PXP");
4507 if (print) {
4508 _print_next_block(par_num++, "PXP");
4509 _print_parity(bp, PXP_REG_PXP_PRTY_STS); 4533 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4510 _print_parity(bp, 4534 _print_parity(bp,
4511 PXP2_REG_PXP2_PRTY_STS_0); 4535 PXP2_REG_PXP2_PRTY_STS_0);
4512 _print_parity(bp, 4536 _print_parity(bp,
4513 PXP2_REG_PXP2_PRTY_STS_1); 4537 PXP2_REG_PXP2_PRTY_STS_1);
4514 } 4538 break;
4515 break; 4539 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4516 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4540 _print_next_block((*par_num)++,
4517 if (print) 4541 "PXPPCICLOCKCLIENT");
4518 _print_next_block(par_num++, 4542 break;
4519 "PXPPCICLOCKCLIENT"); 4543 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4520 break; 4544 _print_next_block((*par_num)++, "CFC");
4521 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4522 if (print) {
4523 _print_next_block(par_num++, "CFC");
4524 _print_parity(bp, 4545 _print_parity(bp,
4525 CFC_REG_CFC_PRTY_STS); 4546 CFC_REG_CFC_PRTY_STS);
4526 } 4547 break;
4527 break; 4548 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4528 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4549 _print_next_block((*par_num)++, "CDU");
4529 if (print) {
4530 _print_next_block(par_num++, "CDU");
4531 _print_parity(bp, CDU_REG_CDU_PRTY_STS); 4550 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4532 } 4551 break;
4533 break; 4552 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4534 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4553 _print_next_block((*par_num)++, "DMAE");
4535 if (print) {
4536 _print_next_block(par_num++, "DMAE");
4537 _print_parity(bp, 4554 _print_parity(bp,
4538 DMAE_REG_DMAE_PRTY_STS); 4555 DMAE_REG_DMAE_PRTY_STS);
4539 } 4556 break;
4540 break; 4557 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4541 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4558 _print_next_block((*par_num)++, "IGU");
4542 if (print) {
4543 _print_next_block(par_num++, "IGU");
4544 if (CHIP_IS_E1x(bp)) 4559 if (CHIP_IS_E1x(bp))
4545 _print_parity(bp, 4560 _print_parity(bp,
4546 HC_REG_HC_PRTY_STS); 4561 HC_REG_HC_PRTY_STS);
4547 else 4562 else
4548 _print_parity(bp, 4563 _print_parity(bp,
4549 IGU_REG_IGU_PRTY_STS); 4564 IGU_REG_IGU_PRTY_STS);
4550 } 4565 break;
4551 break; 4566 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4552 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4567 _print_next_block((*par_num)++, "MISC");
4553 if (print) {
4554 _print_next_block(par_num++, "MISC");
4555 _print_parity(bp, 4568 _print_parity(bp,
4556 MISC_REG_MISC_PRTY_STS); 4569 MISC_REG_MISC_PRTY_STS);
4570 break;
4557 } 4571 }
4558 break;
4559 } 4572 }
4560 4573
4561 /* Clear the bit */ 4574 /* Clear the bit */
@@ -4563,40 +4576,49 @@ static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4563 } 4576 }
4564 } 4577 }
4565 4578
4566 return par_num; 4579 return res;
4567} 4580}
4568 4581
4569static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num, 4582static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4570 bool *global, bool print) 4583 int *par_num, bool *global,
4584 bool print)
4571{ 4585{
4572 int i = 0; 4586 bool res = false;
4573 u32 cur_bit = 0; 4587 u32 cur_bit;
4588 int i;
4589
4574 for (i = 0; sig; i++) { 4590 for (i = 0; sig; i++) {
4575 cur_bit = ((u32)0x1 << i); 4591 cur_bit = (0x1UL << i);
4576 if (sig & cur_bit) { 4592 if (sig & cur_bit) {
4577 switch (cur_bit) { 4593 switch (cur_bit) {
4578 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4594 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4579 if (print) 4595 if (print)
4580 _print_next_block(par_num++, "MCP ROM"); 4596 _print_next_block((*par_num)++,
4597 "MCP ROM");
4581 *global = true; 4598 *global = true;
4599 res |= true;
4582 break; 4600 break;
4583 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4601 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4584 if (print) 4602 if (print)
4585 _print_next_block(par_num++, 4603 _print_next_block((*par_num)++,
4586 "MCP UMP RX"); 4604 "MCP UMP RX");
4587 *global = true; 4605 *global = true;
4606 res |= true;
4588 break; 4607 break;
4589 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4608 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4590 if (print) 4609 if (print)
4591 _print_next_block(par_num++, 4610 _print_next_block((*par_num)++,
4592 "MCP UMP TX"); 4611 "MCP UMP TX");
4593 *global = true; 4612 *global = true;
4613 res |= true;
4594 break; 4614 break;
4595 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4615 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4596 if (print) 4616 if (print)
4597 _print_next_block(par_num++, 4617 _print_next_block((*par_num)++,
4598 "MCP SCPAD"); 4618 "MCP SCPAD");
4599 *global = true; 4619 /* clear latched SCPAD PATIRY from MCP */
4620 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4621 1UL << 10);
4600 break; 4622 break;
4601 } 4623 }
4602 4624
@@ -4605,45 +4627,50 @@ static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4605 } 4627 }
4606 } 4628 }
4607 4629
4608 return par_num; 4630 return res;
4609} 4631}
4610 4632
4611static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, 4633static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4612 int par_num, bool print) 4634 int *par_num, bool print)
4613{ 4635{
4614 int i = 0; 4636 u32 cur_bit;
4615 u32 cur_bit = 0; 4637 bool res;
4638 int i;
4639
4640 res = false;
4641
4616 for (i = 0; sig; i++) { 4642 for (i = 0; sig; i++) {
4617 cur_bit = ((u32)0x1 << i); 4643 cur_bit = (0x1UL << i);
4618 if (sig & cur_bit) { 4644 if (sig & cur_bit) {
4619 switch (cur_bit) { 4645 res |= true; /* Each bit is real error! */
4620 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4646 if (print) {
4621 if (print) { 4647 switch (cur_bit) {
4622 _print_next_block(par_num++, "PGLUE_B"); 4648 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4649 _print_next_block((*par_num)++,
4650 "PGLUE_B");
4623 _print_parity(bp, 4651 _print_parity(bp,
4624 PGLUE_B_REG_PGLUE_B_PRTY_STS); 4652 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4625 } 4653 break;
4626 break; 4654 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4627 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4655 _print_next_block((*par_num)++, "ATC");
4628 if (print) {
4629 _print_next_block(par_num++, "ATC");
4630 _print_parity(bp, 4656 _print_parity(bp,
4631 ATC_REG_ATC_PRTY_STS); 4657 ATC_REG_ATC_PRTY_STS);
4658 break;
4632 } 4659 }
4633 break;
4634 } 4660 }
4635
4636 /* Clear the bit */ 4661 /* Clear the bit */
4637 sig &= ~cur_bit; 4662 sig &= ~cur_bit;
4638 } 4663 }
4639 } 4664 }
4640 4665
4641 return par_num; 4666 return res;
4642} 4667}
4643 4668
4644static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4669static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4645 u32 *sig) 4670 u32 *sig)
4646{ 4671{
4672 bool res = false;
4673
4647 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4674 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4648 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4675 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4649 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4676 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
@@ -4660,23 +4687,22 @@ static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4660 if (print) 4687 if (print)
4661 netdev_err(bp->dev, 4688 netdev_err(bp->dev,
4662 "Parity errors detected in blocks: "); 4689 "Parity errors detected in blocks: ");
4663 par_num = bnx2x_check_blocks_with_parity0(bp, 4690 res |= bnx2x_check_blocks_with_parity0(bp,
4664 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print); 4691 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4665 par_num = bnx2x_check_blocks_with_parity1(bp, 4692 res |= bnx2x_check_blocks_with_parity1(bp,
4666 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print); 4693 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4667 par_num = bnx2x_check_blocks_with_parity2(bp, 4694 res |= bnx2x_check_blocks_with_parity2(bp,
4668 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print); 4695 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4669 par_num = bnx2x_check_blocks_with_parity3( 4696 res |= bnx2x_check_blocks_with_parity3(bp,
4670 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print); 4697 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4671 par_num = bnx2x_check_blocks_with_parity4(bp, 4698 res |= bnx2x_check_blocks_with_parity4(bp,
4672 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print); 4699 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4673 4700
4674 if (print) 4701 if (print)
4675 pr_cont("\n"); 4702 pr_cont("\n");
4703 }
4676 4704
4677 return true; 4705 return res;
4678 } else
4679 return false;
4680} 4706}
4681 4707
4682/** 4708/**
@@ -7126,7 +7152,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
7126 int port = BP_PORT(bp); 7152 int port = BP_PORT(bp);
7127 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 7153 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7128 u32 low, high; 7154 u32 low, high;
7129 u32 val; 7155 u32 val, reg;
7130 7156
7131 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 7157 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7132 7158
@@ -7271,6 +7297,17 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
7271 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 7297 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7272 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 7298 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7273 7299
7300 /* SCPAD_PARITY should NOT trigger close the gates */
7301 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7302 REG_WR(bp, reg,
7303 REG_RD(bp, reg) &
7304 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7305
7306 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7307 REG_WR(bp, reg,
7308 REG_RD(bp, reg) &
7309 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7310
7274 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7311 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7275 7312
7276 if (!CHIP_IS_E1x(bp)) { 7313 if (!CHIP_IS_E1x(bp)) {
@@ -11693,9 +11730,6 @@ static int bnx2x_init_bp(struct bnx2x *bp)
11693static int bnx2x_open(struct net_device *dev) 11730static int bnx2x_open(struct net_device *dev)
11694{ 11731{
11695 struct bnx2x *bp = netdev_priv(dev); 11732 struct bnx2x *bp = netdev_priv(dev);
11696 bool global = false;
11697 int other_engine = BP_PATH(bp) ? 0 : 1;
11698 bool other_load_status, load_status;
11699 int rc; 11733 int rc;
11700 11734
11701 bp->stats_init = true; 11735 bp->stats_init = true;
@@ -11711,6 +11745,10 @@ static int bnx2x_open(struct net_device *dev)
11711 * Parity recovery is only relevant for PF driver. 11745 * Parity recovery is only relevant for PF driver.
11712 */ 11746 */
11713 if (IS_PF(bp)) { 11747 if (IS_PF(bp)) {
11748 int other_engine = BP_PATH(bp) ? 0 : 1;
11749 bool other_load_status, load_status;
11750 bool global = false;
11751
11714 other_load_status = bnx2x_get_load_status(bp, other_engine); 11752 other_load_status = bnx2x_get_load_status(bp, other_engine);
11715 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 11753 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11716 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 11754 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
@@ -12103,7 +12141,6 @@ static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12103 struct device *dev = &bp->pdev->dev; 12141 struct device *dev = &bp->pdev->dev;
12104 12142
12105 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 12143 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
12106 bp->flags |= USING_DAC_FLAG;
12107 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 12144 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
12108 dev_err(dev, "dma_set_coherent_mask failed, aborting\n"); 12145 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
12109 return -EIO; 12146 return -EIO;
@@ -12274,8 +12311,7 @@ static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12274 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 12311 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12275 12312
12276 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; 12313 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12277 if (bp->flags & USING_DAC_FLAG) 12314 dev->features |= NETIF_F_HIGHDMA;
12278 dev->features |= NETIF_F_HIGHDMA;
12279 12315
12280 /* Add Loopback capability to the device */ 12316 /* Add Loopback capability to the device */
12281 dev->hw_features |= NETIF_F_LOOPBACK; 12317 dev->hw_features |= NETIF_F_LOOPBACK;
@@ -12615,24 +12651,24 @@ static int set_max_cos_est(int chip_id)
12615 return BNX2X_MULTI_TX_COS_E1X; 12651 return BNX2X_MULTI_TX_COS_E1X;
12616 case BCM57712: 12652 case BCM57712:
12617 case BCM57712_MF: 12653 case BCM57712_MF:
12618 case BCM57712_VF:
12619 return BNX2X_MULTI_TX_COS_E2_E3A0; 12654 return BNX2X_MULTI_TX_COS_E2_E3A0;
12620 case BCM57800: 12655 case BCM57800:
12621 case BCM57800_MF: 12656 case BCM57800_MF:
12622 case BCM57800_VF:
12623 case BCM57810: 12657 case BCM57810:
12624 case BCM57810_MF: 12658 case BCM57810_MF:
12625 case BCM57840_4_10: 12659 case BCM57840_4_10:
12626 case BCM57840_2_20: 12660 case BCM57840_2_20:
12627 case BCM57840_O: 12661 case BCM57840_O:
12628 case BCM57840_MFO: 12662 case BCM57840_MFO:
12629 case BCM57810_VF:
12630 case BCM57840_MF: 12663 case BCM57840_MF:
12631 case BCM57840_VF:
12632 case BCM57811: 12664 case BCM57811:
12633 case BCM57811_MF: 12665 case BCM57811_MF:
12634 case BCM57811_VF:
12635 return BNX2X_MULTI_TX_COS_E3B0; 12666 return BNX2X_MULTI_TX_COS_E3B0;
12667 case BCM57712_VF:
12668 case BCM57800_VF:
12669 case BCM57810_VF:
12670 case BCM57840_VF:
12671 case BCM57811_VF:
12636 return 1; 12672 return 1;
12637 default: 12673 default:
12638 pr_err("Unknown board_type (%d), aborting\n", chip_id); 12674 pr_err("Unknown board_type (%d), aborting\n", chip_id);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 21:28:46 -0400