diff options
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c')
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 122 |
1 files changed, 59 insertions, 63 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index dd451c3dd83d..0875ecfe3372 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | |||
@@ -4041,20 +4041,6 @@ static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) | |||
4041 | return val != 0; | 4041 | return val != 0; |
4042 | } | 4042 | } |
4043 | 4043 | ||
4044 | /* | ||
4045 | * Reset the load status for the current engine. | ||
4046 | */ | ||
4047 | static void bnx2x_clear_load_status(struct bnx2x *bp) | ||
4048 | { | ||
4049 | u32 val; | ||
4050 | u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : | ||
4051 | BNX2X_PATH0_LOAD_CNT_MASK); | ||
4052 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | ||
4053 | val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); | ||
4054 | REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask)); | ||
4055 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); | ||
4056 | } | ||
4057 | |||
4058 | static void _print_next_block(int idx, const char *blk) | 4044 | static void _print_next_block(int idx, const char *blk) |
4059 | { | 4045 | { |
4060 | pr_cont("%s%s", idx ? ", " : "", blk); | 4046 | pr_cont("%s%s", idx ? ", " : "", blk); |
@@ -7575,8 +7561,14 @@ int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, | |||
7575 | } | 7561 | } |
7576 | 7562 | ||
7577 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); | 7563 | rc = bnx2x_config_vlan_mac(bp, &ramrod_param); |
7578 | if (rc < 0) | 7564 | |
7565 | if (rc == -EEXIST) { | ||
7566 | DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); | ||
7567 | /* do not treat adding same MAC as error */ | ||
7568 | rc = 0; | ||
7569 | } else if (rc < 0) | ||
7579 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); | 7570 | BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); |
7571 | |||
7580 | return rc; | 7572 | return rc; |
7581 | } | 7573 | } |
7582 | 7574 | ||
@@ -8441,6 +8433,8 @@ unload_error: | |||
8441 | 8433 | ||
8442 | /* Disable HW interrupts, NAPI */ | 8434 | /* Disable HW interrupts, NAPI */ |
8443 | bnx2x_netif_stop(bp, 1); | 8435 | bnx2x_netif_stop(bp, 1); |
8436 | /* Delete all NAPI objects */ | ||
8437 | bnx2x_del_all_napi(bp); | ||
8444 | 8438 | ||
8445 | /* Release IRQs */ | 8439 | /* Release IRQs */ |
8446 | bnx2x_free_irq(bp); | 8440 | bnx2x_free_irq(bp); |
@@ -9384,32 +9378,24 @@ static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp) | |||
9384 | return rc; | 9378 | return rc; |
9385 | } | 9379 | } |
9386 | 9380 | ||
9387 | static bool __devinit bnx2x_can_flr(struct bnx2x *bp) | ||
9388 | { | ||
9389 | int pos; | ||
9390 | u32 cap; | ||
9391 | struct pci_dev *dev = bp->pdev; | ||
9392 | |||
9393 | pos = pci_pcie_cap(dev); | ||
9394 | if (!pos) | ||
9395 | return false; | ||
9396 | |||
9397 | pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); | ||
9398 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | ||
9399 | return false; | ||
9400 | |||
9401 | return true; | ||
9402 | } | ||
9403 | |||
9404 | static int __devinit bnx2x_do_flr(struct bnx2x *bp) | 9381 | static int __devinit bnx2x_do_flr(struct bnx2x *bp) |
9405 | { | 9382 | { |
9406 | int i, pos; | 9383 | int i, pos; |
9407 | u16 status; | 9384 | u16 status; |
9408 | struct pci_dev *dev = bp->pdev; | 9385 | struct pci_dev *dev = bp->pdev; |
9409 | 9386 | ||
9410 | /* probe the capability first */ | 9387 | |
9411 | if (bnx2x_can_flr(bp)) | 9388 | if (CHIP_IS_E1x(bp)) { |
9412 | return -ENOTTY; | 9389 | BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); |
9390 | return -EINVAL; | ||
9391 | } | ||
9392 | |||
9393 | /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ | ||
9394 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | ||
9395 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | ||
9396 | bp->common.bc_ver); | ||
9397 | return -EINVAL; | ||
9398 | } | ||
9413 | 9399 | ||
9414 | pos = pci_pcie_cap(dev); | 9400 | pos = pci_pcie_cap(dev); |
9415 | if (!pos) | 9401 | if (!pos) |
@@ -9429,12 +9415,8 @@ static int __devinit bnx2x_do_flr(struct bnx2x *bp) | |||
9429 | "transaction is not cleared; proceeding with reset anyway\n"); | 9415 | "transaction is not cleared; proceeding with reset anyway\n"); |
9430 | 9416 | ||
9431 | clear: | 9417 | clear: |
9432 | if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { | ||
9433 | BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", | ||
9434 | bp->common.bc_ver); | ||
9435 | return -EINVAL; | ||
9436 | } | ||
9437 | 9418 | ||
9419 | BNX2X_DEV_INFO("Initiating FLR\n"); | ||
9438 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); | 9420 | bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); |
9439 | 9421 | ||
9440 | return 0; | 9422 | return 0; |
@@ -9454,8 +9436,21 @@ static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp) | |||
9454 | * the one required, then FLR will be sufficient to clean any residue | 9436 | * the one required, then FLR will be sufficient to clean any residue |
9455 | * left by previous driver | 9437 | * left by previous driver |
9456 | */ | 9438 | */ |
9457 | if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp)) | 9439 | rc = bnx2x_test_firmware_version(bp, false); |
9458 | return bnx2x_do_flr(bp); | 9440 | |
9441 | if (!rc) { | ||
9442 | /* fw version is good */ | ||
9443 | BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); | ||
9444 | rc = bnx2x_do_flr(bp); | ||
9445 | } | ||
9446 | |||
9447 | if (!rc) { | ||
9448 | /* FLR was performed */ | ||
9449 | BNX2X_DEV_INFO("FLR successful\n"); | ||
9450 | return 0; | ||
9451 | } | ||
9452 | |||
9453 | BNX2X_DEV_INFO("Could not FLR\n"); | ||
9459 | 9454 | ||
9460 | /* Close the MCP request, return failure*/ | 9455 | /* Close the MCP request, return failure*/ |
9461 | rc = bnx2x_prev_mcp_done(bp); | 9456 | rc = bnx2x_prev_mcp_done(bp); |
@@ -9836,12 +9831,13 @@ static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | |||
9836 | } | 9831 | } |
9837 | 9832 | ||
9838 | #ifdef CONFIG_PCI_MSI | 9833 | #ifdef CONFIG_PCI_MSI |
9839 | /* | 9834 | /* Due to new PF resource allocation by MFW T7.4 and above, it's |
9840 | * It's expected that number of CAM entries for this functions is equal | 9835 | * optional that number of CAM entries will not be equal to the value |
9841 | * to the number evaluated based on the MSI-X table size. We want a | 9836 | * advertised in PCI. |
9842 | * harsh warning if these values are different! | 9837 | * Driver should use the minimal value of both as the actual status |
9838 | * block count | ||
9843 | */ | 9839 | */ |
9844 | WARN_ON(bp->igu_sb_cnt != igu_sb_cnt); | 9840 | bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); |
9845 | #endif | 9841 | #endif |
9846 | 9842 | ||
9847 | if (igu_sb_cnt == 0) | 9843 | if (igu_sb_cnt == 0) |
@@ -10305,13 +10301,11 @@ static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp) | |||
10305 | dev_info.port_hw_config[port]. | 10301 | dev_info.port_hw_config[port]. |
10306 | fcoe_wwn_node_name_lower); | 10302 | fcoe_wwn_node_name_lower); |
10307 | } else if (!IS_MF_SD(bp)) { | 10303 | } else if (!IS_MF_SD(bp)) { |
10308 | u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); | ||
10309 | |||
10310 | /* | 10304 | /* |
10311 | * Read the WWN info only if the FCoE feature is enabled for | 10305 | * Read the WWN info only if the FCoE feature is enabled for |
10312 | * this function. | 10306 | * this function. |
10313 | */ | 10307 | */ |
10314 | if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) | 10308 | if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) |
10315 | bnx2x_get_ext_wwn_info(bp, func); | 10309 | bnx2x_get_ext_wwn_info(bp, func); |
10316 | 10310 | ||
10317 | } else if (IS_MF_FCOE_SD(bp)) | 10311 | } else if (IS_MF_FCOE_SD(bp)) |
@@ -11084,7 +11078,14 @@ static int bnx2x_set_uc_list(struct bnx2x *bp) | |||
11084 | netdev_for_each_uc_addr(ha, dev) { | 11078 | netdev_for_each_uc_addr(ha, dev) { |
11085 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, | 11079 | rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, |
11086 | BNX2X_UC_LIST_MAC, &ramrod_flags); | 11080 | BNX2X_UC_LIST_MAC, &ramrod_flags); |
11087 | if (rc < 0) { | 11081 | if (rc == -EEXIST) { |
11082 | DP(BNX2X_MSG_SP, | ||
11083 | "Failed to schedule ADD operations: %d\n", rc); | ||
11084 | /* do not treat adding same MAC as error */ | ||
11085 | rc = 0; | ||
11086 | |||
11087 | } else if (rc < 0) { | ||
11088 | |||
11088 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", | 11089 | BNX2X_ERR("Failed to schedule ADD operations: %d\n", |
11089 | rc); | 11090 | rc); |
11090 | return rc; | 11091 | return rc; |
@@ -11242,10 +11243,12 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |||
11242 | static void poll_bnx2x(struct net_device *dev) | 11243 | static void poll_bnx2x(struct net_device *dev) |
11243 | { | 11244 | { |
11244 | struct bnx2x *bp = netdev_priv(dev); | 11245 | struct bnx2x *bp = netdev_priv(dev); |
11246 | int i; | ||
11245 | 11247 | ||
11246 | disable_irq(bp->pdev->irq); | 11248 | for_each_eth_queue(bp, i) { |
11247 | bnx2x_interrupt(bp->pdev->irq, dev); | 11249 | struct bnx2x_fastpath *fp = &bp->fp[i]; |
11248 | enable_irq(bp->pdev->irq); | 11250 | napi_schedule(&bnx2x_fp(bp, fp->index, napi)); |
11251 | } | ||
11249 | } | 11252 | } |
11250 | #endif | 11253 | #endif |
11251 | 11254 | ||
@@ -11427,9 +11430,6 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev, | |||
11427 | if (!chip_is_e1x) | 11430 | if (!chip_is_e1x) |
11428 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | 11431 | REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); |
11429 | 11432 | ||
11430 | /* Reset the load counter */ | ||
11431 | bnx2x_clear_load_status(bp); | ||
11432 | |||
11433 | dev->watchdog_timeo = TX_TIMEOUT; | 11433 | dev->watchdog_timeo = TX_TIMEOUT; |
11434 | 11434 | ||
11435 | dev->netdev_ops = &bnx2x_netdev_ops; | 11435 | dev->netdev_ops = &bnx2x_netdev_ops; |
@@ -11915,9 +11915,6 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev, | |||
11915 | */ | 11915 | */ |
11916 | bnx2x_set_int_mode(bp); | 11916 | bnx2x_set_int_mode(bp); |
11917 | 11917 | ||
11918 | /* Add all NAPI objects */ | ||
11919 | bnx2x_add_all_napi(bp); | ||
11920 | |||
11921 | rc = register_netdev(dev); | 11918 | rc = register_netdev(dev); |
11922 | if (rc) { | 11919 | if (rc) { |
11923 | dev_err(&pdev->dev, "Cannot register net device\n"); | 11920 | dev_err(&pdev->dev, "Cannot register net device\n"); |
@@ -11992,9 +11989,6 @@ static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |||
11992 | 11989 | ||
11993 | unregister_netdev(dev); | 11990 | unregister_netdev(dev); |
11994 | 11991 | ||
11995 | /* Delete all NAPI objects */ | ||
11996 | bnx2x_del_all_napi(bp); | ||
11997 | |||
11998 | /* Power on: we can't let PCI layer write to us while we are in D3 */ | 11992 | /* Power on: we can't let PCI layer write to us while we are in D3 */ |
11999 | bnx2x_set_power_state(bp, PCI_D0); | 11993 | bnx2x_set_power_state(bp, PCI_D0); |
12000 | 11994 | ||
@@ -12041,6 +12035,8 @@ static int bnx2x_eeh_nic_unload(struct bnx2x *bp) | |||
12041 | bnx2x_tx_disable(bp); | 12035 | bnx2x_tx_disable(bp); |
12042 | 12036 | ||
12043 | bnx2x_netif_stop(bp, 0); | 12037 | bnx2x_netif_stop(bp, 0); |
12038 | /* Delete all NAPI objects */ | ||
12039 | bnx2x_del_all_napi(bp); | ||
12044 | 12040 | ||
12045 | del_timer_sync(&bp->timer); | 12041 | del_timer_sync(&bp->timer); |
12046 | 12042 | ||