1 files changed, 55 insertions, 55 deletions

diff --git a/drivers/net/ethernet/altera/altera_msgdma.c b/drivers/net/ethernet/altera/altera_msgdma.c
index 4d1f2fdd5c32..0fb986ba3290 100644
--- a/drivers/net/ethernet/altera/altera_msgdma.c
+++ b/drivers/net/ethernet/altera/altera_msgdma.c
@@ -37,18 +37,16 @@ void msgdma_start_rxdma(struct altera_tse_private *priv)
 void msgdma_reset(struct altera_tse_private *priv)
 {
         int counter;
-        struct msgdma_csr *txcsr =
-                (struct msgdma_csr *)priv->tx_dma_csr;
-        struct msgdma_csr *rxcsr =
-                (struct msgdma_csr *)priv->rx_dma_csr;
 
         /* Reset Rx mSGDMA */
-        iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status);
-        iowrite32(MSGDMA_CSR_CTL_RESET, &rxcsr->control);
+        csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
+                msgdma_csroffs(status));
+        csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
+                msgdma_csroffs(control));
 
         counter = 0;
         while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
-                if (tse_bit_is_clear(&rxcsr->status,
+                if (tse_bit_is_clear(priv->rx_dma_csr, msgdma_csroffs(status),
                                      MSGDMA_CSR_STAT_RESETTING))
                         break;
                 udelay(1);
@@ -59,15 +57,18 @@ void msgdma_reset(struct altera_tse_private *priv)
                            "TSE Rx mSGDMA resetting bit never cleared!\n");
 
         /* clear all status bits */
-        iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status);
+        csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));
 
         /* Reset Tx mSGDMA */
-        iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status);
-        iowrite32(MSGDMA_CSR_CTL_RESET, &txcsr->control);
+        csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
+                msgdma_csroffs(status));
+
+        csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
+                msgdma_csroffs(control));
 
         counter = 0;
         while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
-                if (tse_bit_is_clear(&txcsr->status,
+                if (tse_bit_is_clear(priv->tx_dma_csr, msgdma_csroffs(status),
                                      MSGDMA_CSR_STAT_RESETTING))
                         break;
                 udelay(1);
@@ -78,58 +79,58 @@ void msgdma_reset(struct altera_tse_private *priv)
                            "TSE Tx mSGDMA resetting bit never cleared!\n");
 
         /* clear all status bits */
-        iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status);
+        csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
 }
 
 void msgdma_disable_rxirq(struct altera_tse_private *priv)
 {
-        struct msgdma_csr *csr = priv->rx_dma_csr;
-        tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
+        tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control),
+                      MSGDMA_CSR_CTL_GLOBAL_INTR);
 }
 
 void msgdma_enable_rxirq(struct altera_tse_private *priv)
 {
-        struct msgdma_csr *csr = priv->rx_dma_csr;
-        tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
+        tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control),
+                    MSGDMA_CSR_CTL_GLOBAL_INTR);
 }
 
 void msgdma_disable_txirq(struct altera_tse_private *priv)
 {
-        struct msgdma_csr *csr = priv->tx_dma_csr;
-        tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
+        tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control),
+                      MSGDMA_CSR_CTL_GLOBAL_INTR);
 }
 
 void msgdma_enable_txirq(struct altera_tse_private *priv)
 {
-        struct msgdma_csr *csr = priv->tx_dma_csr;
-        tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR);
+        tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control),
+                    MSGDMA_CSR_CTL_GLOBAL_INTR);
 }
 
 void msgdma_clear_rxirq(struct altera_tse_private *priv)
 {
-        struct msgdma_csr *csr = priv->rx_dma_csr;
-        iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
+        csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
 }
 
 void msgdma_clear_txirq(struct altera_tse_private *priv)
 {
-        struct msgdma_csr *csr = priv->tx_dma_csr;
-        iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
+        csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
 }
 
 /* return 0 to indicate transmit is pending */
 int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
 {
-        struct msgdma_extended_desc *desc = priv->tx_dma_desc;
-
-        iowrite32(lower_32_bits(buffer->dma_addr), &desc->read_addr_lo);
-        iowrite32(upper_32_bits(buffer->dma_addr), &desc->read_addr_hi);
-        iowrite32(0, &desc->write_addr_lo);
-        iowrite32(0, &desc->write_addr_hi);
-        iowrite32(buffer->len, &desc->len);
-        iowrite32(0, &desc->burst_seq_num);
-        iowrite32(MSGDMA_DESC_TX_STRIDE, &desc->stride);
-        iowrite32(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
+        csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
+                msgdma_descroffs(read_addr_lo));
+        csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
+                msgdma_descroffs(read_addr_hi));
+        csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
+        csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
+        csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
+        csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
+        csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
+                msgdma_descroffs(stride));
+        csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
+                msgdma_descroffs(control));
         return 0;
 }
 
@@ -138,17 +139,16 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv)
         u32 ready = 0;
         u32 inuse;
         u32 status;
-        struct msgdma_csr *txcsr =
-                (struct msgdma_csr *)priv->tx_dma_csr;
 
         /* Get number of sent descriptors */
-        inuse = ioread32(&txcsr->rw_fill_level) & 0xffff;
+        inuse = csrrd32(priv->tx_dma_csr, msgdma_csroffs(rw_fill_level))
+                        & 0xffff;
 
         if (inuse) { /* Tx FIFO is not empty */
                 ready = priv->tx_prod - priv->tx_cons - inuse - 1;
         } else {
                 /* Check for buffered last packet */
-                status = ioread32(&txcsr->status);
+                status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
                 if (status & MSGDMA_CSR_STAT_BUSY)
                         ready = priv->tx_prod - priv->tx_cons - 1;
                 else
@@ -162,7 +162,6 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv)
 void msgdma_add_rx_desc(struct altera_tse_private *priv,
                         struct tse_buffer *rxbuffer)
 {
-        struct msgdma_extended_desc *desc = priv->rx_dma_desc;
         u32 len = priv->rx_dma_buf_sz;
         dma_addr_t dma_addr = rxbuffer->dma_addr;
         u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
@@ -172,14 +171,16 @@ void msgdma_add_rx_desc(struct altera_tse_private *priv,
                         | MSGDMA_DESC_CTL_TR_ERR_IRQ
                         | MSGDMA_DESC_CTL_GO);
 
-        iowrite32(0, &desc->read_addr_lo);
-        iowrite32(0, &desc->read_addr_hi);
-        iowrite32(lower_32_bits(dma_addr), &desc->write_addr_lo);
-        iowrite32(upper_32_bits(dma_addr), &desc->write_addr_hi);
-        iowrite32(len, &desc->len);
-        iowrite32(0, &desc->burst_seq_num);
-        iowrite32(0x00010001, &desc->stride);
-        iowrite32(control, &desc->control);
+        csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
+        csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
+        csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
+                msgdma_descroffs(write_addr_lo));
+        csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
+                msgdma_descroffs(write_addr_hi));
+        csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
+        csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
+        csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
+        csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
 }
 
 /* status is returned on upper 16 bits,
@@ -190,14 +191,13 @@ u32 msgdma_rx_status(struct altera_tse_private *priv)
         u32 rxstatus = 0;
         u32 pktlength;
         u32 pktstatus;
-        struct msgdma_csr *rxcsr =
-                (struct msgdma_csr *)priv->rx_dma_csr;
-        struct msgdma_response *rxresp =
-                (struct msgdma_response *)priv->rx_dma_resp;
-
-        if (ioread32(&rxcsr->resp_fill_level) & 0xffff) {
-                pktlength = ioread32(&rxresp->bytes_transferred);
-                pktstatus = ioread32(&rxresp->status);
+
+        if (csrrd32(priv->rx_dma_csr, msgdma_csroffs(resp_fill_level))
+            & 0xffff) {
+                pktlength = csrrd32(priv->rx_dma_resp,
+                                    msgdma_respoffs(bytes_transferred));
+                pktstatus = csrrd32(priv->rx_dma_resp,
+                                    msgdma_respoffs(status));
                 rxstatus = pktstatus;
                 rxstatus = rxstatus << 16;
                 rxstatus |= (pktlength & 0xffff);