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Diffstat (limited to 'drivers/net/e1000e/hw.h')
-rw-r--r--drivers/net/e1000e/hw.h173
1 files changed, 89 insertions, 84 deletions
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index 916025b30fc3..53f1ac6327fa 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel PRO/1000 Linux driver 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation. 4 Copyright(c) 1999 - 2008 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -66,14 +66,14 @@ enum e1e_registers {
66 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */ 66 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
67 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */ 67 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
68 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */ 68 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
69 E1000_RCTL = 0x00100, /* RX Control - RW */ 69 E1000_RCTL = 0x00100, /* Rx Control - RW */
70 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */ 70 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
71 E1000_TXCW = 0x00178, /* TX Configuration Word - RW */ 71 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
72 E1000_RXCW = 0x00180, /* RX Configuration Word - RO */ 72 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
73 E1000_TCTL = 0x00400, /* TX Control - RW */ 73 E1000_TCTL = 0x00400, /* Tx Control - RW */
74 E1000_TCTL_EXT = 0x00404, /* Extended TX Control - RW */ 74 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
75 E1000_TIPG = 0x00410, /* TX Inter-packet gap -RW */ 75 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
76 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle - RW */ 76 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
77 E1000_LEDCTL = 0x00E00, /* LED Control - RW */ 77 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
78 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */ 78 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
79 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */ 79 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
@@ -87,12 +87,14 @@ enum e1e_registers {
87 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */ 87 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
88 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */ 88 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
89 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */ 89 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
90 E1000_RDBAL = 0x02800, /* RX Descriptor Base Address Low - RW */ 90 E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */
91 E1000_RDBAH = 0x02804, /* RX Descriptor Base Address High - RW */ 91 E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */
92 E1000_RDLEN = 0x02808, /* RX Descriptor Length - RW */ 92 E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */
93 E1000_RDH = 0x02810, /* RX Descriptor Head - RW */ 93 E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */
94 E1000_RDT = 0x02818, /* RX Descriptor Tail - RW */ 94 E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */
95 E1000_RDTR = 0x02820, /* RX Delay Timer - RW */ 95 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
96 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
97#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
96 E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */ 98 E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
97 99
98/* Convenience macros 100/* Convenience macros
@@ -105,17 +107,17 @@ enum e1e_registers {
105 */ 107 */
106#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8)) 108#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
107 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */ 109 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
108 E1000_TDBAL = 0x03800, /* TX Descriptor Base Address Low - RW */ 110 E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */
109 E1000_TDBAH = 0x03804, /* TX Descriptor Base Address High - RW */ 111 E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */
110 E1000_TDLEN = 0x03808, /* TX Descriptor Length - RW */ 112 E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */
111 E1000_TDH = 0x03810, /* TX Descriptor Head - RW */ 113 E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */
112 E1000_TDT = 0x03818, /* TX Descriptor Tail - RW */ 114 E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */
113 E1000_TIDV = 0x03820, /* TX Interrupt Delay Value - RW */ 115 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
114 E1000_TXDCTL = 0x03828, /* TX Descriptor Control - RW */ 116 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
115 E1000_TADV = 0x0382C, /* TX Interrupt Absolute Delay Val - RW */ 117#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
116 E1000_TARC0 = 0x03840, /* TX Arbitration Count (0) */ 118 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
117 E1000_TXDCTL1 = 0x03928, /* TX Descriptor Control (1) - RW */ 119 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
118 E1000_TARC1 = 0x03940, /* TX Arbitration Count (1) */ 120#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
119 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */ 121 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
120 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */ 122 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
121 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */ 123 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
@@ -127,53 +129,53 @@ enum e1e_registers {
127 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */ 129 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
128 E1000_COLC = 0x04028, /* Collision Count - R/clr */ 130 E1000_COLC = 0x04028, /* Collision Count - R/clr */
129 E1000_DC = 0x04030, /* Defer Count - R/clr */ 131 E1000_DC = 0x04030, /* Defer Count - R/clr */
130 E1000_TNCRS = 0x04034, /* TX-No CRS - R/clr */ 132 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
131 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */ 133 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
132 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */ 134 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
133 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */ 135 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
134 E1000_XONRXC = 0x04048, /* XON RX Count - R/clr */ 136 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
135 E1000_XONTXC = 0x0404C, /* XON TX Count - R/clr */ 137 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
136 E1000_XOFFRXC = 0x04050, /* XOFF RX Count - R/clr */ 138 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
137 E1000_XOFFTXC = 0x04054, /* XOFF TX Count - R/clr */ 139 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
138 E1000_FCRUC = 0x04058, /* Flow Control RX Unsupported Count- R/clr */ 140 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
139 E1000_PRC64 = 0x0405C, /* Packets RX (64 bytes) - R/clr */ 141 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
140 E1000_PRC127 = 0x04060, /* Packets RX (65-127 bytes) - R/clr */ 142 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
141 E1000_PRC255 = 0x04064, /* Packets RX (128-255 bytes) - R/clr */ 143 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
142 E1000_PRC511 = 0x04068, /* Packets RX (255-511 bytes) - R/clr */ 144 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
143 E1000_PRC1023 = 0x0406C, /* Packets RX (512-1023 bytes) - R/clr */ 145 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
144 E1000_PRC1522 = 0x04070, /* Packets RX (1024-1522 bytes) - R/clr */ 146 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
145 E1000_GPRC = 0x04074, /* Good Packets RX Count - R/clr */ 147 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
146 E1000_BPRC = 0x04078, /* Broadcast Packets RX Count - R/clr */ 148 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
147 E1000_MPRC = 0x0407C, /* Multicast Packets RX Count - R/clr */ 149 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
148 E1000_GPTC = 0x04080, /* Good Packets TX Count - R/clr */ 150 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
149 E1000_GORCL = 0x04088, /* Good Octets RX Count Low - R/clr */ 151 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
150 E1000_GORCH = 0x0408C, /* Good Octets RX Count High - R/clr */ 152 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
151 E1000_GOTCL = 0x04090, /* Good Octets TX Count Low - R/clr */ 153 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
152 E1000_GOTCH = 0x04094, /* Good Octets TX Count High - R/clr */ 154 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
153 E1000_RNBC = 0x040A0, /* RX No Buffers Count - R/clr */ 155 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
154 E1000_RUC = 0x040A4, /* RX Undersize Count - R/clr */ 156 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
155 E1000_RFC = 0x040A8, /* RX Fragment Count - R/clr */ 157 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
156 E1000_ROC = 0x040AC, /* RX Oversize Count - R/clr */ 158 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
157 E1000_RJC = 0x040B0, /* RX Jabber Count - R/clr */ 159 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
158 E1000_MGTPRC = 0x040B4, /* Management Packets RX Count - R/clr */ 160 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
159 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */ 161 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
160 E1000_MGTPTC = 0x040BC, /* Management Packets TX Count - R/clr */ 162 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
161 E1000_TORL = 0x040C0, /* Total Octets RX Low - R/clr */ 163 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
162 E1000_TORH = 0x040C4, /* Total Octets RX High - R/clr */ 164 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
163 E1000_TOTL = 0x040C8, /* Total Octets TX Low - R/clr */ 165 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
164 E1000_TOTH = 0x040CC, /* Total Octets TX High - R/clr */ 166 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
165 E1000_TPR = 0x040D0, /* Total Packets RX - R/clr */ 167 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
166 E1000_TPT = 0x040D4, /* Total Packets TX - R/clr */ 168 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
167 E1000_PTC64 = 0x040D8, /* Packets TX (64 bytes) - R/clr */ 169 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
168 E1000_PTC127 = 0x040DC, /* Packets TX (65-127 bytes) - R/clr */ 170 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
169 E1000_PTC255 = 0x040E0, /* Packets TX (128-255 bytes) - R/clr */ 171 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
170 E1000_PTC511 = 0x040E4, /* Packets TX (256-511 bytes) - R/clr */ 172 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
171 E1000_PTC1023 = 0x040E8, /* Packets TX (512-1023 bytes) - R/clr */ 173 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
172 E1000_PTC1522 = 0x040EC, /* Packets TX (1024-1522 Bytes) - R/clr */ 174 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
173 E1000_MPTC = 0x040F0, /* Multicast Packets TX Count - R/clr */ 175 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
174 E1000_BPTC = 0x040F4, /* Broadcast Packets TX Count - R/clr */ 176 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
175 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context TX - R/clr */ 177 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
176 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context TX Fail - R/clr */ 178 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
177 E1000_IAC = 0x04100, /* Interrupt Assertion Count */ 179 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
178 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */ 180 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
179 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */ 181 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
@@ -183,7 +185,7 @@ enum e1e_registers {
183 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */ 185 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
184 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */ 186 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
185 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */ 187 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
186 E1000_RXCSUM = 0x05000, /* RX Checksum Control - RW */ 188 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
187 E1000_RFCTL = 0x05008, /* Receive Filter Control */ 189 E1000_RFCTL = 0x05008, /* Receive Filter Control */
188 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */ 190 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
189 E1000_RA = 0x05400, /* Receive Address - RW Array */ 191 E1000_RA = 0x05400, /* Receive Address - RW Array */
@@ -250,8 +252,8 @@ enum e1e_registers {
250#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 252#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
251 253
252#define E1000_HICR_EN 0x01 /* Enable bit - RO */ 254#define E1000_HICR_EN 0x01 /* Enable bit - RO */
253#define E1000_HICR_C 0x02 /* Driver sets this bit when done 255/* Driver sets this bit when done to put command in RAM */
254 * to put command in RAM */ 256#define E1000_HICR_C 0x02
255#define E1000_HICR_FW_RESET_ENABLE 0x40 257#define E1000_HICR_FW_RESET_ENABLE 0x40
256#define E1000_HICR_FW_RESET 0x80 258#define E1000_HICR_FW_RESET 0x80
257 259
@@ -400,7 +402,7 @@ enum e1000_rev_polarity{
400 e1000_rev_polarity_undefined = 0xFF 402 e1000_rev_polarity_undefined = 0xFF
401}; 403};
402 404
403enum e1000_fc_mode { 405enum e1000_fc_type {
404 e1000_fc_none = 0, 406 e1000_fc_none = 0,
405 e1000_fc_rx_pause, 407 e1000_fc_rx_pause,
406 e1000_fc_tx_pause, 408 e1000_fc_tx_pause,
@@ -685,8 +687,7 @@ struct e1000_mac_operations {
685 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 687 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
686 s32 (*led_on)(struct e1000_hw *); 688 s32 (*led_on)(struct e1000_hw *);
687 s32 (*led_off)(struct e1000_hw *); 689 s32 (*led_off)(struct e1000_hw *);
688 void (*mc_addr_list_update)(struct e1000_hw *, u8 *, u32, u32, 690 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
689 u32);
690 s32 (*reset_hw)(struct e1000_hw *); 691 s32 (*reset_hw)(struct e1000_hw *);
691 s32 (*init_hw)(struct e1000_hw *); 692 s32 (*init_hw)(struct e1000_hw *);
692 s32 (*setup_link)(struct e1000_hw *); 693 s32 (*setup_link)(struct e1000_hw *);
@@ -728,16 +729,12 @@ struct e1000_mac_info {
728 u8 perm_addr[6]; 729 u8 perm_addr[6];
729 730
730 enum e1000_mac_type type; 731 enum e1000_mac_type type;
731 enum e1000_fc_mode fc;
732 enum e1000_fc_mode original_fc;
733 732
734 u32 collision_delta; 733 u32 collision_delta;
735 u32 ledctl_default; 734 u32 ledctl_default;
736 u32 ledctl_mode1; 735 u32 ledctl_mode1;
737 u32 ledctl_mode2; 736 u32 ledctl_mode2;
738 u32 max_frame_size;
739 u32 mc_filter_type; 737 u32 mc_filter_type;
740 u32 min_frame_size;
741 u32 tx_packet_delta; 738 u32 tx_packet_delta;
742 u32 txcw; 739 u32 txcw;
743 740
@@ -748,9 +745,6 @@ struct e1000_mac_info {
748 u16 ifs_step_size; 745 u16 ifs_step_size;
749 u16 mta_reg_count; 746 u16 mta_reg_count;
750 u16 rar_entry_count; 747 u16 rar_entry_count;
751 u16 fc_high_water;
752 u16 fc_low_water;
753 u16 fc_pause_time;
754 748
755 u8 forced_speed_duplex; 749 u8 forced_speed_duplex;
756 750
@@ -780,6 +774,8 @@ struct e1000_phy_info {
780 u32 reset_delay_us; /* in usec */ 774 u32 reset_delay_us; /* in usec */
781 u32 revision; 775 u32 revision;
782 776
777 enum e1000_media_type media_type;
778
783 u16 autoneg_advertised; 779 u16 autoneg_advertised;
784 u16 autoneg_mask; 780 u16 autoneg_mask;
785 u16 cable_length; 781 u16 cable_length;
@@ -792,7 +788,7 @@ struct e1000_phy_info {
792 bool is_mdix; 788 bool is_mdix;
793 bool polarity_correction; 789 bool polarity_correction;
794 bool speed_downgraded; 790 bool speed_downgraded;
795 bool wait_for_link; 791 bool autoneg_wait_to_complete;
796}; 792};
797 793
798struct e1000_nvm_info { 794struct e1000_nvm_info {
@@ -817,6 +813,16 @@ struct e1000_bus_info {
817 u16 func; 813 u16 func;
818}; 814};
819 815
816struct e1000_fc_info {
817 u32 high_water; /* Flow control high-water mark */
818 u32 low_water; /* Flow control low-water mark */
819 u16 pause_time; /* Flow control pause timer */
820 bool send_xon; /* Flow control send XON */
821 bool strict_ieee; /* Strict IEEE mode */
822 enum e1000_fc_type type; /* Type of flow control */
823 enum e1000_fc_type original_type;
824};
825
820struct e1000_dev_spec_82571 { 826struct e1000_dev_spec_82571 {
821 bool laa_is_present; 827 bool laa_is_present;
822 bool alt_mac_addr_is_present; 828 bool alt_mac_addr_is_present;
@@ -841,6 +847,7 @@ struct e1000_hw {
841 u8 __iomem *flash_address; 847 u8 __iomem *flash_address;
842 848
843 struct e1000_mac_info mac; 849 struct e1000_mac_info mac;
850 struct e1000_fc_info fc;
844 struct e1000_phy_info phy; 851 struct e1000_phy_info phy;
845 struct e1000_nvm_info nvm; 852 struct e1000_nvm_info nvm;
846 struct e1000_bus_info bus; 853 struct e1000_bus_info bus;
@@ -850,8 +857,6 @@ struct e1000_hw {
850 struct e1000_dev_spec_82571 e82571; 857 struct e1000_dev_spec_82571 e82571;
851 struct e1000_dev_spec_ich8lan ich8lan; 858 struct e1000_dev_spec_ich8lan ich8lan;
852 } dev_spec; 859 } dev_spec;
853
854 enum e1000_media_type media_type;
855}; 860};
856 861
857#ifdef DEBUG 862#ifdef DEBUG
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 01:48:25 -0500