diff options
Diffstat (limited to 'drivers/net/e1000e/defines.h')
-rw-r--r-- | drivers/net/e1000e/defines.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 1190167a8b3d..e301e26d6897 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | Intel PRO/1000 Linux driver | 3 | Intel PRO/1000 Linux driver |
4 | Copyright(c) 1999 - 2008 Intel Corporation. | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms and conditions of the GNU General Public License, | 7 | under the terms and conditions of the GNU General Public License, |
@@ -74,7 +74,7 @@ | |||
74 | #define E1000_WUS_BC E1000_WUFC_BC | 74 | #define E1000_WUS_BC E1000_WUFC_BC |
75 | 75 | ||
76 | /* Extended Device Control */ | 76 | /* Extended Device Control */ |
77 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ | 77 | #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ |
78 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ | 78 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ |
79 | #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ | 79 | #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ |
80 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ | 80 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
@@ -320,6 +320,8 @@ | |||
320 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ | 320 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ |
321 | 321 | ||
322 | /* Header split receive */ | 322 | /* Header split receive */ |
323 | #define E1000_RFCTL_NFSW_DIS 0x00000040 | ||
324 | #define E1000_RFCTL_NFSR_DIS 0x00000080 | ||
323 | #define E1000_RFCTL_ACK_DIS 0x00001000 | 325 | #define E1000_RFCTL_ACK_DIS 0x00001000 |
324 | #define E1000_RFCTL_EXTEN 0x00008000 | 326 | #define E1000_RFCTL_EXTEN 0x00008000 |
325 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 | 327 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 |
@@ -460,6 +462,8 @@ | |||
460 | */ | 462 | */ |
461 | #define E1000_RAR_ENTRIES 15 | 463 | #define E1000_RAR_ENTRIES 15 |
462 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ | 464 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ |
465 | #define E1000_RAL_MAC_ADDR_LEN 4 | ||
466 | #define E1000_RAH_MAC_ADDR_LEN 2 | ||
463 | 467 | ||
464 | /* Error Codes */ | 468 | /* Error Codes */ |
465 | #define E1000_ERR_NVM 1 | 469 | #define E1000_ERR_NVM 1 |