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path: root/drivers/net/davinci_emac.c
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Diffstat (limited to 'drivers/net/davinci_emac.c')
-rw-r--r--drivers/net/davinci_emac.c1379
1 files changed, 199 insertions, 1180 deletions
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 7fbd052ddb0a..dcc4a170b0f3 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -63,6 +63,8 @@
63#include <asm/irq.h> 63#include <asm/irq.h>
64#include <asm/page.h> 64#include <asm/page.h>
65 65
66#include "davinci_cpdma.h"
67
66static int debug_level; 68static int debug_level;
67module_param(debug_level, int, 0); 69module_param(debug_level, int, 0);
68MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); 70MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
@@ -92,14 +94,14 @@ MODULE_VERSION(EMAC_MODULE_VERSION);
92static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; 94static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
93 95
94/* Configuration items */ 96/* Configuration items */
95#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ 97#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
96#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ 98#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
97#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ 99#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
98#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ 100#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
99#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ 101#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
100#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ 102#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
101#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ 103#define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
102#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ 104#define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
103#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ 105#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
104#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ 106#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
105#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ 107#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
@@ -113,7 +115,7 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
113#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 115#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
114#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 116#define EMAC_DEF_TX_CH (0) /* Default 0th channel */
115#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 117#define EMAC_DEF_RX_CH (0) /* Default 0th channel */
116#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ 118#define EMAC_DEF_RX_NUM_DESC (128)
117#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 119#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
118#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 120#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
119#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ 121#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
@@ -125,7 +127,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
125/* EMAC register related defines */ 127/* EMAC register related defines */
126#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) 128#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
127#define EMAC_NUM_MULTICAST_BITS (64) 129#define EMAC_NUM_MULTICAST_BITS (64)
128#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
129#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) 130#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
130#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) 131#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
131#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) 132#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
@@ -212,24 +213,10 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
212#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ 213#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
213 214
214/* EMAC Peripheral Device Register Memory Layout structure */ 215/* EMAC Peripheral Device Register Memory Layout structure */
215#define EMAC_TXIDVER 0x0
216#define EMAC_TXCONTROL 0x4
217#define EMAC_TXTEARDOWN 0x8
218#define EMAC_RXIDVER 0x10
219#define EMAC_RXCONTROL 0x14
220#define EMAC_RXTEARDOWN 0x18
221#define EMAC_TXINTSTATRAW 0x80
222#define EMAC_TXINTSTATMASKED 0x84
223#define EMAC_TXINTMASKSET 0x88
224#define EMAC_TXINTMASKCLEAR 0x8C
225#define EMAC_MACINVECTOR 0x90 216#define EMAC_MACINVECTOR 0x90
226 217
227#define EMAC_DM646X_MACEOIVECTOR 0x94 218#define EMAC_DM646X_MACEOIVECTOR 0x94
228 219
229#define EMAC_RXINTSTATRAW 0xA0
230#define EMAC_RXINTSTATMASKED 0xA4
231#define EMAC_RXINTMASKSET 0xA8
232#define EMAC_RXINTMASKCLEAR 0xAC
233#define EMAC_MACINTSTATRAW 0xB0 220#define EMAC_MACINTSTATRAW 0xB0
234#define EMAC_MACINTSTATMASKED 0xB4 221#define EMAC_MACINTSTATMASKED 0xB4
235#define EMAC_MACINTMASKSET 0xB8 222#define EMAC_MACINTMASKSET 0xB8
@@ -256,12 +243,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
256#define EMAC_MACADDRHI 0x504 243#define EMAC_MACADDRHI 0x504
257#define EMAC_MACINDEX 0x508 244#define EMAC_MACINDEX 0x508
258 245
259/* EMAC HDP and Completion registors */
260#define EMAC_TXHDP(ch) (0x600 + (ch * 4))
261#define EMAC_RXHDP(ch) (0x620 + (ch * 4))
262#define EMAC_TXCP(ch) (0x640 + (ch * 4))
263#define EMAC_RXCP(ch) (0x660 + (ch * 4))
264
265/* EMAC statistics registers */ 246/* EMAC statistics registers */
266#define EMAC_RXGOODFRAMES 0x200 247#define EMAC_RXGOODFRAMES 0x200
267#define EMAC_RXBCASTFRAMES 0x204 248#define EMAC_RXBCASTFRAMES 0x204
@@ -303,25 +284,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
303#define EMAC_DM644X_INTMIN_INTVL 0x1 284#define EMAC_DM644X_INTMIN_INTVL 0x1
304#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) 285#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
305 286
306/* EMAC MDIO related */
307/* Mask & Control defines */
308#define MDIO_CONTROL_CLKDIV (0xFF)
309#define MDIO_CONTROL_ENABLE BIT(30)
310#define MDIO_USERACCESS_GO BIT(31)
311#define MDIO_USERACCESS_WRITE BIT(30)
312#define MDIO_USERACCESS_READ (0)
313#define MDIO_USERACCESS_REGADR (0x1F << 21)
314#define MDIO_USERACCESS_PHYADR (0x1F << 16)
315#define MDIO_USERACCESS_DATA (0xFFFF)
316#define MDIO_USERPHYSEL_LINKSEL BIT(7)
317#define MDIO_VER_MODID (0xFFFF << 16)
318#define MDIO_VER_REVMAJ (0xFF << 8)
319#define MDIO_VER_REVMIN (0xFF)
320
321#define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
322#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
323#define MDIO_CONTROL (0x04)
324
325/* EMAC DM646X control module registers */ 287/* EMAC DM646X control module registers */
326#define EMAC_DM646X_CMINTCTRL 0x0C 288#define EMAC_DM646X_CMINTCTRL 0x0C
327#define EMAC_DM646X_CMRXINTEN 0x14 289#define EMAC_DM646X_CMRXINTEN 0x14
@@ -345,120 +307,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
345/* EMAC Stats Clear Mask */ 307/* EMAC Stats Clear Mask */
346#define EMAC_STATS_CLR_MASK (0xFFFFFFFF) 308#define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
347 309
348/** net_buf_obj: EMAC network bufferdata structure
349 *
350 * EMAC network buffer data structure
351 */
352struct emac_netbufobj {
353 void *buf_token;
354 char *data_ptr;
355 int length;
356};
357
358/** net_pkt_obj: EMAC network packet data structure
359 *
360 * EMAC network packet data structure - supports buffer list (for future)
361 */
362struct emac_netpktobj {
363 void *pkt_token; /* data token may hold tx/rx chan id */
364 struct emac_netbufobj *buf_list; /* array of network buffer objects */
365 int num_bufs;
366 int pkt_length;
367};
368
369/** emac_tx_bd: EMAC TX Buffer descriptor data structure
370 *
371 * EMAC TX Buffer descriptor data structure
372 */
373struct emac_tx_bd {
374 int h_next;
375 int buff_ptr;
376 int off_b_len;
377 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
378 struct emac_tx_bd __iomem *next;
379 void *buf_token;
380};
381
382/** emac_txch: EMAC TX Channel data structure
383 *
384 * EMAC TX Channel data structure
385 */
386struct emac_txch {
387 /* Config related */
388 u32 num_bd;
389 u32 service_max;
390
391 /* CPPI specific */
392 u32 alloc_size;
393 void __iomem *bd_mem;
394 struct emac_tx_bd __iomem *bd_pool_head;
395 struct emac_tx_bd __iomem *active_queue_head;
396 struct emac_tx_bd __iomem *active_queue_tail;
397 struct emac_tx_bd __iomem *last_hw_bdprocessed;
398 u32 queue_active;
399 u32 teardown_pending;
400 u32 *tx_complete;
401
402 /** statistics */
403 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
404 u32 mis_queued_packets;
405 u32 queue_reinit;
406 u32 end_of_queue_add;
407 u32 out_of_tx_bd;
408 u32 no_active_pkts; /* IRQ when there were no packets to process */
409 u32 active_queue_count;
410};
411
412/** emac_rx_bd: EMAC RX Buffer descriptor data structure
413 *
414 * EMAC RX Buffer descriptor data structure
415 */
416struct emac_rx_bd {
417 int h_next;
418 int buff_ptr;
419 int off_b_len;
420 int mode;
421 struct emac_rx_bd __iomem *next;
422 void *data_ptr;
423 void *buf_token;
424};
425
426/** emac_rxch: EMAC RX Channel data structure
427 *
428 * EMAC RX Channel data structure
429 */
430struct emac_rxch {
431 /* configuration info */
432 u32 num_bd;
433 u32 service_max;
434 u32 buf_size;
435 char mac_addr[6];
436
437 /** CPPI specific */
438 u32 alloc_size;
439 void __iomem *bd_mem;
440 struct emac_rx_bd __iomem *bd_pool_head;
441 struct emac_rx_bd __iomem *active_queue_head;
442 struct emac_rx_bd __iomem *active_queue_tail;
443 u32 queue_active;
444 u32 teardown_pending;
445
446 /* packet and buffer objects */
447 struct emac_netpktobj pkt_queue;
448 struct emac_netbufobj buf_queue;
449
450 /** statistics */
451 u32 proc_count; /* number of times emac_rx_bdproc is called */
452 u32 processed_bd;
453 u32 recycled_bd;
454 u32 out_of_rx_bd;
455 u32 out_of_rx_buffers;
456 u32 queue_reinit;
457 u32 end_of_queue_add;
458 u32 end_of_queue;
459 u32 mis_queued_packets;
460};
461
462/* emac_priv: EMAC private data structure 310/* emac_priv: EMAC private data structure
463 * 311 *
464 * EMAC adapter private data structure 312 * EMAC adapter private data structure
@@ -469,17 +317,13 @@ struct emac_priv {
469 struct platform_device *pdev; 317 struct platform_device *pdev;
470 struct napi_struct napi; 318 struct napi_struct napi;
471 char mac_addr[6]; 319 char mac_addr[6];
472 spinlock_t tx_lock;
473 spinlock_t rx_lock;
474 void __iomem *remap_addr; 320 void __iomem *remap_addr;
475 u32 emac_base_phys; 321 u32 emac_base_phys;
476 void __iomem *emac_base; 322 void __iomem *emac_base;
477 void __iomem *ctrl_base; 323 void __iomem *ctrl_base;
478 void __iomem *emac_ctrl_ram; 324 struct cpdma_ctlr *dma;
479 u32 ctrl_ram_size; 325 struct cpdma_chan *txchan;
480 u32 hw_ram_addr; 326 struct cpdma_chan *rxchan;
481 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
482 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
483 u32 link; /* 1=link on, 0=link off */ 327 u32 link; /* 1=link on, 0=link off */
484 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ 328 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
485 u32 duplex; /* Link duplex: 0=Half, 1=Full */ 329 u32 duplex; /* Link duplex: 0=Half, 1=Full */
@@ -493,13 +337,7 @@ struct emac_priv {
493 u32 mac_hash2; 337 u32 mac_hash2;
494 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 338 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
495 u32 rx_addr_type; 339 u32 rx_addr_type;
496 /* periodic timer required for MDIO polling */ 340 const char *phy_id;
497 struct timer_list periodic_timer;
498 u32 periodic_ticks;
499 u32 timer_active;
500 u32 phy_mask;
501 /* mii_bus,phy members */
502 struct mii_bus *mii_bus;
503 struct phy_device *phydev; 341 struct phy_device *phydev;
504 spinlock_t lock; 342 spinlock_t lock;
505 /*platform specific members*/ 343 /*platform specific members*/
@@ -510,19 +348,6 @@ struct emac_priv {
510/* clock frequency for EMAC */ 348/* clock frequency for EMAC */
511static struct clk *emac_clk; 349static struct clk *emac_clk;
512static unsigned long emac_bus_frequency; 350static unsigned long emac_bus_frequency;
513static unsigned long mdio_max_freq;
514
515#define emac_virt_to_phys(addr, priv) \
516 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
517 + priv->hw_ram_addr)
518
519/* Cache macros - Packet buffers would be from skb pool which is cached */
520#define EMAC_VIRT_NOCACHE(addr) (addr)
521
522/* DM644x does not have BD's in cached memory - so no cache functions */
523#define BD_CACHE_INVALIDATE(addr, size)
524#define BD_CACHE_WRITEBACK(addr, size)
525#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
526 351
527/* EMAC TX Host Error description strings */ 352/* EMAC TX Host Error description strings */
528static char *emac_txhost_errcodes[16] = { 353static char *emac_txhost_errcodes[16] = {
@@ -548,9 +373,6 @@ static char *emac_rxhost_errcodes[16] = {
548#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) 373#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
549#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) 374#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
550 375
551#define emac_mdio_read(reg) ioread32(bus->priv + (reg))
552#define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
553
554/** 376/**
555 * emac_dump_regs: Dump important EMAC registers to debug terminal 377 * emac_dump_regs: Dump important EMAC registers to debug terminal
556 * @priv: The DaVinci EMAC private adapter structure 378 * @priv: The DaVinci EMAC private adapter structure
@@ -569,20 +391,6 @@ static void emac_dump_regs(struct emac_priv *priv)
569 emac_ctrl_read(EMAC_CTRL_EWCTL), 391 emac_ctrl_read(EMAC_CTRL_EWCTL),
570 emac_ctrl_read(EMAC_CTRL_EWINTTCNT)); 392 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
571 } 393 }
572 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
573 emac_read(EMAC_TXIDVER),
574 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
575 emac_read(EMAC_RXIDVER),
576 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
577 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
578 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
579 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
580 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
581 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
582 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
583 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
584 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
585 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
586 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n", 394 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
587 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL)); 395 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
588 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\ 396 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
@@ -591,8 +399,6 @@ static void emac_dump_regs(struct emac_priv *priv)
591 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\ 399 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
592 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL), 400 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
593 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG)); 401 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
594 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
595 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
596 dev_info(emac_dev, "EMAC Statistics\n"); 402 dev_info(emac_dev, "EMAC Statistics\n");
597 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n", 403 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
598 emac_read(EMAC_RXGOODFRAMES)); 404 emac_read(EMAC_RXGOODFRAMES));
@@ -654,11 +460,10 @@ static void emac_dump_regs(struct emac_priv *priv)
654 emac_read(EMAC_RXMOFOVERRUNS)); 460 emac_read(EMAC_RXMOFOVERRUNS));
655 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n", 461 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
656 emac_read(EMAC_RXDMAOVERRUNS)); 462 emac_read(EMAC_RXDMAOVERRUNS));
463
464 cpdma_ctlr_dump(priv->dma);
657} 465}
658 466
659/*************************************************************************
660 * EMAC MDIO/Phy Functionality
661 *************************************************************************/
662/** 467/**
663 * emac_get_drvinfo: Get EMAC driver information 468 * emac_get_drvinfo: Get EMAC driver information
664 * @ndev: The DaVinci EMAC network adapter 469 * @ndev: The DaVinci EMAC network adapter
@@ -686,7 +491,7 @@ static int emac_get_settings(struct net_device *ndev,
686 struct ethtool_cmd *ecmd) 491 struct ethtool_cmd *ecmd)
687{ 492{
688 struct emac_priv *priv = netdev_priv(ndev); 493 struct emac_priv *priv = netdev_priv(ndev);
689 if (priv->phy_mask) 494 if (priv->phydev)
690 return phy_ethtool_gset(priv->phydev, ecmd); 495 return phy_ethtool_gset(priv->phydev, ecmd);
691 else 496 else
692 return -EOPNOTSUPP; 497 return -EOPNOTSUPP;
@@ -704,7 +509,7 @@ static int emac_get_settings(struct net_device *ndev,
704static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 509static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
705{ 510{
706 struct emac_priv *priv = netdev_priv(ndev); 511 struct emac_priv *priv = netdev_priv(ndev);
707 if (priv->phy_mask) 512 if (priv->phydev)
708 return phy_ethtool_sset(priv->phydev, ecmd); 513 return phy_ethtool_sset(priv->phydev, ecmd);
709 else 514 else
710 return -EOPNOTSUPP; 515 return -EOPNOTSUPP;
@@ -841,7 +646,7 @@ static void emac_update_phystatus(struct emac_priv *priv)
841 mac_control = emac_read(EMAC_MACCONTROL); 646 mac_control = emac_read(EMAC_MACCONTROL);
842 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? 647 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
843 DUPLEX_FULL : DUPLEX_HALF; 648 DUPLEX_FULL : DUPLEX_HALF;
844 if (priv->phy_mask) 649 if (priv->phydev)
845 new_duplex = priv->phydev->duplex; 650 new_duplex = priv->phydev->duplex;
846 else 651 else
847 new_duplex = DUPLEX_FULL; 652 new_duplex = DUPLEX_FULL;
@@ -1184,371 +989,68 @@ static irqreturn_t emac_irq(int irq, void *dev_id)
1184 return IRQ_HANDLED; 989 return IRQ_HANDLED;
1185} 990}
1186 991
1187/** EMAC on-chip buffer descriptor memory 992static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
1188 *
1189 * WARNING: Please note that the on chip memory is used for both TX and RX
1190 * buffer descriptor queues and is equally divided between TX and RX desc's
1191 * If the number of TX or RX descriptors change this memory pointers need
1192 * to be adjusted. If external memory is allocated then these pointers can
1193 * pointer to the memory
1194 *
1195 */
1196#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1197#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1198 (((priv)->ctrl_ram_size) >> 1))
1199
1200/**
1201 * emac_init_txch: TX channel initialization
1202 * @priv: The DaVinci EMAC private adapter structure
1203 * @ch: RX channel number
1204 *
1205 * Called during device init to setup a TX channel (allocate buffer desc
1206 * create free pool and keep ready for transmission
1207 *
1208 * Returns success(0) or mem alloc failures error code
1209 */
1210static int emac_init_txch(struct emac_priv *priv, u32 ch)
1211{
1212 struct device *emac_dev = &priv->ndev->dev;
1213 u32 cnt, bd_size;
1214 void __iomem *mem;
1215 struct emac_tx_bd __iomem *curr_bd;
1216 struct emac_txch *txch = NULL;
1217
1218 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1219 if (NULL == txch) {
1220 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1221 return -ENOMEM;
1222 }
1223 priv->txch[ch] = txch;
1224 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1225 txch->active_queue_head = NULL;
1226 txch->active_queue_tail = NULL;
1227 txch->queue_active = 0;
1228 txch->teardown_pending = 0;
1229
1230 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1231 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1232 GFP_KERNEL);
1233 if (NULL == txch->tx_complete) {
1234 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1235 kfree(txch);
1236 return -ENOMEM;
1237 }
1238
1239 /* allocate buffer descriptor pool align every BD on four word
1240 * boundry for future requirements */
1241 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1242 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1243 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1244
1245 /* alloc TX BD memory */
1246 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1247 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1248
1249 /* initialize the BD linked list */
1250 mem = (void __force __iomem *)
1251 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1252 txch->bd_pool_head = NULL;
1253 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1254 curr_bd = mem + (cnt * bd_size);
1255 curr_bd->next = txch->bd_pool_head;
1256 txch->bd_pool_head = curr_bd;
1257 }
1258
1259 /* reset statistics counters */
1260 txch->out_of_tx_bd = 0;
1261 txch->no_active_pkts = 0;
1262 txch->active_queue_count = 0;
1263
1264 return 0;
1265}
1266
1267/**
1268 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1269 * @priv: The DaVinci EMAC private adapter structure
1270 * @ch: TX channel number
1271 *
1272 * Called to clean up TX channel resources
1273 *
1274 */
1275static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1276{ 993{
1277 struct emac_txch *txch = priv->txch[ch]; 994 struct sk_buff *skb = dev_alloc_skb(priv->rx_buf_size);
1278 995 if (WARN_ON(!skb))
1279 if (txch) { 996 return NULL;
1280 if (txch->bd_mem) 997 skb->dev = priv->ndev;
1281 txch->bd_mem = NULL; 998 skb_reserve(skb, NET_IP_ALIGN);
1282 kfree(txch->tx_complete); 999 return skb;
1283 kfree(txch);
1284 priv->txch[ch] = NULL;
1285 }
1286} 1000}
1287 1001
1288/** 1002static void emac_rx_handler(void *token, int len, int status)
1289 * emac_net_tx_complete: TX packet completion function
1290 * @priv: The DaVinci EMAC private adapter structure
1291 * @net_data_tokens: packet token - skb pointer
1292 * @num_tokens: number of skb's to free
1293 * @ch: TX channel number
1294 *
1295 * Frees the skb once packet is transmitted
1296 *
1297 */
1298static int emac_net_tx_complete(struct emac_priv *priv,
1299 void **net_data_tokens,
1300 int num_tokens, u32 ch)
1301{ 1003{
1302 struct net_device *ndev = priv->ndev; 1004 struct sk_buff *skb = token;
1303 u32 cnt; 1005 struct net_device *ndev = skb->dev;
1304 1006 struct emac_priv *priv = netdev_priv(ndev);
1305 if (unlikely(num_tokens && netif_queue_stopped(ndev))) 1007 struct device *emac_dev = &ndev->dev;
1306 netif_start_queue(ndev); 1008 int ret;
1307 for (cnt = 0; cnt < num_tokens; cnt++) { 1009
1308 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt]; 1010 /* free and bail if we are shutting down */
1309 if (skb == NULL) 1011 if (unlikely(!netif_running(ndev) || !netif_carrier_ok(ndev))) {
1310 continue;
1311 ndev->stats.tx_packets++;
1312 ndev->stats.tx_bytes += skb->len;
1313 dev_kfree_skb_any(skb); 1012 dev_kfree_skb_any(skb);
1013 return;
1314 } 1014 }
1315 return 0;
1316}
1317 1015
1318/** 1016 /* recycle on receive error */
1319 * emac_txch_teardown: TX channel teardown 1017 if (status < 0) {
1320 * @priv: The DaVinci EMAC private adapter structure 1018 ndev->stats.rx_errors++;
1321 * @ch: TX channel number 1019 goto recycle;
1322 *
1323 * Called to teardown TX channel
1324 *
1325 */
1326static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1327{
1328 struct device *emac_dev = &priv->ndev->dev;
1329 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1330 struct emac_txch *txch = priv->txch[ch];
1331 struct emac_tx_bd __iomem *curr_bd;
1332
1333 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1334 EMAC_TEARDOWN_VALUE) {
1335 /* wait till tx teardown complete */
1336 cpu_relax(); /* TODO: check if this helps ... */
1337 --teardown_cnt;
1338 if (0 == teardown_cnt) {
1339 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1340 break;
1341 }
1342 }
1343 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1344
1345 /* process sent packets and return skb's to upper layer */
1346 if (1 == txch->queue_active) {
1347 curr_bd = txch->active_queue_head;
1348 while (curr_bd != NULL) {
1349 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1350 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1351 DMA_TO_DEVICE);
1352
1353 emac_net_tx_complete(priv, (void __force *)
1354 &curr_bd->buf_token, 1, ch);
1355 if (curr_bd != txch->active_queue_tail)
1356 curr_bd = curr_bd->next;
1357 else
1358 break;
1359 }
1360 txch->bd_pool_head = txch->active_queue_head;
1361 txch->active_queue_head =
1362 txch->active_queue_tail = NULL;
1363 }
1364}
1365
1366/**
1367 * emac_stop_txch: Stop TX channel operation
1368 * @priv: The DaVinci EMAC private adapter structure
1369 * @ch: TX channel number
1370 *
1371 * Called to stop TX channel operation
1372 *
1373 */
1374static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1375{
1376 struct emac_txch *txch = priv->txch[ch];
1377
1378 if (txch) {
1379 txch->teardown_pending = 1;
1380 emac_write(EMAC_TXTEARDOWN, 0);
1381 emac_txch_teardown(priv, ch);
1382 txch->teardown_pending = 0;
1383 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1384 } 1020 }
1385}
1386 1021
1387/** 1022 /* feed received packet up the stack */
1388 * emac_tx_bdproc: TX buffer descriptor (packet) processing 1023 skb_put(skb, len);
1389 * @priv: The DaVinci EMAC private adapter structure 1024 skb->protocol = eth_type_trans(skb, ndev);
1390 * @ch: TX channel number to process buffer descriptors for 1025 netif_receive_skb(skb);
1391 * @budget: number of packets allowed to process 1026 ndev->stats.rx_bytes += len;
1392 * @pending: indication to caller that packets are pending to process 1027 ndev->stats.rx_packets++;
1393 *
1394 * Processes TX buffer descriptors after packets are transmitted - checks
1395 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1396 * the SKB buffer. Only "budget" number of packets are processed and
1397 * indication of pending packets provided to the caller
1398 *
1399 * Returns number of packets processed
1400 */
1401static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1402{
1403 struct device *emac_dev = &priv->ndev->dev;
1404 unsigned long flags;
1405 u32 frame_status;
1406 u32 pkts_processed = 0;
1407 u32 tx_complete_cnt = 0;
1408 struct emac_tx_bd __iomem *curr_bd;
1409 struct emac_txch *txch = priv->txch[ch];
1410 u32 *tx_complete_ptr = txch->tx_complete;
1411
1412 if (unlikely(1 == txch->teardown_pending)) {
1413 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1414 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1415 "teardown pending\n");
1416 }
1417 return 0; /* dont handle any pkt completions */
1418 }
1419 1028
1420 ++txch->proc_count; 1029 /* alloc a new packet for receive */
1421 spin_lock_irqsave(&priv->tx_lock, flags); 1030 skb = emac_rx_alloc(priv);
1422 curr_bd = txch->active_queue_head; 1031 if (!skb) {
1423 if (NULL == curr_bd) { 1032 if (netif_msg_rx_err(priv) && net_ratelimit())
1424 emac_write(EMAC_TXCP(ch), 1033 dev_err(emac_dev, "failed rx buffer alloc\n");
1425 emac_virt_to_phys(txch->last_hw_bdprocessed, priv)); 1034 return;
1426 txch->no_active_pkts++;
1427 spin_unlock_irqrestore(&priv->tx_lock, flags);
1428 return 0;
1429 } 1035 }
1430 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1431 frame_status = curr_bd->mode;
1432 while ((curr_bd) &&
1433 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1434 (pkts_processed < budget)) {
1435 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1436 txch->active_queue_head = curr_bd->next;
1437 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1438 if (curr_bd->next) { /* misqueued packet */
1439 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1440 ++txch->mis_queued_packets;
1441 } else {
1442 txch->queue_active = 0; /* end of queue */
1443 }
1444 }
1445
1446 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1447 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1448 DMA_TO_DEVICE);
1449
1450 *tx_complete_ptr = (u32) curr_bd->buf_token;
1451 ++tx_complete_ptr;
1452 ++tx_complete_cnt;
1453 curr_bd->next = txch->bd_pool_head;
1454 txch->bd_pool_head = curr_bd;
1455 --txch->active_queue_count;
1456 pkts_processed++;
1457 txch->last_hw_bdprocessed = curr_bd;
1458 curr_bd = txch->active_queue_head;
1459 if (curr_bd) {
1460 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1461 frame_status = curr_bd->mode;
1462 }
1463 } /* end of pkt processing loop */
1464 1036
1465 emac_net_tx_complete(priv, 1037recycle:
1466 (void *)&txch->tx_complete[0], 1038 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1467 tx_complete_cnt, ch); 1039 skb_tailroom(skb), GFP_KERNEL);
1468 spin_unlock_irqrestore(&priv->tx_lock, flags); 1040 if (WARN_ON(ret < 0))
1469 return pkts_processed; 1041 dev_kfree_skb_any(skb);
1470} 1042}
1471 1043
1472#define EMAC_ERR_TX_OUT_OF_BD -1 1044static void emac_tx_handler(void *token, int len, int status)
1473
1474/**
1475 * emac_send: EMAC Transmit function (internal)
1476 * @priv: The DaVinci EMAC private adapter structure
1477 * @pkt: packet pointer (contains skb ptr)
1478 * @ch: TX channel number
1479 *
1480 * Called by the transmit function to queue the packet in EMAC hardware queue
1481 *
1482 * Returns success(0) or error code (typically out of desc's)
1483 */
1484static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1485{ 1045{
1486 unsigned long flags; 1046 struct sk_buff *skb = token;
1487 struct emac_tx_bd __iomem *curr_bd; 1047 struct net_device *ndev = skb->dev;
1488 struct emac_txch *txch;
1489 struct emac_netbufobj *buf_list;
1490
1491 txch = priv->txch[ch];
1492 buf_list = pkt->buf_list; /* get handle to the buffer array */
1493 1048
1494 /* check packet size and pad if short */ 1049 if (unlikely(netif_queue_stopped(ndev)))
1495 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { 1050 netif_start_queue(ndev);
1496 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); 1051 ndev->stats.tx_packets++;
1497 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; 1052 ndev->stats.tx_bytes += len;
1498 } 1053 dev_kfree_skb_any(skb);
1499
1500 spin_lock_irqsave(&priv->tx_lock, flags);
1501 curr_bd = txch->bd_pool_head;
1502 if (curr_bd == NULL) {
1503 txch->out_of_tx_bd++;
1504 spin_unlock_irqrestore(&priv->tx_lock, flags);
1505 return EMAC_ERR_TX_OUT_OF_BD;
1506 }
1507
1508 txch->bd_pool_head = curr_bd->next;
1509 curr_bd->buf_token = buf_list->buf_token;
1510 curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buf_list->data_ptr,
1511 buf_list->length, DMA_TO_DEVICE);
1512 curr_bd->off_b_len = buf_list->length;
1513 curr_bd->h_next = 0;
1514 curr_bd->next = NULL;
1515 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1516 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1517
1518 /* flush the packet from cache if write back cache is present */
1519 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1520
1521 /* send the packet */
1522 if (txch->active_queue_head == NULL) {
1523 txch->active_queue_head = curr_bd;
1524 txch->active_queue_tail = curr_bd;
1525 if (1 != txch->queue_active) {
1526 emac_write(EMAC_TXHDP(ch),
1527 emac_virt_to_phys(curr_bd, priv));
1528 txch->queue_active = 1;
1529 }
1530 ++txch->queue_reinit;
1531 } else {
1532 register struct emac_tx_bd __iomem *tail_bd;
1533 register u32 frame_status;
1534
1535 tail_bd = txch->active_queue_tail;
1536 tail_bd->next = curr_bd;
1537 txch->active_queue_tail = curr_bd;
1538 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1539 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1540 frame_status = tail_bd->mode;
1541 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1542 emac_write(EMAC_TXHDP(ch),
1543 emac_virt_to_phys(curr_bd, priv));
1544 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1545 tail_bd->mode = frame_status;
1546 ++txch->end_of_queue_add;
1547 }
1548 }
1549 txch->active_queue_count++;
1550 spin_unlock_irqrestore(&priv->tx_lock, flags);
1551 return 0;
1552} 1054}
1553 1055
1554/** 1056/**
@@ -1565,42 +1067,36 @@ static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1565{ 1067{
1566 struct device *emac_dev = &ndev->dev; 1068 struct device *emac_dev = &ndev->dev;
1567 int ret_code; 1069 int ret_code;
1568 struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1569 struct emac_netpktobj tx_packet; /* packet object */
1570 struct emac_priv *priv = netdev_priv(ndev); 1070 struct emac_priv *priv = netdev_priv(ndev);
1571 1071
1572 /* If no link, return */ 1072 /* If no link, return */
1573 if (unlikely(!priv->link)) { 1073 if (unlikely(!priv->link)) {
1574 if (netif_msg_tx_err(priv) && net_ratelimit()) 1074 if (netif_msg_tx_err(priv) && net_ratelimit())
1575 dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); 1075 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1576 return NETDEV_TX_BUSY; 1076 goto fail_tx;
1577 } 1077 }
1578 1078
1579 /* Build the buffer and packet objects - Since only single fragment is 1079 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1580 * supported, need not set length and token in both packet & object. 1080 if (unlikely(ret_code < 0)) {
1581 * Doing so for completeness sake & to show that this needs to be done 1081 if (netif_msg_tx_err(priv) && net_ratelimit())
1582 * in multifragment case 1082 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1583 */ 1083 goto fail_tx;
1584 tx_packet.buf_list = &tx_buf; 1084 }
1585 tx_packet.num_bufs = 1; /* only single fragment supported */ 1085
1586 tx_packet.pkt_length = skb->len; 1086 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1587 tx_packet.pkt_token = (void *)skb; 1087 GFP_KERNEL);
1588 tx_buf.length = skb->len;
1589 tx_buf.buf_token = (void *)skb;
1590 tx_buf.data_ptr = skb->data;
1591 ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1592 if (unlikely(ret_code != 0)) { 1088 if (unlikely(ret_code != 0)) {
1593 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { 1089 if (netif_msg_tx_err(priv) && net_ratelimit())
1594 if (netif_msg_tx_err(priv) && net_ratelimit()) 1090 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1595 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\ 1091 goto fail_tx;
1596 " err. Out of TX BD's");
1597 netif_stop_queue(priv->ndev);
1598 }
1599 ndev->stats.tx_dropped++;
1600 return NETDEV_TX_BUSY;
1601 } 1092 }
1602 1093
1603 return NETDEV_TX_OK; 1094 return NETDEV_TX_OK;
1095
1096fail_tx:
1097 ndev->stats.tx_dropped++;
1098 netif_stop_queue(ndev);
1099 return NETDEV_TX_BUSY;
1604} 1100}
1605 1101
1606/** 1102/**
@@ -1621,218 +1117,16 @@ static void emac_dev_tx_timeout(struct net_device *ndev)
1621 if (netif_msg_tx_err(priv)) 1117 if (netif_msg_tx_err(priv))
1622 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); 1118 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1623 1119
1120 emac_dump_regs(priv);
1121
1624 ndev->stats.tx_errors++; 1122 ndev->stats.tx_errors++;
1625 emac_int_disable(priv); 1123 emac_int_disable(priv);
1626 emac_stop_txch(priv, EMAC_DEF_TX_CH); 1124 cpdma_chan_stop(priv->txchan);
1627 emac_cleanup_txch(priv, EMAC_DEF_TX_CH); 1125 cpdma_chan_start(priv->txchan);
1628 emac_init_txch(priv, EMAC_DEF_TX_CH);
1629 emac_write(EMAC_TXHDP(0), 0);
1630 emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1631 emac_int_enable(priv); 1126 emac_int_enable(priv);
1632} 1127}
1633 1128
1634/** 1129/**
1635 * emac_net_alloc_rx_buf: Allocate a skb for RX
1636 * @priv: The DaVinci EMAC private adapter structure
1637 * @buf_size: size of SKB data buffer to allocate
1638 * @data_token: data token returned (skb handle for storing in buffer desc)
1639 * @ch: RX channel number
1640 *
1641 * Called during RX channel setup - allocates skb buffer of required size
1642 * and provides the skb handle and allocated buffer data pointer to caller
1643 *
1644 * Returns skb data pointer or 0 on failure to alloc skb
1645 */
1646static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1647 void **data_token, u32 ch)
1648{
1649 struct net_device *ndev = priv->ndev;
1650 struct device *emac_dev = &ndev->dev;
1651 struct sk_buff *p_skb;
1652
1653 p_skb = dev_alloc_skb(buf_size);
1654 if (unlikely(NULL == p_skb)) {
1655 if (netif_msg_rx_err(priv) && net_ratelimit())
1656 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1657 return NULL;
1658 }
1659
1660 /* set device pointer in skb and reserve space for extra bytes */
1661 p_skb->dev = ndev;
1662 skb_reserve(p_skb, NET_IP_ALIGN);
1663 *data_token = (void *) p_skb;
1664 return p_skb->data;
1665}
1666
1667/**
1668 * emac_init_rxch: RX channel initialization
1669 * @priv: The DaVinci EMAC private adapter structure
1670 * @ch: RX channel number
1671 * @param: mac address for RX channel
1672 *
1673 * Called during device init to setup a RX channel (allocate buffers and
1674 * buffer descriptors, create queue and keep ready for reception
1675 *
1676 * Returns success(0) or mem alloc failures error code
1677 */
1678static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1679{
1680 struct device *emac_dev = &priv->ndev->dev;
1681 u32 cnt, bd_size;
1682 void __iomem *mem;
1683 struct emac_rx_bd __iomem *curr_bd;
1684 struct emac_rxch *rxch = NULL;
1685
1686 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1687 if (NULL == rxch) {
1688 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1689 return -ENOMEM;
1690 }
1691 priv->rxch[ch] = rxch;
1692 rxch->buf_size = priv->rx_buf_size;
1693 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1694 rxch->queue_active = 0;
1695 rxch->teardown_pending = 0;
1696
1697 /* save mac address */
1698 for (cnt = 0; cnt < 6; cnt++)
1699 rxch->mac_addr[cnt] = param[cnt];
1700
1701 /* allocate buffer descriptor pool align every BD on four word
1702 * boundry for future requirements */
1703 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1704 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1705 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1706 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1707 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1708 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1709
1710 /* allocate RX buffer and initialize the BD linked list */
1711 mem = (void __force __iomem *)
1712 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1713 rxch->active_queue_head = NULL;
1714 rxch->active_queue_tail = mem;
1715 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1716 curr_bd = mem + (cnt * bd_size);
1717 /* for future use the last parameter contains the BD ptr */
1718 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1719 rxch->buf_size,
1720 (void __force **)&curr_bd->buf_token,
1721 EMAC_DEF_RX_CH);
1722 if (curr_bd->data_ptr == NULL) {
1723 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1724 "failed for ch %d\n", ch);
1725 kfree(rxch);
1726 return -ENOMEM;
1727 }
1728
1729 /* populate the hardware descriptor */
1730 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1731 priv);
1732 curr_bd->buff_ptr = dma_map_single(emac_dev, curr_bd->data_ptr,
1733 rxch->buf_size, DMA_FROM_DEVICE);
1734 curr_bd->off_b_len = rxch->buf_size;
1735 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1736
1737 /* write back to hardware memory */
1738 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1739 EMAC_BD_LENGTH_FOR_CACHE);
1740 curr_bd->next = rxch->active_queue_head;
1741 rxch->active_queue_head = curr_bd;
1742 }
1743
1744 /* At this point rxCppi->activeQueueHead points to the first
1745 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1746 points to the last RX BD
1747 */
1748 return 0;
1749}
1750
1751/**
1752 * emac_rxch_teardown: RX channel teardown
1753 * @priv: The DaVinci EMAC private adapter structure
1754 * @ch: RX channel number
1755 *
1756 * Called during device stop to teardown RX channel
1757 *
1758 */
1759static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1760{
1761 struct device *emac_dev = &priv->ndev->dev;
1762 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1763
1764 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1765 EMAC_TEARDOWN_VALUE) {
1766 /* wait till tx teardown complete */
1767 cpu_relax(); /* TODO: check if this helps ... */
1768 --teardown_cnt;
1769 if (0 == teardown_cnt) {
1770 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1771 break;
1772 }
1773 }
1774 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1775}
1776
1777/**
1778 * emac_stop_rxch: Stop RX channel operation
1779 * @priv: The DaVinci EMAC private adapter structure
1780 * @ch: RX channel number
1781 *
1782 * Called during device stop to stop RX channel operation
1783 *
1784 */
1785static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1786{
1787 struct emac_rxch *rxch = priv->rxch[ch];
1788
1789 if (rxch) {
1790 rxch->teardown_pending = 1;
1791 emac_write(EMAC_RXTEARDOWN, ch);
1792 /* wait for teardown complete */
1793 emac_rxch_teardown(priv, ch);
1794 rxch->teardown_pending = 0;
1795 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1796 }
1797}
1798
1799/**
1800 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1801 * @priv: The DaVinci EMAC private adapter structure
1802 * @ch: RX channel number
1803 *
1804 * Called during device stop to clean up RX channel resources
1805 *
1806 */
1807static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1808{
1809 struct emac_rxch *rxch = priv->rxch[ch];
1810 struct emac_rx_bd __iomem *curr_bd;
1811
1812 if (rxch) {
1813 /* free the receive buffers previously allocated */
1814 curr_bd = rxch->active_queue_head;
1815 while (curr_bd) {
1816 if (curr_bd->buf_token) {
1817 dma_unmap_single(&priv->ndev->dev,
1818 curr_bd->buff_ptr,
1819 curr_bd->off_b_len
1820 & EMAC_RX_BD_BUF_SIZE,
1821 DMA_FROM_DEVICE);
1822
1823 dev_kfree_skb_any((struct sk_buff *)\
1824 curr_bd->buf_token);
1825 }
1826 curr_bd = curr_bd->next;
1827 }
1828 if (rxch->bd_mem)
1829 rxch->bd_mem = NULL;
1830 kfree(rxch);
1831 priv->rxch[ch] = NULL;
1832 }
1833}
1834
1835/**
1836 * emac_set_type0addr: Set EMAC Type0 mac address 1130 * emac_set_type0addr: Set EMAC Type0 mac address
1837 * @priv: The DaVinci EMAC private adapter structure 1131 * @priv: The DaVinci EMAC private adapter structure
1838 * @ch: RX channel number 1132 * @ch: RX channel number
@@ -1948,7 +1242,6 @@ static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1948static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) 1242static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1949{ 1243{
1950 struct emac_priv *priv = netdev_priv(ndev); 1244 struct emac_priv *priv = netdev_priv(ndev);
1951 struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1952 struct device *emac_dev = &priv->ndev->dev; 1245 struct device *emac_dev = &priv->ndev->dev;
1953 struct sockaddr *sa = addr; 1246 struct sockaddr *sa = addr;
1954 1247
@@ -1959,11 +1252,10 @@ static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1959 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); 1252 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1960 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len); 1253 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1961 1254
1962 /* If the interface is down - rxch is NULL. */
1963 /* MAC address is configured only after the interface is enabled. */ 1255 /* MAC address is configured only after the interface is enabled. */
1964 if (netif_running(ndev)) { 1256 if (netif_running(ndev)) {
1965 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len); 1257 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1966 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr); 1258 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1967 } 1259 }
1968 1260
1969 if (netif_msg_drv(priv)) 1261 if (netif_msg_drv(priv))
@@ -1974,194 +1266,6 @@ static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1974} 1266}
1975 1267
1976/** 1268/**
1977 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1978 * @priv: The DaVinci EMAC private adapter structure
1979 * @ch: RX channel number to process buffer descriptors for
1980 * @curr_bd: current buffer descriptor
1981 * @buffer: buffer pointer for descriptor
1982 * @buf_token: buffer token (stores skb information)
1983 *
1984 * Prepares the recycled buffer descriptor and addes it to hardware
1985 * receive queue - if queue empty this descriptor becomes the head
1986 * else addes the descriptor to end of queue
1987 *
1988 */
1989static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1990 struct emac_rx_bd __iomem *curr_bd,
1991 char *buffer, void *buf_token)
1992{
1993 struct emac_rxch *rxch = priv->rxch[ch];
1994
1995 /* populate the hardware descriptor */
1996 curr_bd->h_next = 0;
1997 curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buffer,
1998 rxch->buf_size, DMA_FROM_DEVICE);
1999 curr_bd->off_b_len = rxch->buf_size;
2000 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
2001 curr_bd->next = NULL;
2002 curr_bd->data_ptr = buffer;
2003 curr_bd->buf_token = buf_token;
2004
2005 /* write back */
2006 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2007 if (rxch->active_queue_head == NULL) {
2008 rxch->active_queue_head = curr_bd;
2009 rxch->active_queue_tail = curr_bd;
2010 if (0 != rxch->queue_active) {
2011 emac_write(EMAC_RXHDP(ch),
2012 emac_virt_to_phys(rxch->active_queue_head, priv));
2013 rxch->queue_active = 1;
2014 }
2015 } else {
2016 struct emac_rx_bd __iomem *tail_bd;
2017 u32 frame_status;
2018
2019 tail_bd = rxch->active_queue_tail;
2020 rxch->active_queue_tail = curr_bd;
2021 tail_bd->next = curr_bd;
2022 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
2023 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
2024 frame_status = tail_bd->mode;
2025 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2026 emac_write(EMAC_RXHDP(ch),
2027 emac_virt_to_phys(curr_bd, priv));
2028 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
2029 tail_bd->mode = frame_status;
2030 ++rxch->end_of_queue_add;
2031 }
2032 }
2033 ++rxch->recycled_bd;
2034}
2035
2036/**
2037 * emac_net_rx_cb: Prepares packet and sends to upper layer
2038 * @priv: The DaVinci EMAC private adapter structure
2039 * @net_pkt_list: Network packet list (received packets)
2040 *
2041 * Invalidates packet buffer memory and sends the received packet to upper
2042 * layer
2043 *
2044 * Returns success or appropriate error code (none as of now)
2045 */
2046static int emac_net_rx_cb(struct emac_priv *priv,
2047 struct emac_netpktobj *net_pkt_list)
2048{
2049 struct net_device *ndev = priv->ndev;
2050 struct sk_buff *p_skb = net_pkt_list->pkt_token;
2051 /* set length of packet */
2052 skb_put(p_skb, net_pkt_list->pkt_length);
2053 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
2054 netif_receive_skb(p_skb);
2055 ndev->stats.rx_bytes += net_pkt_list->pkt_length;
2056 ndev->stats.rx_packets++;
2057 return 0;
2058}
2059
2060/**
2061 * emac_rx_bdproc: RX buffer descriptor (packet) processing
2062 * @priv: The DaVinci EMAC private adapter structure
2063 * @ch: RX channel number to process buffer descriptors for
2064 * @budget: number of packets allowed to process
2065 * @pending: indication to caller that packets are pending to process
2066 *
2067 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
2068 * descriptor, sends the receive packet to upper layer, allocates a new SKB
2069 * and recycles the buffer descriptor (requeues it in hardware RX queue).
2070 * Only "budget" number of packets are processed and indication of pending
2071 * packets provided to the caller.
2072 *
2073 * Returns number of packets processed (and indication of pending packets)
2074 */
2075static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
2076{
2077 unsigned long flags;
2078 u32 frame_status;
2079 u32 pkts_processed = 0;
2080 char *new_buffer;
2081 struct emac_rx_bd __iomem *curr_bd;
2082 struct emac_rx_bd __iomem *last_bd;
2083 struct emac_netpktobj *curr_pkt, pkt_obj;
2084 struct emac_netbufobj buf_obj;
2085 struct emac_netbufobj *rx_buf_obj;
2086 void *new_buf_token;
2087 struct emac_rxch *rxch = priv->rxch[ch];
2088
2089 if (unlikely(1 == rxch->teardown_pending))
2090 return 0;
2091 ++rxch->proc_count;
2092 spin_lock_irqsave(&priv->rx_lock, flags);
2093 pkt_obj.buf_list = &buf_obj;
2094 curr_pkt = &pkt_obj;
2095 curr_bd = rxch->active_queue_head;
2096 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2097 frame_status = curr_bd->mode;
2098
2099 while ((curr_bd) &&
2100 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
2101 (pkts_processed < budget)) {
2102
2103 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
2104 &new_buf_token, EMAC_DEF_RX_CH);
2105 if (unlikely(NULL == new_buffer)) {
2106 ++rxch->out_of_rx_buffers;
2107 goto end_emac_rx_bdproc;
2108 }
2109
2110 /* populate received packet data structure */
2111 rx_buf_obj = &curr_pkt->buf_list[0];
2112 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
2113 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
2114 rx_buf_obj->buf_token = curr_bd->buf_token;
2115
2116 dma_unmap_single(&priv->ndev->dev, curr_bd->buff_ptr,
2117 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
2118 DMA_FROM_DEVICE);
2119
2120 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
2121 curr_pkt->num_bufs = 1;
2122 curr_pkt->pkt_length =
2123 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
2124 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
2125 ++rxch->processed_bd;
2126 last_bd = curr_bd;
2127 curr_bd = last_bd->next;
2128 rxch->active_queue_head = curr_bd;
2129
2130 /* check if end of RX queue ? */
2131 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2132 if (curr_bd) {
2133 ++rxch->mis_queued_packets;
2134 emac_write(EMAC_RXHDP(ch),
2135 emac_virt_to_phys(curr_bd, priv));
2136 } else {
2137 ++rxch->end_of_queue;
2138 rxch->queue_active = 0;
2139 }
2140 }
2141
2142 /* recycle BD */
2143 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2144 new_buf_token);
2145
2146 /* return the packet to the user - BD ptr passed in
2147 * last parameter for potential *future* use */
2148 spin_unlock_irqrestore(&priv->rx_lock, flags);
2149 emac_net_rx_cb(priv, curr_pkt);
2150 spin_lock_irqsave(&priv->rx_lock, flags);
2151 curr_bd = rxch->active_queue_head;
2152 if (curr_bd) {
2153 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2154 frame_status = curr_bd->mode;
2155 }
2156 ++pkts_processed;
2157 }
2158
2159end_emac_rx_bdproc:
2160 spin_unlock_irqrestore(&priv->rx_lock, flags);
2161 return pkts_processed;
2162}
2163
2164/**
2165 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception 1269 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2166 * @priv: The DaVinci EMAC private adapter structure 1270 * @priv: The DaVinci EMAC private adapter structure
2167 * 1271 *
@@ -2172,7 +1276,7 @@ end_emac_rx_bdproc:
2172 */ 1276 */
2173static int emac_hw_enable(struct emac_priv *priv) 1277static int emac_hw_enable(struct emac_priv *priv)
2174{ 1278{
2175 u32 ch, val, mbp_enable, mac_control; 1279 u32 val, mbp_enable, mac_control;
2176 1280
2177 /* Soft reset */ 1281 /* Soft reset */
2178 emac_write(EMAC_SOFTRESET, 1); 1282 emac_write(EMAC_SOFTRESET, 1);
@@ -2215,26 +1319,9 @@ static int emac_hw_enable(struct emac_priv *priv)
2215 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); 1319 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2216 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; 1320 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2217 1321
2218 val = emac_read(EMAC_TXCONTROL);
2219 val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2220 emac_write(EMAC_TXCONTROL, val);
2221 val = emac_read(EMAC_RXCONTROL);
2222 val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2223 emac_write(EMAC_RXCONTROL, val);
2224 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); 1322 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2225 1323
2226 for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { 1324 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2227 emac_write(EMAC_TXHDP(ch), 0);
2228 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2229 }
2230 for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2231 struct emac_rxch *rxch = priv->rxch[ch];
2232 emac_setmac(priv, ch, rxch->mac_addr);
2233 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2234 rxch->queue_active = 1;
2235 emac_write(EMAC_RXHDP(ch),
2236 emac_virt_to_phys(rxch->active_queue_head, priv));
2237 }
2238 1325
2239 /* Enable MII */ 1326 /* Enable MII */
2240 val = emac_read(EMAC_MACCONTROL); 1327 val = emac_read(EMAC_MACCONTROL);
@@ -2279,8 +1366,8 @@ static int emac_poll(struct napi_struct *napi, int budget)
2279 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; 1366 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2280 1367
2281 if (status & mask) { 1368 if (status & mask) {
2282 num_tx_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, 1369 num_tx_pkts = cpdma_chan_process(priv->txchan,
2283 EMAC_DEF_TX_MAX_SERVICE); 1370 EMAC_DEF_TX_MAX_SERVICE);
2284 } /* TX processing */ 1371 } /* TX processing */
2285 1372
2286 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; 1373 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
@@ -2289,7 +1376,7 @@ static int emac_poll(struct napi_struct *napi, int budget)
2289 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; 1376 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2290 1377
2291 if (status & mask) { 1378 if (status & mask) {
2292 num_rx_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget); 1379 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
2293 } /* RX processing */ 1380 } /* RX processing */
2294 1381
2295 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; 1382 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
@@ -2348,79 +1435,6 @@ void emac_poll_controller(struct net_device *ndev)
2348} 1435}
2349#endif 1436#endif
2350 1437
2351/* PHY/MII bus related */
2352
2353/* Wait until mdio is ready for next command */
2354#define MDIO_WAIT_FOR_USER_ACCESS\
2355 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2356 MDIO_USERACCESS_GO) != 0)
2357
2358static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2359{
2360 unsigned int phy_data = 0;
2361 unsigned int phy_control;
2362
2363 /* Wait until mdio is ready for next command */
2364 MDIO_WAIT_FOR_USER_ACCESS;
2365
2366 phy_control = (MDIO_USERACCESS_GO |
2367 MDIO_USERACCESS_READ |
2368 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2369 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2370 (phy_data & MDIO_USERACCESS_DATA));
2371 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2372
2373 /* Wait until mdio is ready for next command */
2374 MDIO_WAIT_FOR_USER_ACCESS;
2375
2376 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2377
2378}
2379
2380static int emac_mii_write(struct mii_bus *bus, int phy_id,
2381 int phy_reg, u16 phy_data)
2382{
2383
2384 unsigned int control;
2385
2386 /* until mdio is ready for next command */
2387 MDIO_WAIT_FOR_USER_ACCESS;
2388
2389 control = (MDIO_USERACCESS_GO |
2390 MDIO_USERACCESS_WRITE |
2391 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2392 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2393 (phy_data & MDIO_USERACCESS_DATA));
2394 emac_mdio_write(MDIO_USERACCESS(0), control);
2395
2396 return 0;
2397}
2398
2399static int emac_mii_reset(struct mii_bus *bus)
2400{
2401 unsigned int clk_div;
2402 int mdio_bus_freq = emac_bus_frequency;
2403
2404 if (mdio_max_freq && mdio_bus_freq)
2405 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2406 else
2407 clk_div = 0xFF;
2408
2409 clk_div &= MDIO_CONTROL_CLKDIV;
2410
2411 /* Set enable and clock divider in MDIOControl */
2412 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2413
2414 return 0;
2415
2416}
2417
2418static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2419
2420/* emac_driver: EMAC MII bus structure */
2421
2422static struct mii_bus *emac_mii;
2423
2424static void emac_adjust_link(struct net_device *ndev) 1438static void emac_adjust_link(struct net_device *ndev)
2425{ 1439{
2426 struct emac_priv *priv = netdev_priv(ndev); 1440 struct emac_priv *priv = netdev_priv(ndev);
@@ -2485,6 +1499,11 @@ static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2485 return -EOPNOTSUPP; 1499 return -EOPNOTSUPP;
2486} 1500}
2487 1501
1502static int match_first_device(struct device *dev, void *data)
1503{
1504 return 1;
1505}
1506
2488/** 1507/**
2489 * emac_dev_open: EMAC device open 1508 * emac_dev_open: EMAC device open
2490 * @ndev: The DaVinci EMAC network adapter 1509 * @ndev: The DaVinci EMAC network adapter
@@ -2498,10 +1517,9 @@ static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2498static int emac_dev_open(struct net_device *ndev) 1517static int emac_dev_open(struct net_device *ndev)
2499{ 1518{
2500 struct device *emac_dev = &ndev->dev; 1519 struct device *emac_dev = &ndev->dev;
2501 u32 rc, cnt, ch; 1520 u32 cnt;
2502 int phy_addr;
2503 struct resource *res; 1521 struct resource *res;
2504 int q, m; 1522 int q, m, ret;
2505 int i = 0; 1523 int i = 0;
2506 int k = 0; 1524 int k = 0;
2507 struct emac_priv *priv = netdev_priv(ndev); 1525 struct emac_priv *priv = netdev_priv(ndev);
@@ -2513,29 +1531,21 @@ static int emac_dev_open(struct net_device *ndev)
2513 /* Configuration items */ 1531 /* Configuration items */
2514 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; 1532 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2515 1533
2516 /* Clear basic hardware */
2517 for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2518 emac_write(EMAC_TXHDP(ch), 0);
2519 emac_write(EMAC_RXHDP(ch), 0);
2520 emac_write(EMAC_RXHDP(ch), 0);
2521 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2522 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2523 }
2524 priv->mac_hash1 = 0; 1534 priv->mac_hash1 = 0;
2525 priv->mac_hash2 = 0; 1535 priv->mac_hash2 = 0;
2526 emac_write(EMAC_MACHASH1, 0); 1536 emac_write(EMAC_MACHASH1, 0);
2527 emac_write(EMAC_MACHASH2, 0); 1537 emac_write(EMAC_MACHASH2, 0);
2528 1538
2529 /* multi ch not supported - open 1 TX, 1RX ch by default */ 1539 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
2530 rc = emac_init_txch(priv, EMAC_DEF_TX_CH); 1540 struct sk_buff *skb = emac_rx_alloc(priv);
2531 if (0 != rc) { 1541
2532 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed"); 1542 if (!skb)
2533 return rc; 1543 break;
2534 } 1544
2535 rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1545 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
2536 if (0 != rc) { 1546 skb_tailroom(skb), GFP_KERNEL);
2537 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed"); 1547 if (WARN_ON(ret < 0))
2538 return rc; 1548 break;
2539 } 1549 }
2540 1550
2541 /* Request IRQ */ 1551 /* Request IRQ */
@@ -2560,28 +1570,28 @@ static int emac_dev_open(struct net_device *ndev)
2560 emac_set_coalesce(ndev, &coal); 1570 emac_set_coalesce(ndev, &coal);
2561 } 1571 }
2562 1572
2563 /* find the first phy */ 1573 cpdma_ctlr_start(priv->dma);
1574
2564 priv->phydev = NULL; 1575 priv->phydev = NULL;
2565 if (priv->phy_mask) { 1576 /* use the first phy on the bus if pdata did not give us a phy id */
2566 emac_mii_reset(priv->mii_bus); 1577 if (!priv->phy_id) {
2567 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 1578 struct device *phy;
2568 if (priv->mii_bus->phy_map[phy_addr]) {
2569 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2570 break;
2571 }
2572 }
2573 1579
2574 if (!priv->phydev) { 1580 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
2575 printk(KERN_ERR "%s: no PHY found\n", ndev->name); 1581 match_first_device);
2576 return -1; 1582 if (phy)
2577 } 1583 priv->phy_id = dev_name(phy);
1584 }
2578 1585
2579 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev), 1586 if (priv->phy_id && *priv->phy_id) {
2580 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII); 1587 priv->phydev = phy_connect(ndev, priv->phy_id,
1588 &emac_adjust_link, 0,
1589 PHY_INTERFACE_MODE_MII);
2581 1590
2582 if (IS_ERR(priv->phydev)) { 1591 if (IS_ERR(priv->phydev)) {
2583 printk(KERN_ERR "%s: Could not attach to PHY\n", 1592 dev_err(emac_dev, "could not connect to phy %s\n",
2584 ndev->name); 1593 priv->phy_id);
1594 priv->phydev = NULL;
2585 return PTR_ERR(priv->phydev); 1595 return PTR_ERR(priv->phydev);
2586 } 1596 }
2587 1597
@@ -2589,12 +1599,13 @@ static int emac_dev_open(struct net_device *ndev)
2589 priv->speed = 0; 1599 priv->speed = 0;
2590 priv->duplex = ~0; 1600 priv->duplex = ~0;
2591 1601
2592 printk(KERN_INFO "%s: attached PHY driver [%s] " 1602 dev_info(emac_dev, "attached PHY driver [%s] "
2593 "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name, 1603 "(mii_bus:phy_addr=%s, id=%x)\n",
2594 priv->phydev->drv->name, dev_name(&priv->phydev->dev), 1604 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2595 priv->phydev->phy_id); 1605 priv->phydev->phy_id);
2596 } else{ 1606 } else {
2597 /* No PHY , fix the link, speed and duplex settings */ 1607 /* No PHY , fix the link, speed and duplex settings */
1608 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
2598 priv->link = 1; 1609 priv->link = 1;
2599 priv->speed = SPEED_100; 1610 priv->speed = SPEED_100;
2600 priv->duplex = DUPLEX_FULL; 1611 priv->duplex = DUPLEX_FULL;
@@ -2607,7 +1618,7 @@ static int emac_dev_open(struct net_device *ndev)
2607 if (netif_msg_drv(priv)) 1618 if (netif_msg_drv(priv))
2608 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); 1619 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2609 1620
2610 if (priv->phy_mask) 1621 if (priv->phydev)
2611 phy_start(priv->phydev); 1622 phy_start(priv->phydev);
2612 1623
2613 return 0; 1624 return 0;
@@ -2648,10 +1659,7 @@ static int emac_dev_stop(struct net_device *ndev)
2648 1659
2649 netif_carrier_off(ndev); 1660 netif_carrier_off(ndev);
2650 emac_int_disable(priv); 1661 emac_int_disable(priv);
2651 emac_stop_txch(priv, EMAC_DEF_TX_CH); 1662 cpdma_ctlr_stop(priv->dma);
2652 emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2653 emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2654 emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2655 emac_write(EMAC_SOFTRESET, 1); 1663 emac_write(EMAC_SOFTRESET, 1);
2656 1664
2657 if (priv->phydev) 1665 if (priv->phydev)
@@ -2722,7 +1730,7 @@ static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2722 emac_read(EMAC_TXCARRIERSENSE); 1730 emac_read(EMAC_TXCARRIERSENSE);
2723 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); 1731 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2724 1732
2725 ndev->stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); 1733 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
2726 emac_write(EMAC_TXUNDERRUN, stats_clear_mask); 1734 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2727 1735
2728 return &ndev->stats; 1736 return &ndev->stats;
@@ -2756,14 +1764,15 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2756 struct resource *res; 1764 struct resource *res;
2757 struct net_device *ndev; 1765 struct net_device *ndev;
2758 struct emac_priv *priv; 1766 struct emac_priv *priv;
2759 unsigned long size; 1767 unsigned long size, hw_ram_addr;
2760 struct emac_platform_data *pdata; 1768 struct emac_platform_data *pdata;
2761 struct device *emac_dev; 1769 struct device *emac_dev;
1770 struct cpdma_params dma_params;
2762 1771
2763 /* obtain emac clock from kernel */ 1772 /* obtain emac clock from kernel */
2764 emac_clk = clk_get(&pdev->dev, NULL); 1773 emac_clk = clk_get(&pdev->dev, NULL);
2765 if (IS_ERR(emac_clk)) { 1774 if (IS_ERR(emac_clk)) {
2766 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n"); 1775 dev_err(&pdev->dev, "failed to get EMAC clock\n");
2767 return -EBUSY; 1776 return -EBUSY;
2768 } 1777 }
2769 emac_bus_frequency = clk_get_rate(emac_clk); 1778 emac_bus_frequency = clk_get_rate(emac_clk);
@@ -2771,9 +1780,9 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2771 1780
2772 ndev = alloc_etherdev(sizeof(struct emac_priv)); 1781 ndev = alloc_etherdev(sizeof(struct emac_priv));
2773 if (!ndev) { 1782 if (!ndev) {
2774 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n"); 1783 dev_err(&pdev->dev, "error allocating net_device\n");
2775 clk_put(emac_clk); 1784 rc = -ENOMEM;
2776 return -ENOMEM; 1785 goto free_clk;
2777 } 1786 }
2778 1787
2779 platform_set_drvdata(pdev, ndev); 1788 platform_set_drvdata(pdev, ndev);
@@ -2782,19 +1791,18 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2782 priv->ndev = ndev; 1791 priv->ndev = ndev;
2783 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); 1792 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2784 1793
2785 spin_lock_init(&priv->tx_lock);
2786 spin_lock_init(&priv->rx_lock);
2787 spin_lock_init(&priv->lock); 1794 spin_lock_init(&priv->lock);
2788 1795
2789 pdata = pdev->dev.platform_data; 1796 pdata = pdev->dev.platform_data;
2790 if (!pdata) { 1797 if (!pdata) {
2791 printk(KERN_ERR "DaVinci EMAC: No platform data\n"); 1798 dev_err(&pdev->dev, "no platform data\n");
2792 return -ENODEV; 1799 rc = -ENODEV;
1800 goto probe_quit;
2793 } 1801 }
2794 1802
2795 /* MAC addr and PHY mask , RMII enable info from platform_data */ 1803 /* MAC addr and PHY mask , RMII enable info from platform_data */
2796 memcpy(priv->mac_addr, pdata->mac_addr, 6); 1804 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2797 priv->phy_mask = pdata->phy_mask; 1805 priv->phy_id = pdata->phy_id;
2798 priv->rmii_en = pdata->rmii_en; 1806 priv->rmii_en = pdata->rmii_en;
2799 priv->version = pdata->version; 1807 priv->version = pdata->version;
2800 priv->int_enable = pdata->interrupt_enable; 1808 priv->int_enable = pdata->interrupt_enable;
@@ -2807,7 +1815,7 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2807 /* Get EMAC platform data */ 1815 /* Get EMAC platform data */
2808 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1816 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2809 if (!res) { 1817 if (!res) {
2810 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n"); 1818 dev_err(&pdev->dev,"error getting res\n");
2811 rc = -ENOENT; 1819 rc = -ENOENT;
2812 goto probe_quit; 1820 goto probe_quit;
2813 } 1821 }
@@ -2815,14 +1823,14 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2815 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; 1823 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2816 size = res->end - res->start + 1; 1824 size = res->end - res->start + 1;
2817 if (!request_mem_region(res->start, size, ndev->name)) { 1825 if (!request_mem_region(res->start, size, ndev->name)) {
2818 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() for regs\n"); 1826 dev_err(&pdev->dev, "failed request_mem_region() for regs\n");
2819 rc = -ENXIO; 1827 rc = -ENXIO;
2820 goto probe_quit; 1828 goto probe_quit;
2821 } 1829 }
2822 1830
2823 priv->remap_addr = ioremap(res->start, size); 1831 priv->remap_addr = ioremap(res->start, size);
2824 if (!priv->remap_addr) { 1832 if (!priv->remap_addr) {
2825 dev_err(emac_dev, "Unable to map IO\n"); 1833 dev_err(&pdev->dev, "unable to map IO\n");
2826 rc = -ENOMEM; 1834 rc = -ENOMEM;
2827 release_mem_region(res->start, size); 1835 release_mem_region(res->start, size);
2828 goto probe_quit; 1836 goto probe_quit;
@@ -2831,18 +1839,48 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2831 ndev->base_addr = (unsigned long)priv->remap_addr; 1839 ndev->base_addr = (unsigned long)priv->remap_addr;
2832 1840
2833 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; 1841 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2834 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2835 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2836 1842
2837 if (pdata->hw_ram_addr) 1843 hw_ram_addr = pdata->hw_ram_addr;
2838 priv->hw_ram_addr = pdata->hw_ram_addr; 1844 if (!hw_ram_addr)
2839 else 1845 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
2840 priv->hw_ram_addr = (u32 __force)res->start + 1846
2841 pdata->ctrl_ram_offset; 1847 memset(&dma_params, 0, sizeof(dma_params));
1848 dma_params.dev = emac_dev;
1849 dma_params.dmaregs = priv->emac_base;
1850 dma_params.rxthresh = priv->emac_base + 0x120;
1851 dma_params.rxfree = priv->emac_base + 0x140;
1852 dma_params.txhdp = priv->emac_base + 0x600;
1853 dma_params.rxhdp = priv->emac_base + 0x620;
1854 dma_params.txcp = priv->emac_base + 0x640;
1855 dma_params.rxcp = priv->emac_base + 0x660;
1856 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1857 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1858 dma_params.desc_hw_addr = hw_ram_addr;
1859 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1860 dma_params.desc_align = 16;
1861
1862 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1863 (u32 __force)res->start + pdata->ctrl_ram_offset;
1864
1865 priv->dma = cpdma_ctlr_create(&dma_params);
1866 if (!priv->dma) {
1867 dev_err(&pdev->dev, "error initializing DMA\n");
1868 rc = -ENOMEM;
1869 goto no_dma;
1870 }
1871
1872 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1873 emac_tx_handler);
1874 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1875 emac_rx_handler);
1876 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1877 rc = -ENOMEM;
1878 goto no_irq_res;
1879 }
2842 1880
2843 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1881 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2844 if (!res) { 1882 if (!res) {
2845 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n"); 1883 dev_err(&pdev->dev, "error getting irq res\n");
2846 rc = -ENOENT; 1884 rc = -ENOENT;
2847 goto no_irq_res; 1885 goto no_irq_res;
2848 } 1886 }
@@ -2851,8 +1889,8 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2851 if (!is_valid_ether_addr(priv->mac_addr)) { 1889 if (!is_valid_ether_addr(priv->mac_addr)) {
2852 /* Use random MAC if none passed */ 1890 /* Use random MAC if none passed */
2853 random_ether_addr(priv->mac_addr); 1891 random_ether_addr(priv->mac_addr);
2854 printk(KERN_WARNING "%s: using random MAC addr: %pM\n", 1892 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
2855 __func__, priv->mac_addr); 1893 priv->mac_addr);
2856 } 1894 }
2857 1895
2858 ndev->netdev_ops = &emac_netdev_ops; 1896 ndev->netdev_ops = &emac_netdev_ops;
@@ -2865,38 +1903,12 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2865 SET_NETDEV_DEV(ndev, &pdev->dev); 1903 SET_NETDEV_DEV(ndev, &pdev->dev);
2866 rc = register_netdev(ndev); 1904 rc = register_netdev(ndev);
2867 if (rc) { 1905 if (rc) {
2868 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n"); 1906 dev_err(&pdev->dev, "error in register_netdev\n");
2869 rc = -ENODEV; 1907 rc = -ENODEV;
2870 goto netdev_reg_err; 1908 goto netdev_reg_err;
2871 } 1909 }
2872 1910
2873 1911
2874 /* MII/Phy intialisation, mdio bus registration */
2875 emac_mii = mdiobus_alloc();
2876 if (emac_mii == NULL) {
2877 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2878 rc = -ENOMEM;
2879 goto mdio_alloc_err;
2880 }
2881
2882 priv->mii_bus = emac_mii;
2883 emac_mii->name = "emac-mii",
2884 emac_mii->read = emac_mii_read,
2885 emac_mii->write = emac_mii_write,
2886 emac_mii->reset = emac_mii_reset,
2887 emac_mii->irq = mii_irqs,
2888 emac_mii->phy_mask = ~(priv->phy_mask);
2889 emac_mii->parent = &pdev->dev;
2890 emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2891 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2892 mdio_max_freq = pdata->mdio_max_freq;
2893 emac_mii->reset(emac_mii);
2894
2895 /* Register the MII bus */
2896 rc = mdiobus_register(emac_mii);
2897 if (rc)
2898 goto mdiobus_quit;
2899
2900 if (netif_msg_probe(priv)) { 1912 if (netif_msg_probe(priv)) {
2901 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\ 1913 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2902 "(regs: %p, irq: %d)\n", 1914 "(regs: %p, irq: %d)\n",
@@ -2904,20 +1916,23 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
2904 } 1916 }
2905 return 0; 1917 return 0;
2906 1918
2907mdiobus_quit:
2908 mdiobus_free(emac_mii);
2909
2910netdev_reg_err: 1919netdev_reg_err:
2911mdio_alloc_err:
2912 clk_disable(emac_clk); 1920 clk_disable(emac_clk);
2913no_irq_res: 1921no_irq_res:
1922 if (priv->txchan)
1923 cpdma_chan_destroy(priv->txchan);
1924 if (priv->rxchan)
1925 cpdma_chan_destroy(priv->rxchan);
1926 cpdma_ctlr_destroy(priv->dma);
1927no_dma:
2914 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1928 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2915 release_mem_region(res->start, res->end - res->start + 1); 1929 release_mem_region(res->start, res->end - res->start + 1);
2916 iounmap(priv->remap_addr); 1930 iounmap(priv->remap_addr);
2917 1931
2918probe_quit: 1932probe_quit:
2919 clk_put(emac_clk);
2920 free_netdev(ndev); 1933 free_netdev(ndev);
1934free_clk:
1935 clk_put(emac_clk);
2921 return rc; 1936 return rc;
2922} 1937}
2923 1938
@@ -2938,8 +1953,12 @@ static int __devexit davinci_emac_remove(struct platform_device *pdev)
2938 1953
2939 platform_set_drvdata(pdev, NULL); 1954 platform_set_drvdata(pdev, NULL);
2940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1955 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2941 mdiobus_unregister(priv->mii_bus); 1956
2942 mdiobus_free(priv->mii_bus); 1957 if (priv->txchan)
1958 cpdma_chan_destroy(priv->txchan);
1959 if (priv->rxchan)
1960 cpdma_chan_destroy(priv->rxchan);
1961 cpdma_ctlr_destroy(priv->dma);
2943 1962
2944 release_mem_region(res->start, res->end - res->start + 1); 1963 release_mem_region(res->start, res->end - res->start + 1);
2945 1964
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-05 13:37:58 -0400