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path: root/drivers/net/cxgb3/t3_cpl.h
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Diffstat (limited to 'drivers/net/cxgb3/t3_cpl.h')
-rw-r--r--drivers/net/cxgb3/t3_cpl.h40
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/net/cxgb3/t3_cpl.h b/drivers/net/cxgb3/t3_cpl.h
index a666c5d51cc0..917970ed24a1 100644
--- a/drivers/net/cxgb3/t3_cpl.h
+++ b/drivers/net/cxgb3/t3_cpl.h
@@ -191,6 +191,9 @@ union opcode_tid {
191#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 191#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
192#define G_TID(x) ((x) & 0xFFFFFF) 192#define G_TID(x) ((x) & 0xFFFFFF)
193 193
194#define S_QNUM 0
195#define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF)
196
194#define S_HASHTYPE 22 197#define S_HASHTYPE 22
195#define M_HASHTYPE 0x3 198#define M_HASHTYPE 0x3
196#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 199#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
@@ -779,6 +782,12 @@ struct tx_data_wr {
779 __be32 param; 782 __be32 param;
780}; 783};
781 784
785/* tx_data_wr.flags fields */
786#define S_TX_ACK_PAGES 21
787#define M_TX_ACK_PAGES 0x7
788#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
789#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
790
782/* tx_data_wr.param fields */ 791/* tx_data_wr.param fields */
783#define S_TX_PORT 0 792#define S_TX_PORT 0
784#define M_TX_PORT 0x7 793#define M_TX_PORT 0x7
@@ -1452,4 +1461,35 @@ struct cpl_rdma_terminate {
1452#define M_TERM_TID 0xFFFFF 1461#define M_TERM_TID 0xFFFFF
1453#define V_TERM_TID(x) ((x) << S_TERM_TID) 1462#define V_TERM_TID(x) ((x) << S_TERM_TID)
1454#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1463#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1464
1465/* ULP_TX opcodes */
1466enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1467
1468#define S_ULPTX_CMD 28
1469#define M_ULPTX_CMD 0xF
1470#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1471
1472#define S_ULPTX_NFLITS 0
1473#define M_ULPTX_NFLITS 0xFF
1474#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1475
1476struct ulp_mem_io {
1477 WR_HDR;
1478 __be32 cmd_lock_addr;
1479 __be32 len;
1480};
1481
1482/* ulp_mem_io.cmd_lock_addr fields */
1483#define S_ULP_MEMIO_ADDR 0
1484#define M_ULP_MEMIO_ADDR 0x7FFFFFF
1485#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1486#define S_ULP_MEMIO_LOCK 27
1487#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1488#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1489
1490/* ulp_mem_io.len fields */
1491#define S_ULP_MEMIO_DATA_LEN 28
1492#define M_ULP_MEMIO_DATA_LEN 0xF
1493#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1494
1455#endif /* T3_CPL_H */ 1495#endif /* T3_CPL_H */