1 files changed, 145 insertions, 0 deletions
diff --git a/drivers/net/chelsio/cpl5_cmd.h b/drivers/net/chelsio/cpl5_cmd.h
new file mode 100644
index 000000000000..27925e487bcf
--- /dev/null
+++ b/drivers/net/chelsio/cpl5_cmd.h
@@ -0,0 +1,145 @@
+/*****************************************************************************
+ *                                                                           *
+ * File: cpl5_cmd.h                                                          *
+ * $Revision: 1.6 $                                                          *
+ * $Date: 2005/06/21 18:29:47 $                                              *
+ * Description:                                                              *
+ *  part of the Chelsio 10Gb Ethernet Driver.                                *
+ *                                                                           *
+ * This program is free software; you can redistribute it and/or modify      *
+ * it under the terms of the GNU General Public License, version 2, as       *
+ * published by the Free Software Foundation.                                *
+ *                                                                           *
+ * You should have received a copy of the GNU General Public License along   *
+ * with this program; if not, write to the Free Software Foundation, Inc.,   *
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
+ *                                                                           *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
+ *                                                                           *
+ * http://www.chelsio.com                                                    *
+ *                                                                           *
+ * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
+ * All rights reserved.                                                      *
+ *                                                                           *
+ * Maintainers: maintainers@chelsio.com                                      *
+ *                                                                           *
+ * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
+ *          Tina Yang               <tainay@chelsio.com>                     *
+ *          Felix Marti             <felix@chelsio.com>                      *
+ *          Scott Bardone           <sbardone@chelsio.com>                   *
+ *          Kurt Ottaway            <kottaway@chelsio.com>                   *
+ *          Frank DiMambro          <frank@chelsio.com>                      *
+ *                                                                           *
+ * History:                                                                  *
+ *                                                                           *
+ ****************************************************************************/
+#ifndef _CXGB_CPL5_CMD_H_
+#define _CXGB_CPL5_CMD_H_
+#include <asm/byteorder.h>
+#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
+#error "Adjust your <asm/byteorder.h> defines"
+#endif
+enum CPL_opcode {
+        CPL_RX_PKT            = 0xAD,
+        CPL_TX_PKT            = 0xB2,
+        CPL_TX_PKT_LSO        = 0xB6,
+};
+enum {                /* TX_PKT_LSO ethernet types */
+        CPL_ETH_II,
+        CPL_ETH_II_VLAN,
+        CPL_ETH_802_3,
+        CPL_ETH_802_3_VLAN
+};
+struct cpl_rx_data {
+        u32 rsvd0;
+        u32 len;
+        u32 seq;
+        u16 urg;
+        u8  rsvd1;
+        u8  status;
+};
+/*
+ * We want this header's alignment to be no more stringent than 2-byte aligned.
+ * All fields are u8 or u16 except for the length.  However that field is not
+ * used so we break it into 2 16-bit parts to easily meet our alignment needs.
+ */
+struct cpl_tx_pkt {
+        u8 opcode;
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+        u8 iff:4;
+        u8 ip_csum_dis:1;
+        u8 l4_csum_dis:1;
+        u8 vlan_valid:1;
+        u8 rsvd:1;
+#else
+        u8 rsvd:1;
+        u8 vlan_valid:1;
+        u8 l4_csum_dis:1;
+        u8 ip_csum_dis:1;
+        u8 iff:4;
+#endif
+        u16 vlan;
+        u16 len_hi;
+        u16 len_lo;
+};
+struct cpl_tx_pkt_lso {
+        u8 opcode;
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+        u8 iff:4;
+        u8 ip_csum_dis:1;
+        u8 l4_csum_dis:1;
+        u8 vlan_valid:1;
+        u8 rsvd:1;
+#else
+        u8 rsvd:1;
+        u8 vlan_valid:1;
+        u8 l4_csum_dis:1;
+        u8 ip_csum_dis:1;
+        u8 iff:4;
+#endif
+        u16 vlan;
+        u32 len;
+        u32 rsvd2;
+        u8 rsvd3;
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+        u8 tcp_hdr_words:4;
+        u8 ip_hdr_words:4;
+#else
+        u8 ip_hdr_words:4;
+        u8 tcp_hdr_words:4;
+#endif
+        u16 eth_type_mss;
+};
+struct cpl_rx_pkt {
+        u8 opcode;
+#if defined(__LITTLE_ENDIAN_BITFIELD)
+        u8 iff:4;
+        u8 csum_valid:1;
+        u8 bad_pkt:1;
+        u8 vlan_valid:1;
+        u8 rsvd:1;
+#else
+        u8 rsvd:1;
+        u8 vlan_valid:1;
+        u8 bad_pkt:1;
+        u8 csum_valid:1;
+        u8 iff:4;
+#endif
+        u16 csum;
+        u16 vlan;
+        u16 len;
+};
+#endif /* _CXGB_CPL5_CMD_H_ */

diff --git a/drivers/net/chelsio/cpl5_cmd.h b/drivers/net/chelsio/cpl5_cmd.h new file mode 100644 index 000000000000..27925e487bcf --- /dev/null +++ b/drivers/net/chelsio/cpl5_cmd.h
@@ -0,0 +1,145 @@
	1	/*****************************************************************************
	2	* *
	3	* File: cpl5_cmd.h *
	4	* $Revision: 1.6 $ *
	5	* $Date: 2005/06/21 18:29:47 $ *
	6	* Description: *
	7	* part of the Chelsio 10Gb Ethernet Driver. *
	8	* *
	9	* This program is free software; you can redistribute it and/or modify *
	10	* it under the terms of the GNU General Public License, version 2, as *
	11	* published by the Free Software Foundation. *
	12	* *
	13	* You should have received a copy of the GNU General Public License along *
	14	* with this program; if not, write to the Free Software Foundation, Inc., *
	15	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
	16	* *
	17	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
	18	* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
	19	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
	20	* *
	21	* http://www.chelsio.com *
	22	* *
	23	* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
	24	* All rights reserved. *
	25	* *
	26	* Maintainers: maintainers@chelsio.com *
	27	* *
	28	* Authors: Dimitrios Michailidis <dm@chelsio.com> *
	29	* Tina Yang <tainay@chelsio.com> *
	30	* Felix Marti <felix@chelsio.com> *
	31	* Scott Bardone <sbardone@chelsio.com> *
	32	* Kurt Ottaway <kottaway@chelsio.com> *
	33	* Frank DiMambro <frank@chelsio.com> *
	34	* *
	35	* History: *
	36	* *
	37	****************************************************************************/
	38
	39	#ifndef _CXGB_CPL5_CMD_H_
	40	#define _CXGB_CPL5_CMD_H_
	41
	42	#include <asm/byteorder.h>
	43
	44	#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
	45	#error "Adjust your <asm/byteorder.h> defines"
	46	#endif
	47
	48	enum CPL_opcode {
	49	CPL_RX_PKT = 0xAD,
	50	CPL_TX_PKT = 0xB2,
	51	CPL_TX_PKT_LSO = 0xB6,
	52	};
	53
	54	enum { /* TX_PKT_LSO ethernet types */
	55	CPL_ETH_II,
	56	CPL_ETH_II_VLAN,
	57	CPL_ETH_802_3,
	58	CPL_ETH_802_3_VLAN
	59	};
	60
	61	struct cpl_rx_data {
	62	u32 rsvd0;
	63	u32 len;
	64	u32 seq;
	65	u16 urg;
	66	u8 rsvd1;
	67	u8 status;
	68	};
	69
	70	/*
	71	* We want this header's alignment to be no more stringent than 2-byte aligned.
	72	* All fields are u8 or u16 except for the length. However that field is not
	73	* used so we break it into 2 16-bit parts to easily meet our alignment needs.
	74	*/
	75	struct cpl_tx_pkt {
	76	u8 opcode;
	77	#if defined(__LITTLE_ENDIAN_BITFIELD)
	78	u8 iff:4;
	79	u8 ip_csum_dis:1;
	80	u8 l4_csum_dis:1;
	81	u8 vlan_valid:1;
	82	u8 rsvd:1;
	83	#else
	84	u8 rsvd:1;
	85	u8 vlan_valid:1;
	86	u8 l4_csum_dis:1;
	87	u8 ip_csum_dis:1;
	88	u8 iff:4;
	89	#endif
	90	u16 vlan;
	91	u16 len_hi;
	92	u16 len_lo;
	93	};
	94
	95	struct cpl_tx_pkt_lso {
	96	u8 opcode;
	97	#if defined(__LITTLE_ENDIAN_BITFIELD)
	98	u8 iff:4;
	99	u8 ip_csum_dis:1;
	100	u8 l4_csum_dis:1;
	101	u8 vlan_valid:1;
	102	u8 rsvd:1;
	103	#else
	104	u8 rsvd:1;
	105	u8 vlan_valid:1;
	106	u8 l4_csum_dis:1;
	107	u8 ip_csum_dis:1;
	108	u8 iff:4;
	109	#endif
	110	u16 vlan;
	111	u32 len;
	112
	113	u32 rsvd2;
	114	u8 rsvd3;
	115	#if defined(__LITTLE_ENDIAN_BITFIELD)
	116	u8 tcp_hdr_words:4;
	117	u8 ip_hdr_words:4;
	118	#else
	119	u8 ip_hdr_words:4;
	120	u8 tcp_hdr_words:4;
	121	#endif
	122	u16 eth_type_mss;
	123	};
	124
	125	struct cpl_rx_pkt {
	126	u8 opcode;
	127	#if defined(__LITTLE_ENDIAN_BITFIELD)
	128	u8 iff:4;
	129	u8 csum_valid:1;
	130	u8 bad_pkt:1;
	131	u8 vlan_valid:1;
	132	u8 rsvd:1;
	133	#else
	134	u8 rsvd:1;
	135	u8 vlan_valid:1;
	136	u8 bad_pkt:1;
	137	u8 csum_valid:1;
	138	u8 iff:4;
	139	#endif
	140	u16 csum;
	141	u16 vlan;
	142	u16 len;
	143	};
	144
	145	#endif /* _CXGB_CPL5_CMD_H_ */