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-rw-r--r--drivers/net/can/Kconfig30
-rw-r--r--drivers/net/can/Makefile4
-rw-r--r--drivers/net/can/c_can/c_can.c15
-rw-r--r--drivers/net/can/c_can/c_can.h8
-rw-r--r--drivers/net/can/c_can/c_can_pci.c78
-rw-r--r--drivers/net/can/c_can/c_can_platform.c84
-rw-r--r--drivers/net/can/mscan/Kconfig2
-rw-r--r--drivers/net/can/rcar_can.c876
-rw-r--r--drivers/net/can/softing/softing_main.c20
-rw-r--r--drivers/net/can/spi/Kconfig10
-rw-r--r--drivers/net/can/spi/Makefile8
-rw-r--r--drivers/net/can/spi/mcp251x.c (renamed from drivers/net/can/mcp251x.c)95
-rw-r--r--drivers/net/can/usb/Kconfig12
-rw-r--r--drivers/net/can/usb/Makefile1
-rw-r--r--drivers/net/can/usb/gs_usb.c971
-rw-r--r--drivers/net/can/usb/kvaser_usb.c53
-rw-r--r--drivers/net/can/xilinx_can.c1208
17 files changed, 3351 insertions, 124 deletions
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 9e7d95dae2c7..41688229c570 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -65,7 +65,7 @@ config CAN_LEDS
65 65
66config CAN_AT91 66config CAN_AT91
67 tristate "Atmel AT91 onchip CAN controller" 67 tristate "Atmel AT91 onchip CAN controller"
68 depends on ARM 68 depends on ARCH_AT91 || COMPILE_TEST
69 ---help--- 69 ---help---
70 This is a driver for the SoC CAN controller in Atmel's AT91SAM9263 70 This is a driver for the SoC CAN controller in Atmel's AT91SAM9263
71 and AT91SAM9X5 processors. 71 and AT91SAM9X5 processors.
@@ -77,12 +77,6 @@ config CAN_TI_HECC
77 Driver for TI HECC (High End CAN Controller) module found on many 77 Driver for TI HECC (High End CAN Controller) module found on many
78 TI devices. The device specifications are available from www.ti.com 78 TI devices. The device specifications are available from www.ti.com
79 79
80config CAN_MCP251X
81 tristate "Microchip MCP251x SPI CAN controllers"
82 depends on SPI && HAS_DMA
83 ---help---
84 Driver for the Microchip MCP251x SPI CAN controllers.
85
86config CAN_BFIN 80config CAN_BFIN
87 depends on BF534 || BF536 || BF537 || BF538 || BF539 || BF54x 81 depends on BF534 || BF536 || BF537 || BF538 || BF539 || BF54x
88 tristate "Analog Devices Blackfin on-chip CAN" 82 tristate "Analog Devices Blackfin on-chip CAN"
@@ -110,7 +104,7 @@ config CAN_FLEXCAN
110 104
111config PCH_CAN 105config PCH_CAN
112 tristate "Intel EG20T PCH CAN controller" 106 tristate "Intel EG20T PCH CAN controller"
113 depends on PCI 107 depends on PCI && (X86_32 || COMPILE_TEST)
114 ---help--- 108 ---help---
115 This driver is for PCH CAN of Topcliff (Intel EG20T PCH) which 109 This driver is for PCH CAN of Topcliff (Intel EG20T PCH) which
116 is an IOH for x86 embedded processor (Intel Atom E6xx series). 110 is an IOH for x86 embedded processor (Intel Atom E6xx series).
@@ -125,6 +119,24 @@ config CAN_GRCAN
125 endian syntheses of the cores would need some modifications on 119 endian syntheses of the cores would need some modifications on
126 the hardware level to work. 120 the hardware level to work.
127 121
122config CAN_RCAR
123 tristate "Renesas R-Car CAN controller"
124 depends on ARM
125 ---help---
126 Say Y here if you want to use CAN controller found on Renesas R-Car
127 SoCs.
128
129 To compile this driver as a module, choose M here: the module will
130 be called rcar_can.
131
132config CAN_XILINXCAN
133 tristate "Xilinx CAN"
134 depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
135 depends on COMMON_CLK && HAS_IOMEM
136 ---help---
137 Xilinx CAN driver. This driver supports both soft AXI CAN IP and
138 Zynq CANPS IP.
139
128source "drivers/net/can/mscan/Kconfig" 140source "drivers/net/can/mscan/Kconfig"
129 141
130source "drivers/net/can/sja1000/Kconfig" 142source "drivers/net/can/sja1000/Kconfig"
@@ -133,6 +145,8 @@ source "drivers/net/can/c_can/Kconfig"
133 145
134source "drivers/net/can/cc770/Kconfig" 146source "drivers/net/can/cc770/Kconfig"
135 147
148source "drivers/net/can/spi/Kconfig"
149
136source "drivers/net/can/usb/Kconfig" 150source "drivers/net/can/usb/Kconfig"
137 151
138source "drivers/net/can/softing/Kconfig" 152source "drivers/net/can/softing/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index c7440392adbb..1697f22353a9 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -10,6 +10,7 @@ can-dev-y := dev.o
10 10
11can-dev-$(CONFIG_CAN_LEDS) += led.o 11can-dev-$(CONFIG_CAN_LEDS) += led.o
12 12
13obj-y += spi/
13obj-y += usb/ 14obj-y += usb/
14obj-y += softing/ 15obj-y += softing/
15 16
@@ -19,11 +20,12 @@ obj-$(CONFIG_CAN_C_CAN) += c_can/
19obj-$(CONFIG_CAN_CC770) += cc770/ 20obj-$(CONFIG_CAN_CC770) += cc770/
20obj-$(CONFIG_CAN_AT91) += at91_can.o 21obj-$(CONFIG_CAN_AT91) += at91_can.o
21obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o 22obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
22obj-$(CONFIG_CAN_MCP251X) += mcp251x.o
23obj-$(CONFIG_CAN_BFIN) += bfin_can.o 23obj-$(CONFIG_CAN_BFIN) += bfin_can.o
24obj-$(CONFIG_CAN_JANZ_ICAN3) += janz-ican3.o 24obj-$(CONFIG_CAN_JANZ_ICAN3) += janz-ican3.o
25obj-$(CONFIG_CAN_FLEXCAN) += flexcan.o 25obj-$(CONFIG_CAN_FLEXCAN) += flexcan.o
26obj-$(CONFIG_PCH_CAN) += pch_can.o 26obj-$(CONFIG_PCH_CAN) += pch_can.o
27obj-$(CONFIG_CAN_GRCAN) += grcan.o 27obj-$(CONFIG_CAN_GRCAN) += grcan.o
28obj-$(CONFIG_CAN_RCAR) += rcar_can.o
29obj-$(CONFIG_CAN_XILINXCAN) += xilinx_can.o
28 30
29ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG 31ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c
index 95e04e2002da..8e78bb48f5a4 100644
--- a/drivers/net/can/c_can/c_can.c
+++ b/drivers/net/can/c_can/c_can.c
@@ -252,8 +252,7 @@ static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj
252 struct c_can_priv *priv = netdev_priv(dev); 252 struct c_can_priv *priv = netdev_priv(dev);
253 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); 253 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
254 254
255 priv->write_reg(priv, reg + 1, cmd); 255 priv->write_reg32(priv, reg, (cmd << 16) | obj);
256 priv->write_reg(priv, reg, obj);
257 256
258 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { 257 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
259 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) 258 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
@@ -328,8 +327,7 @@ static void c_can_setup_tx_object(struct net_device *dev, int iface,
328 change_bit(idx, &priv->tx_dir); 327 change_bit(idx, &priv->tx_dir);
329 } 328 }
330 329
331 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), arb); 330 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
332 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), arb >> 16);
333 331
334 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 332 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
335 333
@@ -391,8 +389,7 @@ static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
391 389
392 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 390 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
393 391
394 arb = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)); 392 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface));
395 arb |= priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)) << 16;
396 393
397 if (arb & IF_ARB_MSGXTD) 394 if (arb & IF_ARB_MSGXTD)
398 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; 395 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
@@ -424,12 +421,10 @@ static void c_can_setup_receive_object(struct net_device *dev, int iface,
424 struct c_can_priv *priv = netdev_priv(dev); 421 struct c_can_priv *priv = netdev_priv(dev);
425 422
426 mask |= BIT(29); 423 mask |= BIT(29);
427 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), mask); 424 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
428 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), mask >> 16);
429 425
430 id |= IF_ARB_MSGVAL; 426 id |= IF_ARB_MSGVAL;
431 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), id); 427 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id);
432 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), id >> 16);
433 428
434 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 429 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
435 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); 430 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index c56f1b1c11ca..99ad1aa576b0 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -78,6 +78,7 @@ enum reg {
78 C_CAN_INTPND2_REG, 78 C_CAN_INTPND2_REG,
79 C_CAN_MSGVAL1_REG, 79 C_CAN_MSGVAL1_REG,
80 C_CAN_MSGVAL2_REG, 80 C_CAN_MSGVAL2_REG,
81 C_CAN_FUNCTION_REG,
81}; 82};
82 83
83static const u16 reg_map_c_can[] = { 84static const u16 reg_map_c_can[] = {
@@ -129,6 +130,7 @@ static const u16 reg_map_d_can[] = {
129 [C_CAN_BRPEXT_REG] = 0x0E, 130 [C_CAN_BRPEXT_REG] = 0x0E,
130 [C_CAN_INT_REG] = 0x10, 131 [C_CAN_INT_REG] = 0x10,
131 [C_CAN_TEST_REG] = 0x14, 132 [C_CAN_TEST_REG] = 0x14,
133 [C_CAN_FUNCTION_REG] = 0x18,
132 [C_CAN_TXRQST1_REG] = 0x88, 134 [C_CAN_TXRQST1_REG] = 0x88,
133 [C_CAN_TXRQST2_REG] = 0x8A, 135 [C_CAN_TXRQST2_REG] = 0x8A,
134 [C_CAN_NEWDAT1_REG] = 0x9C, 136 [C_CAN_NEWDAT1_REG] = 0x9C,
@@ -176,8 +178,10 @@ struct c_can_priv {
176 atomic_t tx_active; 178 atomic_t tx_active;
177 unsigned long tx_dir; 179 unsigned long tx_dir;
178 int last_status; 180 int last_status;
179 u16 (*read_reg) (struct c_can_priv *priv, enum reg index); 181 u16 (*read_reg) (const struct c_can_priv *priv, enum reg index);
180 void (*write_reg) (struct c_can_priv *priv, enum reg index, u16 val); 182 void (*write_reg) (const struct c_can_priv *priv, enum reg index, u16 val);
183 u32 (*read_reg32) (const struct c_can_priv *priv, enum reg index);
184 void (*write_reg32) (const struct c_can_priv *priv, enum reg index, u32 val);
181 void __iomem *base; 185 void __iomem *base;
182 const u16 *regs; 186 const u16 *regs;
183 void *priv; /* for board-specific data */ 187 void *priv; /* for board-specific data */
diff --git a/drivers/net/can/c_can/c_can_pci.c b/drivers/net/can/c_can/c_can_pci.c
index fe5f6303b584..5d11e0e4225b 100644
--- a/drivers/net/can/c_can/c_can_pci.c
+++ b/drivers/net/can/c_can/c_can_pci.c
@@ -19,9 +19,13 @@
19 19
20#include "c_can.h" 20#include "c_can.h"
21 21
22#define PCI_DEVICE_ID_PCH_CAN 0x8818
23#define PCH_PCI_SOFT_RESET 0x01fc
24
22enum c_can_pci_reg_align { 25enum c_can_pci_reg_align {
23 C_CAN_REG_ALIGN_16, 26 C_CAN_REG_ALIGN_16,
24 C_CAN_REG_ALIGN_32, 27 C_CAN_REG_ALIGN_32,
28 C_CAN_REG_32,
25}; 29};
26 30
27struct c_can_pci_data { 31struct c_can_pci_data {
@@ -31,6 +35,10 @@ struct c_can_pci_data {
31 enum c_can_pci_reg_align reg_align; 35 enum c_can_pci_reg_align reg_align;
32 /* Set the frequency */ 36 /* Set the frequency */
33 unsigned int freq; 37 unsigned int freq;
38 /* PCI bar number */
39 int bar;
40 /* Callback for reset */
41 void (*init)(const struct c_can_priv *priv, bool enable);
34}; 42};
35 43
36/* 44/*
@@ -39,30 +47,70 @@ struct c_can_pci_data {
39 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc. 47 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
40 * Handle the same by providing a common read/write interface. 48 * Handle the same by providing a common read/write interface.
41 */ 49 */
42static u16 c_can_pci_read_reg_aligned_to_16bit(struct c_can_priv *priv, 50static u16 c_can_pci_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
43 enum reg index) 51 enum reg index)
44{ 52{
45 return readw(priv->base + priv->regs[index]); 53 return readw(priv->base + priv->regs[index]);
46} 54}
47 55
48static void c_can_pci_write_reg_aligned_to_16bit(struct c_can_priv *priv, 56static void c_can_pci_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
49 enum reg index, u16 val) 57 enum reg index, u16 val)
50{ 58{
51 writew(val, priv->base + priv->regs[index]); 59 writew(val, priv->base + priv->regs[index]);
52} 60}
53 61
54static u16 c_can_pci_read_reg_aligned_to_32bit(struct c_can_priv *priv, 62static u16 c_can_pci_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
55 enum reg index) 63 enum reg index)
56{ 64{
57 return readw(priv->base + 2 * priv->regs[index]); 65 return readw(priv->base + 2 * priv->regs[index]);
58} 66}
59 67
60static void c_can_pci_write_reg_aligned_to_32bit(struct c_can_priv *priv, 68static void c_can_pci_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
61 enum reg index, u16 val) 69 enum reg index, u16 val)
62{ 70{
63 writew(val, priv->base + 2 * priv->regs[index]); 71 writew(val, priv->base + 2 * priv->regs[index]);
64} 72}
65 73
74static u16 c_can_pci_read_reg_32bit(const struct c_can_priv *priv,
75 enum reg index)
76{
77 return (u16)ioread32(priv->base + 2 * priv->regs[index]);
78}
79
80static void c_can_pci_write_reg_32bit(const struct c_can_priv *priv,
81 enum reg index, u16 val)
82{
83 iowrite32((u32)val, priv->base + 2 * priv->regs[index]);
84}
85
86static u32 c_can_pci_read_reg32(const struct c_can_priv *priv, enum reg index)
87{
88 u32 val;
89
90 val = priv->read_reg(priv, index);
91 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
92
93 return val;
94}
95
96static void c_can_pci_write_reg32(const struct c_can_priv *priv, enum reg index,
97 u32 val)
98{
99 priv->write_reg(priv, index + 1, val >> 16);
100 priv->write_reg(priv, index, val);
101}
102
103static void c_can_pci_reset_pch(const struct c_can_priv *priv, bool enable)
104{
105 if (enable) {
106 u32 __iomem *addr = priv->base + PCH_PCI_SOFT_RESET;
107
108 /* write to sw reset register */
109 iowrite32(1, addr);
110 iowrite32(0, addr);
111 }
112}
113
66static int c_can_pci_probe(struct pci_dev *pdev, 114static int c_can_pci_probe(struct pci_dev *pdev,
67 const struct pci_device_id *ent) 115 const struct pci_device_id *ent)
68{ 116{
@@ -90,7 +138,8 @@ static int c_can_pci_probe(struct pci_dev *pdev,
90 pci_set_master(pdev); 138 pci_set_master(pdev);
91 } 139 }
92 140
93 addr = pci_iomap(pdev, 0, pci_resource_len(pdev, 0)); 141 addr = pci_iomap(pdev, c_can_pci_data->bar,
142 pci_resource_len(pdev, c_can_pci_data->bar));
94 if (!addr) { 143 if (!addr) {
95 dev_err(&pdev->dev, 144 dev_err(&pdev->dev,
96 "device has no PCI memory resources, " 145 "device has no PCI memory resources, "
@@ -147,10 +196,18 @@ static int c_can_pci_probe(struct pci_dev *pdev,
147 priv->read_reg = c_can_pci_read_reg_aligned_to_16bit; 196 priv->read_reg = c_can_pci_read_reg_aligned_to_16bit;
148 priv->write_reg = c_can_pci_write_reg_aligned_to_16bit; 197 priv->write_reg = c_can_pci_write_reg_aligned_to_16bit;
149 break; 198 break;
199 case C_CAN_REG_32:
200 priv->read_reg = c_can_pci_read_reg_32bit;
201 priv->write_reg = c_can_pci_write_reg_32bit;
202 break;
150 default: 203 default:
151 ret = -EINVAL; 204 ret = -EINVAL;
152 goto out_free_c_can; 205 goto out_free_c_can;
153 } 206 }
207 priv->read_reg32 = c_can_pci_read_reg32;
208 priv->write_reg32 = c_can_pci_write_reg32;
209
210 priv->raminit = c_can_pci_data->init;
154 211
155 ret = register_c_can_dev(dev); 212 ret = register_c_can_dev(dev);
156 if (ret) { 213 if (ret) {
@@ -198,6 +255,15 @@ static struct c_can_pci_data c_can_sta2x11= {
198 .type = BOSCH_C_CAN, 255 .type = BOSCH_C_CAN,
199 .reg_align = C_CAN_REG_ALIGN_32, 256 .reg_align = C_CAN_REG_ALIGN_32,
200 .freq = 52000000, /* 52 Mhz */ 257 .freq = 52000000, /* 52 Mhz */
258 .bar = 0,
259};
260
261static struct c_can_pci_data c_can_pch = {
262 .type = BOSCH_C_CAN,
263 .reg_align = C_CAN_REG_32,
264 .freq = 50000000, /* 50 MHz */
265 .init = c_can_pci_reset_pch,
266 .bar = 1,
201}; 267};
202 268
203#define C_CAN_ID(_vend, _dev, _driverdata) { \ 269#define C_CAN_ID(_vend, _dev, _driverdata) { \
@@ -207,6 +273,8 @@ static struct c_can_pci_data c_can_sta2x11= {
207static DEFINE_PCI_DEVICE_TABLE(c_can_pci_tbl) = { 273static DEFINE_PCI_DEVICE_TABLE(c_can_pci_tbl) = {
208 C_CAN_ID(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_CAN, 274 C_CAN_ID(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_CAN,
209 c_can_sta2x11), 275 c_can_sta2x11),
276 C_CAN_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_CAN,
277 c_can_pch),
210 {}, 278 {},
211}; 279};
212static struct pci_driver c_can_pci_driver = { 280static struct pci_driver c_can_pci_driver = {
diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
index 1df0b322d1e4..824108cd9fd5 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -40,6 +40,7 @@
40#define CAN_RAMINIT_START_MASK(i) (0x001 << (i)) 40#define CAN_RAMINIT_START_MASK(i) (0x001 << (i))
41#define CAN_RAMINIT_DONE_MASK(i) (0x100 << (i)) 41#define CAN_RAMINIT_DONE_MASK(i) (0x100 << (i))
42#define CAN_RAMINIT_ALL_MASK(i) (0x101 << (i)) 42#define CAN_RAMINIT_ALL_MASK(i) (0x101 << (i))
43#define DCAN_RAM_INIT_BIT (1 << 3)
43static DEFINE_SPINLOCK(raminit_lock); 44static DEFINE_SPINLOCK(raminit_lock);
44/* 45/*
45 * 16-bit c_can registers can be arranged differently in the memory 46 * 16-bit c_can registers can be arranged differently in the memory
@@ -47,31 +48,31 @@ static DEFINE_SPINLOCK(raminit_lock);
47 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc. 48 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
48 * Handle the same by providing a common read/write interface. 49 * Handle the same by providing a common read/write interface.
49 */ 50 */
50static u16 c_can_plat_read_reg_aligned_to_16bit(struct c_can_priv *priv, 51static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
51 enum reg index) 52 enum reg index)
52{ 53{
53 return readw(priv->base + priv->regs[index]); 54 return readw(priv->base + priv->regs[index]);
54} 55}
55 56
56static void c_can_plat_write_reg_aligned_to_16bit(struct c_can_priv *priv, 57static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
57 enum reg index, u16 val) 58 enum reg index, u16 val)
58{ 59{
59 writew(val, priv->base + priv->regs[index]); 60 writew(val, priv->base + priv->regs[index]);
60} 61}
61 62
62static u16 c_can_plat_read_reg_aligned_to_32bit(struct c_can_priv *priv, 63static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
63 enum reg index) 64 enum reg index)
64{ 65{
65 return readw(priv->base + 2 * priv->regs[index]); 66 return readw(priv->base + 2 * priv->regs[index]);
66} 67}
67 68
68static void c_can_plat_write_reg_aligned_to_32bit(struct c_can_priv *priv, 69static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
69 enum reg index, u16 val) 70 enum reg index, u16 val)
70{ 71{
71 writew(val, priv->base + 2 * priv->regs[index]); 72 writew(val, priv->base + 2 * priv->regs[index]);
72} 73}
73 74
74static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask, 75static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
75 u32 val) 76 u32 val)
76{ 77{
77 /* We look only at the bits of our instance. */ 78 /* We look only at the bits of our instance. */
@@ -80,7 +81,7 @@ static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask,
80 udelay(1); 81 udelay(1);
81} 82}
82 83
83static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable) 84static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
84{ 85{
85 u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance); 86 u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance);
86 u32 ctrl; 87 u32 ctrl;
@@ -96,18 +97,68 @@ static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
96 ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance); 97 ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
97 writel(ctrl, priv->raminit_ctrlreg); 98 writel(ctrl, priv->raminit_ctrlreg);
98 ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance); 99 ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
99 c_can_hw_raminit_wait(priv, ctrl, mask); 100 c_can_hw_raminit_wait_ti(priv, ctrl, mask);
100 101
101 if (enable) { 102 if (enable) {
102 /* Set start bit and wait for the done bit. */ 103 /* Set start bit and wait for the done bit. */
103 ctrl |= CAN_RAMINIT_START_MASK(priv->instance); 104 ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
104 writel(ctrl, priv->raminit_ctrlreg); 105 writel(ctrl, priv->raminit_ctrlreg);
105 ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance); 106 ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
106 c_can_hw_raminit_wait(priv, ctrl, mask); 107 c_can_hw_raminit_wait_ti(priv, ctrl, mask);
107 } 108 }
108 spin_unlock(&raminit_lock); 109 spin_unlock(&raminit_lock);
109} 110}
110 111
112static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
113{
114 u32 val;
115
116 val = priv->read_reg(priv, index);
117 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
118
119 return val;
120}
121
122static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
123 u32 val)
124{
125 priv->write_reg(priv, index + 1, val >> 16);
126 priv->write_reg(priv, index, val);
127}
128
129static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
130{
131 return readl(priv->base + priv->regs[index]);
132}
133
134static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
135 u32 val)
136{
137 writel(val, priv->base + priv->regs[index]);
138}
139
140static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask)
141{
142 while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask)
143 udelay(1);
144}
145
146static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
147{
148 u32 ctrl;
149
150 ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG);
151 ctrl &= ~DCAN_RAM_INIT_BIT;
152 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
153 c_can_hw_raminit_wait(priv, ctrl);
154
155 if (enable) {
156 ctrl |= DCAN_RAM_INIT_BIT;
157 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
158 c_can_hw_raminit_wait(priv, ctrl);
159 }
160}
161
111static struct platform_device_id c_can_id_table[] = { 162static struct platform_device_id c_can_id_table[] = {
112 [BOSCH_C_CAN_PLATFORM] = { 163 [BOSCH_C_CAN_PLATFORM] = {
113 .name = KBUILD_MODNAME, 164 .name = KBUILD_MODNAME,
@@ -201,11 +252,15 @@ static int c_can_plat_probe(struct platform_device *pdev)
201 case IORESOURCE_MEM_32BIT: 252 case IORESOURCE_MEM_32BIT:
202 priv->read_reg = c_can_plat_read_reg_aligned_to_32bit; 253 priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
203 priv->write_reg = c_can_plat_write_reg_aligned_to_32bit; 254 priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
255 priv->read_reg32 = c_can_plat_read_reg32;
256 priv->write_reg32 = c_can_plat_write_reg32;
204 break; 257 break;
205 case IORESOURCE_MEM_16BIT: 258 case IORESOURCE_MEM_16BIT:
206 default: 259 default:
207 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 260 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
208 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 261 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
262 priv->read_reg32 = c_can_plat_read_reg32;
263 priv->write_reg32 = c_can_plat_write_reg32;
209 break; 264 break;
210 } 265 }
211 break; 266 break;
@@ -214,6 +269,8 @@ static int c_can_plat_probe(struct platform_device *pdev)
214 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES; 269 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
215 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 270 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
216 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 271 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
272 priv->read_reg32 = d_can_plat_read_reg32;
273 priv->write_reg32 = d_can_plat_write_reg32;
217 274
218 if (pdev->dev.of_node) 275 if (pdev->dev.of_node)
219 priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can"); 276 priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can");
@@ -221,11 +278,20 @@ static int c_can_plat_probe(struct platform_device *pdev)
221 priv->instance = pdev->id; 278 priv->instance = pdev->id;
222 279
223 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 280 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
281 /* Not all D_CAN modules have a separate register for the D_CAN
282 * RAM initialization. Use default RAM init bit in D_CAN module
283 * if not specified in DT.
284 */
285 if (!res) {
286 priv->raminit = c_can_hw_raminit;
287 break;
288 }
289
224 priv->raminit_ctrlreg = devm_ioremap_resource(&pdev->dev, res); 290 priv->raminit_ctrlreg = devm_ioremap_resource(&pdev->dev, res);
225 if (IS_ERR(priv->raminit_ctrlreg) || priv->instance < 0) 291 if (IS_ERR(priv->raminit_ctrlreg) || priv->instance < 0)
226 dev_info(&pdev->dev, "control memory is not used for raminit\n"); 292 dev_info(&pdev->dev, "control memory is not used for raminit\n");
227 else 293 else
228 priv->raminit = c_can_hw_raminit; 294 priv->raminit = c_can_hw_raminit_ti;
229 break; 295 break;
230 default: 296 default:
231 ret = -EINVAL; 297 ret = -EINVAL;
diff --git a/drivers/net/can/mscan/Kconfig b/drivers/net/can/mscan/Kconfig
index f19be5269e7b..81c711719490 100644
--- a/drivers/net/can/mscan/Kconfig
+++ b/drivers/net/can/mscan/Kconfig
@@ -1,5 +1,5 @@
1config CAN_MSCAN 1config CAN_MSCAN
2 depends on PPC || M68K 2 depends on PPC
3 tristate "Support for Freescale MSCAN based chips" 3 tristate "Support for Freescale MSCAN based chips"
4 ---help--- 4 ---help---
5 The Motorola Scalable Controller Area Network (MSCAN) definition 5 The Motorola Scalable Controller Area Network (MSCAN) definition
diff --git a/drivers/net/can/rcar_can.c b/drivers/net/can/rcar_can.c
new file mode 100644
index 000000000000..5268d216ecfa
--- /dev/null
+++ b/drivers/net/can/rcar_can.c
@@ -0,0 +1,876 @@
1/* Renesas R-Car CAN device driver
2 *
3 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com>
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/errno.h>
17#include <linux/netdevice.h>
18#include <linux/platform_device.h>
19#include <linux/can/led.h>
20#include <linux/can/dev.h>
21#include <linux/clk.h>
22#include <linux/can/platform/rcar_can.h>
23
24#define RCAR_CAN_DRV_NAME "rcar_can"
25
26/* Mailbox configuration:
27 * mailbox 60 - 63 - Rx FIFO mailboxes
28 * mailbox 56 - 59 - Tx FIFO mailboxes
29 * non-FIFO mailboxes are not used
30 */
31#define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */
32#define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */
33#define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */
34#define RCAR_CAN_FIFO_DEPTH 4
35
36/* Mailbox registers structure */
37struct rcar_can_mbox_regs {
38 u32 id; /* IDE and RTR bits, SID and EID */
39 u8 stub; /* Not used */
40 u8 dlc; /* Data Length Code - bits [0..3] */
41 u8 data[8]; /* Data Bytes */
42 u8 tsh; /* Time Stamp Higher Byte */
43 u8 tsl; /* Time Stamp Lower Byte */
44};
45
46struct rcar_can_regs {
47 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */
48 u32 mkr_2_9[8]; /* Mask Registers 2-9 */
49 u32 fidcr[2]; /* FIFO Received ID Compare Register */
50 u32 mkivlr1; /* Mask Invalid Register 1 */
51 u32 mier1; /* Mailbox Interrupt Enable Register 1 */
52 u32 mkr_0_1[2]; /* Mask Registers 0-1 */
53 u32 mkivlr0; /* Mask Invalid Register 0*/
54 u32 mier0; /* Mailbox Interrupt Enable Register 0 */
55 u8 pad_440[0x3c0];
56 u8 mctl[64]; /* Message Control Registers */
57 u16 ctlr; /* Control Register */
58 u16 str; /* Status register */
59 u8 bcr[3]; /* Bit Configuration Register */
60 u8 clkr; /* Clock Select Register */
61 u8 rfcr; /* Receive FIFO Control Register */
62 u8 rfpcr; /* Receive FIFO Pointer Control Register */
63 u8 tfcr; /* Transmit FIFO Control Register */
64 u8 tfpcr; /* Transmit FIFO Pointer Control Register */
65 u8 eier; /* Error Interrupt Enable Register */
66 u8 eifr; /* Error Interrupt Factor Judge Register */
67 u8 recr; /* Receive Error Count Register */
68 u8 tecr; /* Transmit Error Count Register */
69 u8 ecsr; /* Error Code Store Register */
70 u8 cssr; /* Channel Search Support Register */
71 u8 mssr; /* Mailbox Search Status Register */
72 u8 msmr; /* Mailbox Search Mode Register */
73 u16 tsr; /* Time Stamp Register */
74 u8 afsr; /* Acceptance Filter Support Register */
75 u8 pad_857;
76 u8 tcr; /* Test Control Register */
77 u8 pad_859[7];
78 u8 ier; /* Interrupt Enable Register */
79 u8 isr; /* Interrupt Status Register */
80 u8 pad_862;
81 u8 mbsmr; /* Mailbox Search Mask Register */
82};
83
84struct rcar_can_priv {
85 struct can_priv can; /* Must be the first member! */
86 struct net_device *ndev;
87 struct napi_struct napi;
88 struct rcar_can_regs __iomem *regs;
89 struct clk *clk;
90 u8 tx_dlc[RCAR_CAN_FIFO_DEPTH];
91 u32 tx_head;
92 u32 tx_tail;
93 u8 clock_select;
94 u8 ier;
95};
96
97static const struct can_bittiming_const rcar_can_bittiming_const = {
98 .name = RCAR_CAN_DRV_NAME,
99 .tseg1_min = 4,
100 .tseg1_max = 16,
101 .tseg2_min = 2,
102 .tseg2_max = 8,
103 .sjw_max = 4,
104 .brp_min = 1,
105 .brp_max = 1024,
106 .brp_inc = 1,
107};
108
109/* Control Register bits */
110#define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */
111#define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */
112 /* at bus-off entry */
113#define RCAR_CAN_CTLR_SLPM (1 << 10)
114#define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */
115#define RCAR_CAN_CTLR_CANM_HALT (1 << 9)
116#define RCAR_CAN_CTLR_CANM_RESET (1 << 8)
117#define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8)
118#define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */
119#define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */
120#define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */
121#define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */
122
123/* Status Register bits */
124#define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */
125
126/* FIFO Received ID Compare Registers 0 and 1 bits */
127#define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */
128#define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */
129
130/* Receive FIFO Control Register bits */
131#define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */
132#define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */
133
134/* Transmit FIFO Control Register bits */
135#define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */
136 /* Number Status Bits */
137#define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */
138 /* Message Number Status Bits */
139#define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */
140
141#define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */
142 /* for Rx mailboxes 0-31 */
143#define RCAR_CAN_N_RX_MKREGS2 8
144
145/* Bit Configuration Register settings */
146#define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20)
147#define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)
148#define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)
149#define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07)
150
151/* Mailbox and Mask Registers bits */
152#define RCAR_CAN_IDE (1 << 31)
153#define RCAR_CAN_RTR (1 << 30)
154#define RCAR_CAN_SID_SHIFT 18
155
156/* Mailbox Interrupt Enable Register 1 bits */
157#define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */
158#define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */
159
160/* Interrupt Enable Register bits */
161#define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */
162#define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */
163 /* Enable Bit */
164#define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */
165 /* Enable Bit */
166/* Interrupt Status Register bits */
167#define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */
168#define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */
169 /* Status Bit */
170#define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */
171 /* Status Bit */
172
173/* Error Interrupt Enable Register bits */
174#define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */
175#define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */
176 /* Interrupt Enable */
177#define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */
178#define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */
179#define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */
180#define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */
181#define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */
182#define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */
183
184/* Error Interrupt Factor Judge Register bits */
185#define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */
186#define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */
187 /* Detect Flag */
188#define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */
189#define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */
190#define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */
191#define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */
192#define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */
193#define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */
194
195/* Error Code Store Register bits */
196#define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */
197#define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */
198#define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */
199#define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */
200#define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */
201#define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */
202#define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */
203#define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */
204
205#define RCAR_CAN_NAPI_WEIGHT 4
206#define MAX_STR_READS 0x100
207
208static void tx_failure_cleanup(struct net_device *ndev)
209{
210 int i;
211
212 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++)
213 can_free_echo_skb(ndev, i);
214}
215
216static void rcar_can_error(struct net_device *ndev)
217{
218 struct rcar_can_priv *priv = netdev_priv(ndev);
219 struct net_device_stats *stats = &ndev->stats;
220 struct can_frame *cf;
221 struct sk_buff *skb;
222 u8 eifr, txerr = 0, rxerr = 0;
223
224 /* Propagate the error condition to the CAN stack */
225 skb = alloc_can_err_skb(ndev, &cf);
226
227 eifr = readb(&priv->regs->eifr);
228 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) {
229 txerr = readb(&priv->regs->tecr);
230 rxerr = readb(&priv->regs->recr);
231 if (skb) {
232 cf->can_id |= CAN_ERR_CRTL;
233 cf->data[6] = txerr;
234 cf->data[7] = rxerr;
235 }
236 }
237 if (eifr & RCAR_CAN_EIFR_BEIF) {
238 int rx_errors = 0, tx_errors = 0;
239 u8 ecsr;
240
241 netdev_dbg(priv->ndev, "Bus error interrupt:\n");
242 if (skb) {
243 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
244 cf->data[2] = CAN_ERR_PROT_UNSPEC;
245 }
246 ecsr = readb(&priv->regs->ecsr);
247 if (ecsr & RCAR_CAN_ECSR_ADEF) {
248 netdev_dbg(priv->ndev, "ACK Delimiter Error\n");
249 tx_errors++;
250 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr);
251 if (skb)
252 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
253 }
254 if (ecsr & RCAR_CAN_ECSR_BE0F) {
255 netdev_dbg(priv->ndev, "Bit Error (dominant)\n");
256 tx_errors++;
257 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr);
258 if (skb)
259 cf->data[2] |= CAN_ERR_PROT_BIT0;
260 }
261 if (ecsr & RCAR_CAN_ECSR_BE1F) {
262 netdev_dbg(priv->ndev, "Bit Error (recessive)\n");
263 tx_errors++;
264 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr);
265 if (skb)
266 cf->data[2] |= CAN_ERR_PROT_BIT1;
267 }
268 if (ecsr & RCAR_CAN_ECSR_CEF) {
269 netdev_dbg(priv->ndev, "CRC Error\n");
270 rx_errors++;
271 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr);
272 if (skb)
273 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
274 }
275 if (ecsr & RCAR_CAN_ECSR_AEF) {
276 netdev_dbg(priv->ndev, "ACK Error\n");
277 tx_errors++;
278 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr);
279 if (skb) {
280 cf->can_id |= CAN_ERR_ACK;
281 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
282 }
283 }
284 if (ecsr & RCAR_CAN_ECSR_FEF) {
285 netdev_dbg(priv->ndev, "Form Error\n");
286 rx_errors++;
287 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr);
288 if (skb)
289 cf->data[2] |= CAN_ERR_PROT_FORM;
290 }
291 if (ecsr & RCAR_CAN_ECSR_SEF) {
292 netdev_dbg(priv->ndev, "Stuff Error\n");
293 rx_errors++;
294 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr);
295 if (skb)
296 cf->data[2] |= CAN_ERR_PROT_STUFF;
297 }
298
299 priv->can.can_stats.bus_error++;
300 ndev->stats.rx_errors += rx_errors;
301 ndev->stats.tx_errors += tx_errors;
302 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr);
303 }
304 if (eifr & RCAR_CAN_EIFR_EWIF) {
305 netdev_dbg(priv->ndev, "Error warning interrupt\n");
306 priv->can.state = CAN_STATE_ERROR_WARNING;
307 priv->can.can_stats.error_warning++;
308 /* Clear interrupt condition */
309 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr);
310 if (skb)
311 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
312 CAN_ERR_CRTL_RX_WARNING;
313 }
314 if (eifr & RCAR_CAN_EIFR_EPIF) {
315 netdev_dbg(priv->ndev, "Error passive interrupt\n");
316 priv->can.state = CAN_STATE_ERROR_PASSIVE;
317 priv->can.can_stats.error_passive++;
318 /* Clear interrupt condition */
319 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr);
320 if (skb)
321 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
322 CAN_ERR_CRTL_RX_PASSIVE;
323 }
324 if (eifr & RCAR_CAN_EIFR_BOEIF) {
325 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n");
326 tx_failure_cleanup(ndev);
327 priv->ier = RCAR_CAN_IER_ERSIE;
328 writeb(priv->ier, &priv->regs->ier);
329 priv->can.state = CAN_STATE_BUS_OFF;
330 /* Clear interrupt condition */
331 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr);
332 can_bus_off(ndev);
333 if (skb)
334 cf->can_id |= CAN_ERR_BUSOFF;
335 }
336 if (eifr & RCAR_CAN_EIFR_ORIF) {
337 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n");
338 ndev->stats.rx_over_errors++;
339 ndev->stats.rx_errors++;
340 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr);
341 if (skb) {
342 cf->can_id |= CAN_ERR_CRTL;
343 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
344 }
345 }
346 if (eifr & RCAR_CAN_EIFR_OLIF) {
347 netdev_dbg(priv->ndev,
348 "Overload Frame Transmission error interrupt\n");
349 ndev->stats.rx_over_errors++;
350 ndev->stats.rx_errors++;
351 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr);
352 if (skb) {
353 cf->can_id |= CAN_ERR_PROT;
354 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
355 }
356 }
357
358 if (skb) {
359 stats->rx_packets++;
360 stats->rx_bytes += cf->can_dlc;
361 netif_rx(skb);
362 }
363}
364
365static void rcar_can_tx_done(struct net_device *ndev)
366{
367 struct rcar_can_priv *priv = netdev_priv(ndev);
368 struct net_device_stats *stats = &ndev->stats;
369 u8 isr;
370
371 while (1) {
372 u8 unsent = readb(&priv->regs->tfcr);
373
374 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >>
375 RCAR_CAN_TFCR_TFUST_SHIFT;
376 if (priv->tx_head - priv->tx_tail <= unsent)
377 break;
378 stats->tx_packets++;
379 stats->tx_bytes += priv->tx_dlc[priv->tx_tail %
380 RCAR_CAN_FIFO_DEPTH];
381 priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0;
382 can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH);
383 priv->tx_tail++;
384 netif_wake_queue(ndev);
385 }
386 /* Clear interrupt */
387 isr = readb(&priv->regs->isr);
388 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr);
389 can_led_event(ndev, CAN_LED_EVENT_TX);
390}
391
392static irqreturn_t rcar_can_interrupt(int irq, void *dev_id)
393{
394 struct net_device *ndev = dev_id;
395 struct rcar_can_priv *priv = netdev_priv(ndev);
396 u8 isr;
397
398 isr = readb(&priv->regs->isr);
399 if (!(isr & priv->ier))
400 return IRQ_NONE;
401
402 if (isr & RCAR_CAN_ISR_ERSF)
403 rcar_can_error(ndev);
404
405 if (isr & RCAR_CAN_ISR_TXFF)
406 rcar_can_tx_done(ndev);
407
408 if (isr & RCAR_CAN_ISR_RXFF) {
409 if (napi_schedule_prep(&priv->napi)) {
410 /* Disable Rx FIFO interrupts */
411 priv->ier &= ~RCAR_CAN_IER_RXFIE;
412 writeb(priv->ier, &priv->regs->ier);
413 __napi_schedule(&priv->napi);
414 }
415 }
416
417 return IRQ_HANDLED;
418}
419
420static void rcar_can_set_bittiming(struct net_device *dev)
421{
422 struct rcar_can_priv *priv = netdev_priv(dev);
423 struct can_bittiming *bt = &priv->can.bittiming;
424 u32 bcr;
425
426 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) |
427 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) |
428 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1);
429 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
430 * All the registers are big-endian but they get byte-swapped on 32-bit
431 * read/write (but not on 8-bit, contrary to the manuals)...
432 */
433 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr);
434}
435
436static void rcar_can_start(struct net_device *ndev)
437{
438 struct rcar_can_priv *priv = netdev_priv(ndev);
439 u16 ctlr;
440 int i;
441
442 /* Set controller to known mode:
443 * - FIFO mailbox mode
444 * - accept all messages
445 * - overrun mode
446 * CAN is in sleep mode after MCU hardware or software reset.
447 */
448 ctlr = readw(&priv->regs->ctlr);
449 ctlr &= ~RCAR_CAN_CTLR_SLPM;
450 writew(ctlr, &priv->regs->ctlr);
451 /* Go to reset mode */
452 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;
453 writew(ctlr, &priv->regs->ctlr);
454 for (i = 0; i < MAX_STR_READS; i++) {
455 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)
456 break;
457 }
458 rcar_can_set_bittiming(ndev);
459 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */
460 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */
461 /* at bus-off */
462 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */
463 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */
464 writew(ctlr, &priv->regs->ctlr);
465
466 /* Accept all SID and EID */
467 writel(0, &priv->regs->mkr_2_9[6]);
468 writel(0, &priv->regs->mkr_2_9[7]);
469 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */
470 writel(0, &priv->regs->mkivlr1);
471 /* Accept all frames */
472 writel(0, &priv->regs->fidcr[0]);
473 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]);
474 /* Enable and configure FIFO mailbox interrupts */
475 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1);
476
477 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE |
478 RCAR_CAN_IER_TXFIE;
479 writeb(priv->ier, &priv->regs->ier);
480
481 /* Accumulate error codes */
482 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr);
483 /* Enable error interrupts */
484 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE |
485 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ?
486 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE |
487 RCAR_CAN_EIER_OLIE, &priv->regs->eier);
488 priv->can.state = CAN_STATE_ERROR_ACTIVE;
489
490 /* Go to operation mode */
491 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr);
492 for (i = 0; i < MAX_STR_READS; i++) {
493 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST))
494 break;
495 }
496 /* Enable Rx and Tx FIFO */
497 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr);
498 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr);
499}
500
501static int rcar_can_open(struct net_device *ndev)
502{
503 struct rcar_can_priv *priv = netdev_priv(ndev);
504 int err;
505
506 err = clk_prepare_enable(priv->clk);
507 if (err) {
508 netdev_err(ndev, "clk_prepare_enable() failed, error %d\n",
509 err);
510 goto out;
511 }
512 err = open_candev(ndev);
513 if (err) {
514 netdev_err(ndev, "open_candev() failed, error %d\n", err);
515 goto out_clock;
516 }
517 napi_enable(&priv->napi);
518 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev);
519 if (err) {
520 netdev_err(ndev, "error requesting interrupt %x\n", ndev->irq);
521 goto out_close;
522 }
523 can_led_event(ndev, CAN_LED_EVENT_OPEN);
524 rcar_can_start(ndev);
525 netif_start_queue(ndev);
526 return 0;
527out_close:
528 napi_disable(&priv->napi);
529 close_candev(ndev);
530out_clock:
531 clk_disable_unprepare(priv->clk);
532out:
533 return err;
534}
535
536static void rcar_can_stop(struct net_device *ndev)
537{
538 struct rcar_can_priv *priv = netdev_priv(ndev);
539 u16 ctlr;
540 int i;
541
542 /* Go to (force) reset mode */
543 ctlr = readw(&priv->regs->ctlr);
544 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;
545 writew(ctlr, &priv->regs->ctlr);
546 for (i = 0; i < MAX_STR_READS; i++) {
547 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)
548 break;
549 }
550 writel(0, &priv->regs->mier0);
551 writel(0, &priv->regs->mier1);
552 writeb(0, &priv->regs->ier);
553 writeb(0, &priv->regs->eier);
554 /* Go to sleep mode */
555 ctlr |= RCAR_CAN_CTLR_SLPM;
556 writew(ctlr, &priv->regs->ctlr);
557 priv->can.state = CAN_STATE_STOPPED;
558}
559
560static int rcar_can_close(struct net_device *ndev)
561{
562 struct rcar_can_priv *priv = netdev_priv(ndev);
563
564 netif_stop_queue(ndev);
565 rcar_can_stop(ndev);
566 free_irq(ndev->irq, ndev);
567 napi_disable(&priv->napi);
568 clk_disable_unprepare(priv->clk);
569 close_candev(ndev);
570 can_led_event(ndev, CAN_LED_EVENT_STOP);
571 return 0;
572}
573
574static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb,
575 struct net_device *ndev)
576{
577 struct rcar_can_priv *priv = netdev_priv(ndev);
578 struct can_frame *cf = (struct can_frame *)skb->data;
579 u32 data, i;
580
581 if (can_dropped_invalid_skb(ndev, skb))
582 return NETDEV_TX_OK;
583
584 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
585 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE;
586 else /* Standard frame format */
587 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT;
588
589 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */
590 data |= RCAR_CAN_RTR;
591 } else {
592 for (i = 0; i < cf->can_dlc; i++)
593 writeb(cf->data[i],
594 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]);
595 }
596
597 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id);
598
599 writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc);
600
601 priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc;
602 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH);
603 priv->tx_head++;
604 /* Start Tx: write 0xff to the TFPCR register to increment
605 * the CPU-side pointer for the transmit FIFO to the next
606 * mailbox location
607 */
608 writeb(0xff, &priv->regs->tfpcr);
609 /* Stop the queue if we've filled all FIFO entries */
610 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH)
611 netif_stop_queue(ndev);
612
613 return NETDEV_TX_OK;
614}
615
616static const struct net_device_ops rcar_can_netdev_ops = {
617 .ndo_open = rcar_can_open,
618 .ndo_stop = rcar_can_close,
619 .ndo_start_xmit = rcar_can_start_xmit,
620};
621
622static void rcar_can_rx_pkt(struct rcar_can_priv *priv)
623{
624 struct net_device_stats *stats = &priv->ndev->stats;
625 struct can_frame *cf;
626 struct sk_buff *skb;
627 u32 data;
628 u8 dlc;
629
630 skb = alloc_can_skb(priv->ndev, &cf);
631 if (!skb) {
632 stats->rx_dropped++;
633 return;
634 }
635
636 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id);
637 if (data & RCAR_CAN_IDE)
638 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
639 else
640 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK;
641
642 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc);
643 cf->can_dlc = get_can_dlc(dlc);
644 if (data & RCAR_CAN_RTR) {
645 cf->can_id |= CAN_RTR_FLAG;
646 } else {
647 for (dlc = 0; dlc < cf->can_dlc; dlc++)
648 cf->data[dlc] =
649 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]);
650 }
651
652 can_led_event(priv->ndev, CAN_LED_EVENT_RX);
653
654 stats->rx_bytes += cf->can_dlc;
655 stats->rx_packets++;
656 netif_receive_skb(skb);
657}
658
659static int rcar_can_rx_poll(struct napi_struct *napi, int quota)
660{
661 struct rcar_can_priv *priv = container_of(napi,
662 struct rcar_can_priv, napi);
663 int num_pkts;
664
665 for (num_pkts = 0; num_pkts < quota; num_pkts++) {
666 u8 rfcr, isr;
667
668 isr = readb(&priv->regs->isr);
669 /* Clear interrupt bit */
670 if (isr & RCAR_CAN_ISR_RXFF)
671 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr);
672 rfcr = readb(&priv->regs->rfcr);
673 if (rfcr & RCAR_CAN_RFCR_RFEST)
674 break;
675 rcar_can_rx_pkt(priv);
676 /* Write 0xff to the RFPCR register to increment
677 * the CPU-side pointer for the receive FIFO
678 * to the next mailbox location
679 */
680 writeb(0xff, &priv->regs->rfpcr);
681 }
682 /* All packets processed */
683 if (num_pkts < quota) {
684 napi_complete(napi);
685 priv->ier |= RCAR_CAN_IER_RXFIE;
686 writeb(priv->ier, &priv->regs->ier);
687 }
688 return num_pkts;
689}
690
691static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
692{
693 switch (mode) {
694 case CAN_MODE_START:
695 rcar_can_start(ndev);
696 netif_wake_queue(ndev);
697 return 0;
698 default:
699 return -EOPNOTSUPP;
700 }
701}
702
703static int rcar_can_get_berr_counter(const struct net_device *dev,
704 struct can_berr_counter *bec)
705{
706 struct rcar_can_priv *priv = netdev_priv(dev);
707 int err;
708
709 err = clk_prepare_enable(priv->clk);
710 if (err)
711 return err;
712 bec->txerr = readb(&priv->regs->tecr);
713 bec->rxerr = readb(&priv->regs->recr);
714 clk_disable_unprepare(priv->clk);
715 return 0;
716}
717
718static int rcar_can_probe(struct platform_device *pdev)
719{
720 struct rcar_can_platform_data *pdata;
721 struct rcar_can_priv *priv;
722 struct net_device *ndev;
723 struct resource *mem;
724 void __iomem *addr;
725 int err = -ENODEV;
726 int irq;
727
728 pdata = dev_get_platdata(&pdev->dev);
729 if (!pdata) {
730 dev_err(&pdev->dev, "No platform data provided!\n");
731 goto fail;
732 }
733
734 irq = platform_get_irq(pdev, 0);
735 if (!irq) {
736 dev_err(&pdev->dev, "No IRQ resource\n");
737 goto fail;
738 }
739
740 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
741 addr = devm_ioremap_resource(&pdev->dev, mem);
742 if (IS_ERR(addr)) {
743 err = PTR_ERR(addr);
744 goto fail;
745 }
746
747 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH);
748 if (!ndev) {
749 dev_err(&pdev->dev, "alloc_candev() failed\n");
750 err = -ENOMEM;
751 goto fail;
752 }
753
754 priv = netdev_priv(ndev);
755
756 priv->clk = devm_clk_get(&pdev->dev, NULL);
757 if (IS_ERR(priv->clk)) {
758 err = PTR_ERR(priv->clk);
759 dev_err(&pdev->dev, "cannot get clock: %d\n", err);
760 goto fail_clk;
761 }
762
763 ndev->netdev_ops = &rcar_can_netdev_ops;
764 ndev->irq = irq;
765 ndev->flags |= IFF_ECHO;
766 priv->ndev = ndev;
767 priv->regs = addr;
768 priv->clock_select = pdata->clock_select;
769 priv->can.clock.freq = clk_get_rate(priv->clk);
770 priv->can.bittiming_const = &rcar_can_bittiming_const;
771 priv->can.do_set_mode = rcar_can_do_set_mode;
772 priv->can.do_get_berr_counter = rcar_can_get_berr_counter;
773 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
774 platform_set_drvdata(pdev, ndev);
775 SET_NETDEV_DEV(ndev, &pdev->dev);
776
777 netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll,
778 RCAR_CAN_NAPI_WEIGHT);
779 err = register_candev(ndev);
780 if (err) {
781 dev_err(&pdev->dev, "register_candev() failed, error %d\n",
782 err);
783 goto fail_candev;
784 }
785
786 devm_can_led_init(ndev);
787
788 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
789 priv->regs, ndev->irq);
790
791 return 0;
792fail_candev:
793 netif_napi_del(&priv->napi);
794fail_clk:
795 free_candev(ndev);
796fail:
797 return err;
798}
799
800static int rcar_can_remove(struct platform_device *pdev)
801{
802 struct net_device *ndev = platform_get_drvdata(pdev);
803 struct rcar_can_priv *priv = netdev_priv(ndev);
804
805 unregister_candev(ndev);
806 netif_napi_del(&priv->napi);
807 free_candev(ndev);
808 return 0;
809}
810
811static int __maybe_unused rcar_can_suspend(struct device *dev)
812{
813 struct net_device *ndev = dev_get_drvdata(dev);
814 struct rcar_can_priv *priv = netdev_priv(ndev);
815 u16 ctlr;
816
817 if (netif_running(ndev)) {
818 netif_stop_queue(ndev);
819 netif_device_detach(ndev);
820 }
821 ctlr = readw(&priv->regs->ctlr);
822 ctlr |= RCAR_CAN_CTLR_CANM_HALT;
823 writew(ctlr, &priv->regs->ctlr);
824 ctlr |= RCAR_CAN_CTLR_SLPM;
825 writew(ctlr, &priv->regs->ctlr);
826 priv->can.state = CAN_STATE_SLEEPING;
827
828 clk_disable(priv->clk);
829 return 0;
830}
831
832static int __maybe_unused rcar_can_resume(struct device *dev)
833{
834 struct net_device *ndev = dev_get_drvdata(dev);
835 struct rcar_can_priv *priv = netdev_priv(ndev);
836 u16 ctlr;
837 int err;
838
839 err = clk_enable(priv->clk);
840 if (err) {
841 netdev_err(ndev, "clk_enable() failed, error %d\n", err);
842 return err;
843 }
844
845 ctlr = readw(&priv->regs->ctlr);
846 ctlr &= ~RCAR_CAN_CTLR_SLPM;
847 writew(ctlr, &priv->regs->ctlr);
848 ctlr &= ~RCAR_CAN_CTLR_CANM;
849 writew(ctlr, &priv->regs->ctlr);
850 priv->can.state = CAN_STATE_ERROR_ACTIVE;
851
852 if (netif_running(ndev)) {
853 netif_device_attach(ndev);
854 netif_start_queue(ndev);
855 }
856 return 0;
857}
858
859static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume);
860
861static struct platform_driver rcar_can_driver = {
862 .driver = {
863 .name = RCAR_CAN_DRV_NAME,
864 .owner = THIS_MODULE,
865 .pm = &rcar_can_pm_ops,
866 },
867 .probe = rcar_can_probe,
868 .remove = rcar_can_remove,
869};
870
871module_platform_driver(rcar_can_driver);
872
873MODULE_AUTHOR("Cogent Embedded, Inc.");
874MODULE_LICENSE("GPL");
875MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC");
876MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME);
diff --git a/drivers/net/can/softing/softing_main.c b/drivers/net/can/softing/softing_main.c
index 7d8c8f3672dd..bacd236ce306 100644
--- a/drivers/net/can/softing/softing_main.c
+++ b/drivers/net/can/softing/softing_main.c
@@ -556,15 +556,6 @@ failed:
556/* 556/*
557 * netdev sysfs 557 * netdev sysfs
558 */ 558 */
559static ssize_t show_channel(struct device *dev, struct device_attribute *attr,
560 char *buf)
561{
562 struct net_device *ndev = to_net_dev(dev);
563 struct softing_priv *priv = netdev2softing(ndev);
564
565 return sprintf(buf, "%i\n", priv->index);
566}
567
568static ssize_t show_chip(struct device *dev, struct device_attribute *attr, 559static ssize_t show_chip(struct device *dev, struct device_attribute *attr,
569 char *buf) 560 char *buf)
570{ 561{
@@ -609,12 +600,10 @@ static ssize_t store_output(struct device *dev, struct device_attribute *attr,
609 return count; 600 return count;
610} 601}
611 602
612static const DEVICE_ATTR(channel, S_IRUGO, show_channel, NULL);
613static const DEVICE_ATTR(chip, S_IRUGO, show_chip, NULL); 603static const DEVICE_ATTR(chip, S_IRUGO, show_chip, NULL);
614static const DEVICE_ATTR(output, S_IRUGO | S_IWUSR, show_output, store_output); 604static const DEVICE_ATTR(output, S_IRUGO | S_IWUSR, show_output, store_output);
615 605
616static const struct attribute *const netdev_sysfs_attrs[] = { 606static const struct attribute *const netdev_sysfs_attrs[] = {
617 &dev_attr_channel.attr,
618 &dev_attr_chip.attr, 607 &dev_attr_chip.attr,
619 &dev_attr_output.attr, 608 &dev_attr_output.attr,
620 NULL, 609 NULL,
@@ -679,17 +668,20 @@ static int softing_netdev_register(struct net_device *netdev)
679{ 668{
680 int ret; 669 int ret;
681 670
682 netdev->sysfs_groups[0] = &netdev_sysfs_group;
683 ret = register_candev(netdev); 671 ret = register_candev(netdev);
684 if (ret) { 672 if (ret) {
685 dev_alert(&netdev->dev, "register failed\n"); 673 dev_alert(&netdev->dev, "register failed\n");
686 return ret; 674 return ret;
687 } 675 }
676 if (sysfs_create_group(&netdev->dev.kobj, &netdev_sysfs_group) < 0)
677 netdev_alert(netdev, "sysfs group failed\n");
678
688 return 0; 679 return 0;
689} 680}
690 681
691static void softing_netdev_cleanup(struct net_device *netdev) 682static void softing_netdev_cleanup(struct net_device *netdev)
692{ 683{
684 sysfs_remove_group(&netdev->dev.kobj, &netdev_sysfs_group);
693 unregister_candev(netdev); 685 unregister_candev(netdev);
694 free_candev(netdev); 686 free_candev(netdev);
695} 687}
@@ -721,8 +713,6 @@ DEV_ATTR_RO(firmware_version, id.fw_version);
721DEV_ATTR_RO_STR(hardware, pdat->name); 713DEV_ATTR_RO_STR(hardware, pdat->name);
722DEV_ATTR_RO(hardware_version, id.hw_version); 714DEV_ATTR_RO(hardware_version, id.hw_version);
723DEV_ATTR_RO(license, id.license); 715DEV_ATTR_RO(license, id.license);
724DEV_ATTR_RO(frequency, id.freq);
725DEV_ATTR_RO(txpending, tx.pending);
726 716
727static struct attribute *softing_pdev_attrs[] = { 717static struct attribute *softing_pdev_attrs[] = {
728 &dev_attr_serial.attr, 718 &dev_attr_serial.attr,
@@ -731,8 +721,6 @@ static struct attribute *softing_pdev_attrs[] = {
731 &dev_attr_hardware.attr, 721 &dev_attr_hardware.attr,
732 &dev_attr_hardware_version.attr, 722 &dev_attr_hardware_version.attr,
733 &dev_attr_license.attr, 723 &dev_attr_license.attr,
734 &dev_attr_frequency.attr,
735 &dev_attr_txpending.attr,
736 NULL, 724 NULL,
737}; 725};
738 726
diff --git a/drivers/net/can/spi/Kconfig b/drivers/net/can/spi/Kconfig
new file mode 100644
index 000000000000..148cae5871a6
--- /dev/null
+++ b/drivers/net/can/spi/Kconfig
@@ -0,0 +1,10 @@
1menu "CAN SPI interfaces"
2 depends on SPI
3
4config CAN_MCP251X
5 tristate "Microchip MCP251x SPI CAN controllers"
6 depends on HAS_DMA
7 ---help---
8 Driver for the Microchip MCP251x SPI CAN controllers.
9
10endmenu
diff --git a/drivers/net/can/spi/Makefile b/drivers/net/can/spi/Makefile
new file mode 100644
index 000000000000..90bcacffbc65
--- /dev/null
+++ b/drivers/net/can/spi/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the Linux Controller Area Network SPI drivers.
3#
4
5
6obj-$(CONFIG_CAN_MCP251X) += mcp251x.o
7
8ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/mcp251x.c b/drivers/net/can/spi/mcp251x.c
index 28c11f815245..5df239e68812 100644
--- a/drivers/net/can/mcp251x.c
+++ b/drivers/net/can/spi/mcp251x.c
@@ -214,6 +214,8 @@
214 214
215#define TX_ECHO_SKB_MAX 1 215#define TX_ECHO_SKB_MAX 1
216 216
217#define MCP251X_OST_DELAY_MS (5)
218
217#define DEVICE_NAME "mcp251x" 219#define DEVICE_NAME "mcp251x"
218 220
219static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */ 221static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
@@ -624,50 +626,45 @@ static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
624static int mcp251x_hw_reset(struct spi_device *spi) 626static int mcp251x_hw_reset(struct spi_device *spi)
625{ 627{
626 struct mcp251x_priv *priv = spi_get_drvdata(spi); 628 struct mcp251x_priv *priv = spi_get_drvdata(spi);
629 u8 reg;
627 int ret; 630 int ret;
628 unsigned long timeout; 631
632 /* Wait for oscillator startup timer after power up */
633 mdelay(MCP251X_OST_DELAY_MS);
629 634
630 priv->spi_tx_buf[0] = INSTRUCTION_RESET; 635 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
631 ret = spi_write(spi, priv->spi_tx_buf, 1); 636 ret = mcp251x_spi_trans(spi, 1);
632 if (ret) { 637 if (ret)
633 dev_err(&spi->dev, "reset failed: ret = %d\n", ret); 638 return ret;
634 return -EIO; 639
635 } 640 /* Wait for oscillator startup timer after reset */
641 mdelay(MCP251X_OST_DELAY_MS);
642
643 reg = mcp251x_read_reg(spi, CANSTAT);
644 if ((reg & CANCTRL_REQOP_MASK) != CANCTRL_REQOP_CONF)
645 return -ENODEV;
636 646
637 /* Wait for reset to finish */
638 timeout = jiffies + HZ;
639 mdelay(10);
640 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
641 != CANCTRL_REQOP_CONF) {
642 schedule();
643 if (time_after(jiffies, timeout)) {
644 dev_err(&spi->dev, "MCP251x didn't"
645 " enter in conf mode after reset\n");
646 return -EBUSY;
647 }
648 }
649 return 0; 647 return 0;
650} 648}
651 649
652static int mcp251x_hw_probe(struct spi_device *spi) 650static int mcp251x_hw_probe(struct spi_device *spi)
653{ 651{
654 int st1, st2; 652 u8 ctrl;
653 int ret;
655 654
656 mcp251x_hw_reset(spi); 655 ret = mcp251x_hw_reset(spi);
656 if (ret)
657 return ret;
657 658
658 /* 659 ctrl = mcp251x_read_reg(spi, CANCTRL);
659 * Please note that these are "magic values" based on after 660
660 * reset defaults taken from data sheet which allows us to see 661 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
661 * if we really have a chip on the bus (we avoid common all
662 * zeroes or all ones situations)
663 */
664 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
665 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
666 662
667 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2); 663 /* Check for power up default value */
664 if ((ctrl & 0x17) != 0x07)
665 return -ENODEV;
668 666
669 /* Check for power up default values */ 667 return 0;
670 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
671} 668}
672 669
673static int mcp251x_power_enable(struct regulator *reg, int enable) 670static int mcp251x_power_enable(struct regulator *reg, int enable)
@@ -776,7 +773,6 @@ static void mcp251x_restart_work_handler(struct work_struct *ws)
776 773
777 mutex_lock(&priv->mcp_lock); 774 mutex_lock(&priv->mcp_lock);
778 if (priv->after_suspend) { 775 if (priv->after_suspend) {
779 mdelay(10);
780 mcp251x_hw_reset(spi); 776 mcp251x_hw_reset(spi);
781 mcp251x_setup(net, priv, spi); 777 mcp251x_setup(net, priv, spi);
782 if (priv->after_suspend & AFTER_SUSPEND_RESTART) { 778 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
@@ -955,7 +951,7 @@ static int mcp251x_open(struct net_device *net)
955 priv->tx_len = 0; 951 priv->tx_len = 0;
956 952
957 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, 953 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
958 flags, DEVICE_NAME, priv); 954 flags | IRQF_ONESHOT, DEVICE_NAME, priv);
959 if (ret) { 955 if (ret) {
960 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 956 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
961 mcp251x_power_enable(priv->transceiver, 0); 957 mcp251x_power_enable(priv->transceiver, 0);
@@ -1032,8 +1028,8 @@ static int mcp251x_can_probe(struct spi_device *spi)
1032 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev); 1028 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1033 struct net_device *net; 1029 struct net_device *net;
1034 struct mcp251x_priv *priv; 1030 struct mcp251x_priv *priv;
1035 int freq, ret = -ENODEV;
1036 struct clk *clk; 1031 struct clk *clk;
1032 int freq, ret;
1037 1033
1038 clk = devm_clk_get(&spi->dev, NULL); 1034 clk = devm_clk_get(&spi->dev, NULL);
1039 if (IS_ERR(clk)) { 1035 if (IS_ERR(clk)) {
@@ -1076,6 +1072,18 @@ static int mcp251x_can_probe(struct spi_device *spi)
1076 priv->net = net; 1072 priv->net = net;
1077 priv->clk = clk; 1073 priv->clk = clk;
1078 1074
1075 spi_set_drvdata(spi, priv);
1076
1077 /* Configure the SPI bus */
1078 spi->bits_per_word = 8;
1079 if (mcp251x_is_2510(spi))
1080 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1081 else
1082 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1083 ret = spi_setup(spi);
1084 if (ret)
1085 goto out_clk;
1086
1079 priv->power = devm_regulator_get(&spi->dev, "vdd"); 1087 priv->power = devm_regulator_get(&spi->dev, "vdd");
1080 priv->transceiver = devm_regulator_get(&spi->dev, "xceiver"); 1088 priv->transceiver = devm_regulator_get(&spi->dev, "xceiver");
1081 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 1089 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
@@ -1088,8 +1096,6 @@ static int mcp251x_can_probe(struct spi_device *spi)
1088 if (ret) 1096 if (ret)
1089 goto out_clk; 1097 goto out_clk;
1090 1098
1091 spi_set_drvdata(spi, priv);
1092
1093 priv->spi = spi; 1099 priv->spi = spi;
1094 mutex_init(&priv->mcp_lock); 1100 mutex_init(&priv->mcp_lock);
1095 1101
@@ -1134,20 +1140,11 @@ static int mcp251x_can_probe(struct spi_device *spi)
1134 1140
1135 SET_NETDEV_DEV(net, &spi->dev); 1141 SET_NETDEV_DEV(net, &spi->dev);
1136 1142
1137 /* Configure the SPI bus */
1138 spi->mode = spi->mode ? : SPI_MODE_0;
1139 if (mcp251x_is_2510(spi))
1140 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1141 else
1142 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1143 spi->bits_per_word = 8;
1144 spi_setup(spi);
1145
1146 /* Here is OK to not lock the MCP, no one knows about it yet */ 1143 /* Here is OK to not lock the MCP, no one knows about it yet */
1147 if (!mcp251x_hw_probe(spi)) { 1144 ret = mcp251x_hw_probe(spi);
1148 ret = -ENODEV; 1145 if (ret)
1149 goto error_probe; 1146 goto error_probe;
1150 } 1147
1151 mcp251x_hw_sleep(spi); 1148 mcp251x_hw_sleep(spi);
1152 1149
1153 ret = register_candev(net); 1150 ret = register_candev(net);
@@ -1156,7 +1153,7 @@ static int mcp251x_can_probe(struct spi_device *spi)
1156 1153
1157 devm_can_led_init(net); 1154 devm_can_led_init(net);
1158 1155
1159 return ret; 1156 return 0;
1160 1157
1161error_probe: 1158error_probe:
1162 if (mcp251x_enable_dma) 1159 if (mcp251x_enable_dma)
diff --git a/drivers/net/can/usb/Kconfig b/drivers/net/can/usb/Kconfig
index fc96a3d83ebe..a77db919363c 100644
--- a/drivers/net/can/usb/Kconfig
+++ b/drivers/net/can/usb/Kconfig
@@ -13,13 +13,21 @@ config CAN_ESD_USB2
13 This driver supports the CAN-USB/2 interface 13 This driver supports the CAN-USB/2 interface
14 from esd electronic system design gmbh (http://www.esd.eu). 14 from esd electronic system design gmbh (http://www.esd.eu).
15 15
16config CAN_GS_USB
17 tristate "Geschwister Schneider UG interfaces"
18 ---help---
19 This driver supports the Geschwister Schneider USB/CAN devices.
20 If unsure choose N,
21 choose Y for built in support,
22 M to compile as module (module will be named: gs_usb).
23
16config CAN_KVASER_USB 24config CAN_KVASER_USB
17 tristate "Kvaser CAN/USB interface" 25 tristate "Kvaser CAN/USB interface"
18 ---help--- 26 ---help---
19 This driver adds support for Kvaser CAN/USB devices like Kvaser 27 This driver adds support for Kvaser CAN/USB devices like Kvaser
20 Leaf Light. 28 Leaf Light.
21 29
22 The driver gives support for the following devices: 30 The driver provides support for the following devices:
23 - Kvaser Leaf Light 31 - Kvaser Leaf Light
24 - Kvaser Leaf Professional HS 32 - Kvaser Leaf Professional HS
25 - Kvaser Leaf SemiPro HS 33 - Kvaser Leaf SemiPro HS
@@ -36,6 +44,8 @@ config CAN_KVASER_USB
36 - Kvaser Leaf Light "China" 44 - Kvaser Leaf Light "China"
37 - Kvaser BlackBird SemiPro 45 - Kvaser BlackBird SemiPro
38 - Kvaser USBcan R 46 - Kvaser USBcan R
47 - Kvaser Leaf Light v2
48 - Kvaser Mini PCI Express HS
39 49
40 If unsure, say N. 50 If unsure, say N.
41 51
diff --git a/drivers/net/can/usb/Makefile b/drivers/net/can/usb/Makefile
index becef460a91a..7b9a393b1ac8 100644
--- a/drivers/net/can/usb/Makefile
+++ b/drivers/net/can/usb/Makefile
@@ -4,6 +4,7 @@
4 4
5obj-$(CONFIG_CAN_EMS_USB) += ems_usb.o 5obj-$(CONFIG_CAN_EMS_USB) += ems_usb.o
6obj-$(CONFIG_CAN_ESD_USB2) += esd_usb2.o 6obj-$(CONFIG_CAN_ESD_USB2) += esd_usb2.o
7obj-$(CONFIG_CAN_GS_USB) += gs_usb.o
7obj-$(CONFIG_CAN_KVASER_USB) += kvaser_usb.o 8obj-$(CONFIG_CAN_KVASER_USB) += kvaser_usb.o
8obj-$(CONFIG_CAN_PEAK_USB) += peak_usb/ 9obj-$(CONFIG_CAN_PEAK_USB) += peak_usb/
9obj-$(CONFIG_CAN_8DEV_USB) += usb_8dev.o 10obj-$(CONFIG_CAN_8DEV_USB) += usb_8dev.o
diff --git a/drivers/net/can/usb/gs_usb.c b/drivers/net/can/usb/gs_usb.c
new file mode 100644
index 000000000000..04b0f84612f0
--- /dev/null
+++ b/drivers/net/can/usb/gs_usb.c
@@ -0,0 +1,971 @@
1/* CAN driver for Geschwister Schneider USB/CAN devices.
2 *
3 * Copyright (C) 2013 Geschwister Schneider Technologie-,
4 * Entwicklungs- und Vertriebs UG (Haftungsbeschränkt).
5 *
6 * Many thanks to all socketcan devs!
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published
10 * by the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 */
17
18#include <linux/init.h>
19#include <linux/signal.h>
20#include <linux/module.h>
21#include <linux/netdevice.h>
22#include <linux/usb.h>
23
24#include <linux/can.h>
25#include <linux/can/dev.h>
26#include <linux/can/error.h>
27
28/* Device specific constants */
29#define USB_GSUSB_1_VENDOR_ID 0x1d50
30#define USB_GSUSB_1_PRODUCT_ID 0x606f
31
32#define GSUSB_ENDPOINT_IN 1
33#define GSUSB_ENDPOINT_OUT 2
34
35/* Device specific constants */
36enum gs_usb_breq {
37 GS_USB_BREQ_HOST_FORMAT = 0,
38 GS_USB_BREQ_BITTIMING,
39 GS_USB_BREQ_MODE,
40 GS_USB_BREQ_BERR,
41 GS_USB_BREQ_BT_CONST,
42 GS_USB_BREQ_DEVICE_CONFIG
43};
44
45enum gs_can_mode {
46 /* reset a channel. turns it off */
47 GS_CAN_MODE_RESET = 0,
48 /* starts a channel */
49 GS_CAN_MODE_START
50};
51
52enum gs_can_state {
53 GS_CAN_STATE_ERROR_ACTIVE = 0,
54 GS_CAN_STATE_ERROR_WARNING,
55 GS_CAN_STATE_ERROR_PASSIVE,
56 GS_CAN_STATE_BUS_OFF,
57 GS_CAN_STATE_STOPPED,
58 GS_CAN_STATE_SLEEPING
59};
60
61/* data types passed between host and device */
62struct gs_host_config {
63 u32 byte_order;
64} __packed;
65/* All data exchanged between host and device is exchanged in host byte order,
66 * thanks to the struct gs_host_config byte_order member, which is sent first
67 * to indicate the desired byte order.
68 */
69
70struct gs_device_config {
71 u8 reserved1;
72 u8 reserved2;
73 u8 reserved3;
74 u8 icount;
75 u32 sw_version;
76 u32 hw_version;
77} __packed;
78
79#define GS_CAN_MODE_NORMAL 0
80#define GS_CAN_MODE_LISTEN_ONLY (1<<0)
81#define GS_CAN_MODE_LOOP_BACK (1<<1)
82#define GS_CAN_MODE_TRIPLE_SAMPLE (1<<2)
83#define GS_CAN_MODE_ONE_SHOT (1<<3)
84
85struct gs_device_mode {
86 u32 mode;
87 u32 flags;
88} __packed;
89
90struct gs_device_state {
91 u32 state;
92 u32 rxerr;
93 u32 txerr;
94} __packed;
95
96struct gs_device_bittiming {
97 u32 prop_seg;
98 u32 phase_seg1;
99 u32 phase_seg2;
100 u32 sjw;
101 u32 brp;
102} __packed;
103
104#define GS_CAN_FEATURE_LISTEN_ONLY (1<<0)
105#define GS_CAN_FEATURE_LOOP_BACK (1<<1)
106#define GS_CAN_FEATURE_TRIPLE_SAMPLE (1<<2)
107#define GS_CAN_FEATURE_ONE_SHOT (1<<3)
108
109struct gs_device_bt_const {
110 u32 feature;
111 u32 fclk_can;
112 u32 tseg1_min;
113 u32 tseg1_max;
114 u32 tseg2_min;
115 u32 tseg2_max;
116 u32 sjw_max;
117 u32 brp_min;
118 u32 brp_max;
119 u32 brp_inc;
120} __packed;
121
122#define GS_CAN_FLAG_OVERFLOW 1
123
124struct gs_host_frame {
125 u32 echo_id;
126 u32 can_id;
127
128 u8 can_dlc;
129 u8 channel;
130 u8 flags;
131 u8 reserved;
132
133 u8 data[8];
134} __packed;
135/* The GS USB devices make use of the same flags and masks as in
136 * linux/can.h and linux/can/error.h, and no additional mapping is necessary.
137 */
138
139/* Only send a max of GS_MAX_TX_URBS frames per channel at a time. */
140#define GS_MAX_TX_URBS 10
141/* Only launch a max of GS_MAX_RX_URBS usb requests at a time. */
142#define GS_MAX_RX_URBS 30
143/* Maximum number of interfaces the driver supports per device.
144 * Current hardware only supports 2 interfaces. The future may vary.
145 */
146#define GS_MAX_INTF 2
147
148struct gs_tx_context {
149 struct gs_can *dev;
150 unsigned int echo_id;
151};
152
153struct gs_can {
154 struct can_priv can; /* must be the first member */
155
156 struct gs_usb *parent;
157
158 struct net_device *netdev;
159 struct usb_device *udev;
160 struct usb_interface *iface;
161
162 struct can_bittiming_const bt_const;
163 unsigned int channel; /* channel number */
164
165 /* This lock prevents a race condition between xmit and recieve. */
166 spinlock_t tx_ctx_lock;
167 struct gs_tx_context tx_context[GS_MAX_TX_URBS];
168
169 struct usb_anchor tx_submitted;
170 atomic_t active_tx_urbs;
171};
172
173/* usb interface struct */
174struct gs_usb {
175 struct gs_can *canch[GS_MAX_INTF];
176 struct usb_anchor rx_submitted;
177 atomic_t active_channels;
178 struct usb_device *udev;
179};
180
181/* 'allocate' a tx context.
182 * returns a valid tx context or NULL if there is no space.
183 */
184static struct gs_tx_context *gs_alloc_tx_context(struct gs_can *dev)
185{
186 int i = 0;
187 unsigned long flags;
188
189 spin_lock_irqsave(&dev->tx_ctx_lock, flags);
190
191 for (; i < GS_MAX_TX_URBS; i++) {
192 if (dev->tx_context[i].echo_id == GS_MAX_TX_URBS) {
193 dev->tx_context[i].echo_id = i;
194 spin_unlock_irqrestore(&dev->tx_ctx_lock, flags);
195 return &dev->tx_context[i];
196 }
197 }
198
199 spin_unlock_irqrestore(&dev->tx_ctx_lock, flags);
200 return NULL;
201}
202
203/* releases a tx context
204 */
205static void gs_free_tx_context(struct gs_tx_context *txc)
206{
207 txc->echo_id = GS_MAX_TX_URBS;
208}
209
210/* Get a tx context by id.
211 */
212static struct gs_tx_context *gs_get_tx_context(struct gs_can *dev, unsigned int id)
213{
214 unsigned long flags;
215
216 if (id < GS_MAX_TX_URBS) {
217 spin_lock_irqsave(&dev->tx_ctx_lock, flags);
218 if (dev->tx_context[id].echo_id == id) {
219 spin_unlock_irqrestore(&dev->tx_ctx_lock, flags);
220 return &dev->tx_context[id];
221 }
222 spin_unlock_irqrestore(&dev->tx_ctx_lock, flags);
223 }
224 return NULL;
225}
226
227static int gs_cmd_reset(struct gs_usb *gsusb, struct gs_can *gsdev)
228{
229 struct gs_device_mode *dm;
230 struct usb_interface *intf = gsdev->iface;
231 int rc;
232
233 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
234 if (!dm)
235 return -ENOMEM;
236
237 dm->mode = GS_CAN_MODE_RESET;
238
239 rc = usb_control_msg(interface_to_usbdev(intf),
240 usb_sndctrlpipe(interface_to_usbdev(intf), 0),
241 GS_USB_BREQ_MODE,
242 USB_DIR_OUT|USB_TYPE_VENDOR|USB_RECIP_INTERFACE,
243 gsdev->channel,
244 0,
245 dm,
246 sizeof(*dm),
247 1000);
248
249 return rc;
250}
251
252static void gs_update_state(struct gs_can *dev, struct can_frame *cf)
253{
254 struct can_device_stats *can_stats = &dev->can.can_stats;
255
256 if (cf->can_id & CAN_ERR_RESTARTED) {
257 dev->can.state = CAN_STATE_ERROR_ACTIVE;
258 can_stats->restarts++;
259 } else if (cf->can_id & CAN_ERR_BUSOFF) {
260 dev->can.state = CAN_STATE_BUS_OFF;
261 can_stats->bus_off++;
262 } else if (cf->can_id & CAN_ERR_CRTL) {
263 if ((cf->data[1] & CAN_ERR_CRTL_TX_WARNING) ||
264 (cf->data[1] & CAN_ERR_CRTL_RX_WARNING)) {
265 dev->can.state = CAN_STATE_ERROR_WARNING;
266 can_stats->error_warning++;
267 } else if ((cf->data[1] & CAN_ERR_CRTL_TX_PASSIVE) ||
268 (cf->data[1] & CAN_ERR_CRTL_RX_PASSIVE)) {
269 dev->can.state = CAN_STATE_ERROR_PASSIVE;
270 can_stats->error_passive++;
271 } else {
272 dev->can.state = CAN_STATE_ERROR_ACTIVE;
273 }
274 }
275}
276
277static void gs_usb_recieve_bulk_callback(struct urb *urb)
278{
279 struct gs_usb *usbcan = urb->context;
280 struct gs_can *dev;
281 struct net_device *netdev;
282 int rc;
283 struct net_device_stats *stats;
284 struct gs_host_frame *hf = urb->transfer_buffer;
285 struct gs_tx_context *txc;
286 struct can_frame *cf;
287 struct sk_buff *skb;
288
289 BUG_ON(!usbcan);
290
291 switch (urb->status) {
292 case 0: /* success */
293 break;
294 case -ENOENT:
295 case -ESHUTDOWN:
296 return;
297 default:
298 /* do not resubmit aborted urbs. eg: when device goes down */
299 return;
300 }
301
302 /* device reports out of range channel id */
303 if (hf->channel >= GS_MAX_INTF)
304 goto resubmit_urb;
305
306 dev = usbcan->canch[hf->channel];
307
308 netdev = dev->netdev;
309 stats = &netdev->stats;
310
311 if (!netif_device_present(netdev))
312 return;
313
314 if (hf->echo_id == -1) { /* normal rx */
315 skb = alloc_can_skb(dev->netdev, &cf);
316 if (!skb)
317 return;
318
319 cf->can_id = hf->can_id;
320
321 cf->can_dlc = get_can_dlc(hf->can_dlc);
322 memcpy(cf->data, hf->data, 8);
323
324 /* ERROR frames tell us information about the controller */
325 if (hf->can_id & CAN_ERR_FLAG)
326 gs_update_state(dev, cf);
327
328 netdev->stats.rx_packets++;
329 netdev->stats.rx_bytes += hf->can_dlc;
330
331 netif_rx(skb);
332 } else { /* echo_id == hf->echo_id */
333 if (hf->echo_id >= GS_MAX_TX_URBS) {
334 netdev_err(netdev,
335 "Unexpected out of range echo id %d\n",
336 hf->echo_id);
337 goto resubmit_urb;
338 }
339
340 netdev->stats.tx_packets++;
341 netdev->stats.tx_bytes += hf->can_dlc;
342
343 txc = gs_get_tx_context(dev, hf->echo_id);
344
345 /* bad devices send bad echo_ids. */
346 if (!txc) {
347 netdev_err(netdev,
348 "Unexpected unused echo id %d\n",
349 hf->echo_id);
350 goto resubmit_urb;
351 }
352
353 can_get_echo_skb(netdev, hf->echo_id);
354
355 gs_free_tx_context(txc);
356
357 netif_wake_queue(netdev);
358 }
359
360 if (hf->flags & GS_CAN_FLAG_OVERFLOW) {
361 skb = alloc_can_err_skb(netdev, &cf);
362 if (!skb)
363 goto resubmit_urb;
364
365 cf->can_id |= CAN_ERR_CRTL;
366 cf->can_dlc = CAN_ERR_DLC;
367 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
368 stats->rx_over_errors++;
369 stats->rx_errors++;
370 netif_rx(skb);
371 }
372
373 resubmit_urb:
374 usb_fill_bulk_urb(urb,
375 usbcan->udev,
376 usb_rcvbulkpipe(usbcan->udev, GSUSB_ENDPOINT_IN),
377 hf,
378 sizeof(struct gs_host_frame),
379 gs_usb_recieve_bulk_callback,
380 usbcan
381 );
382
383 rc = usb_submit_urb(urb, GFP_ATOMIC);
384
385 /* USB failure take down all interfaces */
386 if (rc == -ENODEV) {
387 for (rc = 0; rc < GS_MAX_INTF; rc++) {
388 if (usbcan->canch[rc])
389 netif_device_detach(usbcan->canch[rc]->netdev);
390 }
391 }
392}
393
394static int gs_usb_set_bittiming(struct net_device *netdev)
395{
396 struct gs_can *dev = netdev_priv(netdev);
397 struct can_bittiming *bt = &dev->can.bittiming;
398 struct usb_interface *intf = dev->iface;
399 int rc;
400 struct gs_device_bittiming *dbt;
401
402 dbt = kmalloc(sizeof(*dbt), GFP_KERNEL);
403 if (!dbt)
404 return -ENOMEM;
405
406 dbt->prop_seg = bt->prop_seg;
407 dbt->phase_seg1 = bt->phase_seg1;
408 dbt->phase_seg2 = bt->phase_seg2;
409 dbt->sjw = bt->sjw;
410 dbt->brp = bt->brp;
411
412 /* request bit timings */
413 rc = usb_control_msg(interface_to_usbdev(intf),
414 usb_sndctrlpipe(interface_to_usbdev(intf), 0),
415 GS_USB_BREQ_BITTIMING,
416 USB_DIR_OUT|USB_TYPE_VENDOR|USB_RECIP_INTERFACE,
417 dev->channel,
418 0,
419 dbt,
420 sizeof(*dbt),
421 1000);
422
423 kfree(dbt);
424
425 if (rc < 0)
426 dev_err(netdev->dev.parent, "Couldn't set bittimings (err=%d)",
427 rc);
428
429 return rc;
430}
431
432static void gs_usb_xmit_callback(struct urb *urb)
433{
434 struct gs_tx_context *txc = urb->context;
435 struct gs_can *dev = txc->dev;
436 struct net_device *netdev = dev->netdev;
437
438 if (urb->status)
439 netdev_info(netdev, "usb xmit fail %d\n", txc->echo_id);
440
441 usb_free_coherent(urb->dev,
442 urb->transfer_buffer_length,
443 urb->transfer_buffer,
444 urb->transfer_dma);
445
446 atomic_dec(&dev->active_tx_urbs);
447
448 if (!netif_device_present(netdev))
449 return;
450
451 if (netif_queue_stopped(netdev))
452 netif_wake_queue(netdev);
453}
454
455static netdev_tx_t gs_can_start_xmit(struct sk_buff *skb, struct net_device *netdev)
456{
457 struct gs_can *dev = netdev_priv(netdev);
458 struct net_device_stats *stats = &dev->netdev->stats;
459 struct urb *urb;
460 struct gs_host_frame *hf;
461 struct can_frame *cf;
462 int rc;
463 unsigned int idx;
464 struct gs_tx_context *txc;
465
466 if (can_dropped_invalid_skb(netdev, skb))
467 return NETDEV_TX_OK;
468
469 /* find an empty context to keep track of transmission */
470 txc = gs_alloc_tx_context(dev);
471 if (!txc)
472 return NETDEV_TX_BUSY;
473
474 /* create a URB, and a buffer for it */
475 urb = usb_alloc_urb(0, GFP_ATOMIC);
476 if (!urb) {
477 netdev_err(netdev, "No memory left for URB\n");
478 goto nomem_urb;
479 }
480
481 hf = usb_alloc_coherent(dev->udev, sizeof(*hf), GFP_ATOMIC,
482 &urb->transfer_dma);
483 if (!hf) {
484 netdev_err(netdev, "No memory left for USB buffer\n");
485 goto nomem_hf;
486 }
487
488 idx = txc->echo_id;
489
490 if (idx >= GS_MAX_TX_URBS) {
491 netdev_err(netdev, "Invalid tx context %d\n", idx);
492 goto badidx;
493 }
494
495 hf->echo_id = idx;
496 hf->channel = dev->channel;
497
498 cf = (struct can_frame *)skb->data;
499
500 hf->can_id = cf->can_id;
501 hf->can_dlc = cf->can_dlc;
502 memcpy(hf->data, cf->data, cf->can_dlc);
503
504 usb_fill_bulk_urb(urb, dev->udev,
505 usb_sndbulkpipe(dev->udev, GSUSB_ENDPOINT_OUT),
506 hf,
507 sizeof(*hf),
508 gs_usb_xmit_callback,
509 txc);
510
511 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
512 usb_anchor_urb(urb, &dev->tx_submitted);
513
514 can_put_echo_skb(skb, netdev, idx);
515
516 atomic_inc(&dev->active_tx_urbs);
517
518 rc = usb_submit_urb(urb, GFP_ATOMIC);
519 if (unlikely(rc)) { /* usb send failed */
520 atomic_dec(&dev->active_tx_urbs);
521
522 can_free_echo_skb(netdev, idx);
523 gs_free_tx_context(txc);
524
525 usb_unanchor_urb(urb);
526 usb_free_coherent(dev->udev,
527 sizeof(*hf),
528 hf,
529 urb->transfer_dma);
530
531
532 if (rc == -ENODEV) {
533 netif_device_detach(netdev);
534 } else {
535 netdev_err(netdev, "usb_submit failed (err=%d)\n", rc);
536 stats->tx_dropped++;
537 }
538 } else {
539 /* Slow down tx path */
540 if (atomic_read(&dev->active_tx_urbs) >= GS_MAX_TX_URBS)
541 netif_stop_queue(netdev);
542 }
543
544 /* let usb core take care of this urb */
545 usb_free_urb(urb);
546
547 return NETDEV_TX_OK;
548
549 badidx:
550 usb_free_coherent(dev->udev,
551 sizeof(*hf),
552 hf,
553 urb->transfer_dma);
554 nomem_hf:
555 usb_free_urb(urb);
556
557 nomem_urb:
558 gs_free_tx_context(txc);
559 dev_kfree_skb(skb);
560 stats->tx_dropped++;
561 return NETDEV_TX_OK;
562}
563
564static int gs_can_open(struct net_device *netdev)
565{
566 struct gs_can *dev = netdev_priv(netdev);
567 struct gs_usb *parent = dev->parent;
568 int rc, i;
569 struct gs_device_mode *dm;
570 u32 ctrlmode;
571
572 rc = open_candev(netdev);
573 if (rc)
574 return rc;
575
576 if (atomic_add_return(1, &parent->active_channels) == 1) {
577 for (i = 0; i < GS_MAX_RX_URBS; i++) {
578 struct urb *urb;
579 u8 *buf;
580
581 /* alloc rx urb */
582 urb = usb_alloc_urb(0, GFP_KERNEL);
583 if (!urb) {
584 netdev_err(netdev,
585 "No memory left for URB\n");
586 return -ENOMEM;
587 }
588
589 /* alloc rx buffer */
590 buf = usb_alloc_coherent(dev->udev,
591 sizeof(struct gs_host_frame),
592 GFP_KERNEL,
593 &urb->transfer_dma);
594 if (!buf) {
595 netdev_err(netdev,
596 "No memory left for USB buffer\n");
597 usb_free_urb(urb);
598 return -ENOMEM;
599 }
600
601 /* fill, anchor, and submit rx urb */
602 usb_fill_bulk_urb(urb,
603 dev->udev,
604 usb_rcvbulkpipe(dev->udev,
605 GSUSB_ENDPOINT_IN),
606 buf,
607 sizeof(struct gs_host_frame),
608 gs_usb_recieve_bulk_callback,
609 parent);
610 urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
611
612 usb_anchor_urb(urb, &parent->rx_submitted);
613
614 rc = usb_submit_urb(urb, GFP_KERNEL);
615 if (rc) {
616 if (rc == -ENODEV)
617 netif_device_detach(dev->netdev);
618
619 netdev_err(netdev,
620 "usb_submit failed (err=%d)\n",
621 rc);
622
623 usb_unanchor_urb(urb);
624 break;
625 }
626
627 /* Drop reference,
628 * USB core will take care of freeing it
629 */
630 usb_free_urb(urb);
631 }
632 }
633
634 dm = kmalloc(sizeof(*dm), GFP_KERNEL);
635 if (!dm)
636 return -ENOMEM;
637
638 /* flags */
639 ctrlmode = dev->can.ctrlmode;
640 dm->flags = 0;
641
642 if (ctrlmode & CAN_CTRLMODE_LOOPBACK)
643 dm->flags |= GS_CAN_MODE_LOOP_BACK;
644 else if (ctrlmode & CAN_CTRLMODE_LISTENONLY)
645 dm->flags |= GS_CAN_MODE_LISTEN_ONLY;
646
647 /* Controller is not allowed to retry TX
648 * this mode is unavailable on atmels uc3c hardware
649 */
650 if (ctrlmode & CAN_CTRLMODE_ONE_SHOT)
651 dm->flags |= GS_CAN_MODE_ONE_SHOT;
652
653 if (ctrlmode & CAN_CTRLMODE_3_SAMPLES)
654 dm->flags |= GS_CAN_MODE_TRIPLE_SAMPLE;
655
656 /* finally start device */
657 dm->mode = GS_CAN_MODE_START;
658 rc = usb_control_msg(interface_to_usbdev(dev->iface),
659 usb_sndctrlpipe(interface_to_usbdev(dev->iface), 0),
660 GS_USB_BREQ_MODE,
661 USB_DIR_OUT|USB_TYPE_VENDOR|USB_RECIP_INTERFACE,
662 dev->channel,
663 0,
664 dm,
665 sizeof(*dm),
666 1000);
667
668 if (rc < 0) {
669 netdev_err(netdev, "Couldn't start device (err=%d)\n", rc);
670 kfree(dm);
671 return rc;
672 }
673
674 kfree(dm);
675
676 dev->can.state = CAN_STATE_ERROR_ACTIVE;
677
678 if (!(dev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
679 netif_start_queue(netdev);
680
681 return 0;
682}
683
684static int gs_can_close(struct net_device *netdev)
685{
686 int rc;
687 struct gs_can *dev = netdev_priv(netdev);
688 struct gs_usb *parent = dev->parent;
689
690 netif_stop_queue(netdev);
691
692 /* Stop polling */
693 if (atomic_dec_and_test(&parent->active_channels))
694 usb_kill_anchored_urbs(&parent->rx_submitted);
695
696 /* Stop sending URBs */
697 usb_kill_anchored_urbs(&dev->tx_submitted);
698 atomic_set(&dev->active_tx_urbs, 0);
699
700 /* reset the device */
701 rc = gs_cmd_reset(parent, dev);
702 if (rc < 0)
703 netdev_warn(netdev, "Couldn't shutdown device (err=%d)", rc);
704
705 /* reset tx contexts */
706 for (rc = 0; rc < GS_MAX_TX_URBS; rc++) {
707 dev->tx_context[rc].dev = dev;
708 dev->tx_context[rc].echo_id = GS_MAX_TX_URBS;
709 }
710
711 /* close the netdev */
712 close_candev(netdev);
713
714 return 0;
715}
716
717static const struct net_device_ops gs_usb_netdev_ops = {
718 .ndo_open = gs_can_open,
719 .ndo_stop = gs_can_close,
720 .ndo_start_xmit = gs_can_start_xmit,
721};
722
723static struct gs_can *gs_make_candev(unsigned int channel, struct usb_interface *intf)
724{
725 struct gs_can *dev;
726 struct net_device *netdev;
727 int rc;
728 struct gs_device_bt_const *bt_const;
729
730 bt_const = kmalloc(sizeof(*bt_const), GFP_KERNEL);
731 if (!bt_const)
732 return ERR_PTR(-ENOMEM);
733
734 /* fetch bit timing constants */
735 rc = usb_control_msg(interface_to_usbdev(intf),
736 usb_rcvctrlpipe(interface_to_usbdev(intf), 0),
737 GS_USB_BREQ_BT_CONST,
738 USB_DIR_IN|USB_TYPE_VENDOR|USB_RECIP_INTERFACE,
739 channel,
740 0,
741 bt_const,
742 sizeof(*bt_const),
743 1000);
744
745 if (rc < 0) {
746 dev_err(&intf->dev,
747 "Couldn't get bit timing const for channel (err=%d)\n",
748 rc);
749 kfree(bt_const);
750 return ERR_PTR(rc);
751 }
752
753 /* create netdev */
754 netdev = alloc_candev(sizeof(struct gs_can), GS_MAX_TX_URBS);
755 if (!netdev) {
756 dev_err(&intf->dev, "Couldn't allocate candev\n");
757 kfree(bt_const);
758 return ERR_PTR(-ENOMEM);
759 }
760
761 dev = netdev_priv(netdev);
762
763 netdev->netdev_ops = &gs_usb_netdev_ops;
764
765 netdev->flags |= IFF_ECHO; /* we support full roundtrip echo */
766
767 /* dev settup */
768 strcpy(dev->bt_const.name, "gs_usb");
769 dev->bt_const.tseg1_min = bt_const->tseg1_min;
770 dev->bt_const.tseg1_max = bt_const->tseg1_max;
771 dev->bt_const.tseg2_min = bt_const->tseg2_min;
772 dev->bt_const.tseg2_max = bt_const->tseg2_max;
773 dev->bt_const.sjw_max = bt_const->sjw_max;
774 dev->bt_const.brp_min = bt_const->brp_min;
775 dev->bt_const.brp_max = bt_const->brp_max;
776 dev->bt_const.brp_inc = bt_const->brp_inc;
777
778 dev->udev = interface_to_usbdev(intf);
779 dev->iface = intf;
780 dev->netdev = netdev;
781 dev->channel = channel;
782
783 init_usb_anchor(&dev->tx_submitted);
784 atomic_set(&dev->active_tx_urbs, 0);
785 spin_lock_init(&dev->tx_ctx_lock);
786 for (rc = 0; rc < GS_MAX_TX_URBS; rc++) {
787 dev->tx_context[rc].dev = dev;
788 dev->tx_context[rc].echo_id = GS_MAX_TX_URBS;
789 }
790
791 /* can settup */
792 dev->can.state = CAN_STATE_STOPPED;
793 dev->can.clock.freq = bt_const->fclk_can;
794 dev->can.bittiming_const = &dev->bt_const;
795 dev->can.do_set_bittiming = gs_usb_set_bittiming;
796
797 dev->can.ctrlmode_supported = 0;
798
799 if (bt_const->feature & GS_CAN_FEATURE_LISTEN_ONLY)
800 dev->can.ctrlmode_supported |= CAN_CTRLMODE_LISTENONLY;
801
802 if (bt_const->feature & GS_CAN_FEATURE_LOOP_BACK)
803 dev->can.ctrlmode_supported |= CAN_CTRLMODE_LOOPBACK;
804
805 if (bt_const->feature & GS_CAN_FEATURE_TRIPLE_SAMPLE)
806 dev->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
807
808 if (bt_const->feature & GS_CAN_FEATURE_ONE_SHOT)
809 dev->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;
810
811 kfree(bt_const);
812
813 SET_NETDEV_DEV(netdev, &intf->dev);
814
815 rc = register_candev(dev->netdev);
816 if (rc) {
817 free_candev(dev->netdev);
818 dev_err(&intf->dev, "Couldn't register candev (err=%d)\n", rc);
819 return ERR_PTR(rc);
820 }
821
822 return dev;
823}
824
825static void gs_destroy_candev(struct gs_can *dev)
826{
827 unregister_candev(dev->netdev);
828 free_candev(dev->netdev);
829 usb_kill_anchored_urbs(&dev->tx_submitted);
830 kfree(dev);
831}
832
833static int gs_usb_probe(struct usb_interface *intf, const struct usb_device_id *id)
834{
835 struct gs_usb *dev;
836 int rc = -ENOMEM;
837 unsigned int icount, i;
838 struct gs_host_config *hconf;
839 struct gs_device_config *dconf;
840
841 hconf = kmalloc(sizeof(*hconf), GFP_KERNEL);
842 if (!hconf)
843 return -ENOMEM;
844
845 hconf->byte_order = 0x0000beef;
846
847 /* send host config */
848 rc = usb_control_msg(interface_to_usbdev(intf),
849 usb_sndctrlpipe(interface_to_usbdev(intf), 0),
850 GS_USB_BREQ_HOST_FORMAT,
851 USB_DIR_OUT|USB_TYPE_VENDOR|USB_RECIP_INTERFACE,
852 1,
853 intf->altsetting[0].desc.bInterfaceNumber,
854 hconf,
855 sizeof(*hconf),
856 1000);
857
858 kfree(hconf);
859
860 if (rc < 0) {
861 dev_err(&intf->dev, "Couldn't send data format (err=%d)\n",
862 rc);
863 return rc;
864 }
865
866 dconf = kmalloc(sizeof(*dconf), GFP_KERNEL);
867 if (!dconf)
868 return -ENOMEM;
869
870 /* read device config */
871 rc = usb_control_msg(interface_to_usbdev(intf),
872 usb_rcvctrlpipe(interface_to_usbdev(intf), 0),
873 GS_USB_BREQ_DEVICE_CONFIG,
874 USB_DIR_IN|USB_TYPE_VENDOR|USB_RECIP_INTERFACE,
875 1,
876 intf->altsetting[0].desc.bInterfaceNumber,
877 dconf,
878 sizeof(*dconf),
879 1000);
880 if (rc < 0) {
881 dev_err(&intf->dev, "Couldn't get device config: (err=%d)\n",
882 rc);
883
884 kfree(dconf);
885
886 return rc;
887 }
888
889 icount = dconf->icount+1;
890
891 kfree(dconf);
892
893 dev_info(&intf->dev, "Configuring for %d interfaces\n", icount);
894
895 if (icount > GS_MAX_INTF) {
896 dev_err(&intf->dev,
897 "Driver cannot handle more that %d CAN interfaces\n",
898 GS_MAX_INTF);
899 return -EINVAL;
900 }
901
902 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
903 init_usb_anchor(&dev->rx_submitted);
904
905 atomic_set(&dev->active_channels, 0);
906
907 usb_set_intfdata(intf, dev);
908 dev->udev = interface_to_usbdev(intf);
909
910 for (i = 0; i < icount; i++) {
911 dev->canch[i] = gs_make_candev(i, intf);
912 if (IS_ERR_OR_NULL(dev->canch[i])) {
913 /* on failure destroy previously created candevs */
914 icount = i;
915 for (i = 0; i < icount; i++) {
916 gs_destroy_candev(dev->canch[i]);
917 dev->canch[i] = NULL;
918 }
919 kfree(dev);
920 return rc;
921 }
922 dev->canch[i]->parent = dev;
923 }
924
925 return 0;
926}
927
928static void gs_usb_disconnect(struct usb_interface *intf)
929{
930 unsigned i;
931 struct gs_usb *dev = usb_get_intfdata(intf);
932 usb_set_intfdata(intf, NULL);
933
934 if (!dev) {
935 dev_err(&intf->dev, "Disconnect (nodata)\n");
936 return;
937 }
938
939 for (i = 0; i < GS_MAX_INTF; i++) {
940 struct gs_can *can = dev->canch[i];
941
942 if (!can)
943 continue;
944
945 gs_destroy_candev(can);
946 }
947
948 usb_kill_anchored_urbs(&dev->rx_submitted);
949}
950
951static const struct usb_device_id gs_usb_table[] = {
952 {USB_DEVICE(USB_GSUSB_1_VENDOR_ID, USB_GSUSB_1_PRODUCT_ID)},
953 {} /* Terminating entry */
954};
955
956MODULE_DEVICE_TABLE(usb, gs_usb_table);
957
958static struct usb_driver gs_usb_driver = {
959 .name = "gs_usb",
960 .probe = gs_usb_probe,
961 .disconnect = gs_usb_disconnect,
962 .id_table = gs_usb_table,
963};
964
965module_usb_driver(gs_usb_driver);
966
967MODULE_AUTHOR("Maximilian Schneider <mws@schneidersoft.net>");
968MODULE_DESCRIPTION(
969"Socket CAN device driver for Geschwister Schneider Technologie-, "
970"Entwicklungs- und Vertriebs UG. USB2.0 to CAN interfaces.");
971MODULE_LICENSE("GPL v2");
diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c
index 4ca46edc061d..541fb7a05625 100644
--- a/drivers/net/can/usb/kvaser_usb.c
+++ b/drivers/net/can/usb/kvaser_usb.c
@@ -53,6 +53,8 @@
53#define USB_OEM_MERCURY_PRODUCT_ID 34 53#define USB_OEM_MERCURY_PRODUCT_ID 34
54#define USB_OEM_LEAF_PRODUCT_ID 35 54#define USB_OEM_LEAF_PRODUCT_ID 35
55#define USB_CAN_R_PRODUCT_ID 39 55#define USB_CAN_R_PRODUCT_ID 39
56#define USB_LEAF_LITE_V2_PRODUCT_ID 288
57#define USB_MINI_PCIE_HS_PRODUCT_ID 289
56 58
57/* USB devices features */ 59/* USB devices features */
58#define KVASER_HAS_SILENT_MODE BIT(0) 60#define KVASER_HAS_SILENT_MODE BIT(0)
@@ -356,6 +358,8 @@ static const struct usb_device_id kvaser_usb_table[] = {
356 .driver_info = KVASER_HAS_TXRX_ERRORS }, 358 .driver_info = KVASER_HAS_TXRX_ERRORS },
357 { USB_DEVICE(KVASER_VENDOR_ID, USB_CAN_R_PRODUCT_ID), 359 { USB_DEVICE(KVASER_VENDOR_ID, USB_CAN_R_PRODUCT_ID),
358 .driver_info = KVASER_HAS_TXRX_ERRORS }, 360 .driver_info = KVASER_HAS_TXRX_ERRORS },
361 { USB_DEVICE(KVASER_VENDOR_ID, USB_LEAF_LITE_V2_PRODUCT_ID) },
362 { USB_DEVICE(KVASER_VENDOR_ID, USB_MINI_PCIE_HS_PRODUCT_ID) },
359 { } 363 { }
360}; 364};
361MODULE_DEVICE_TABLE(usb, kvaser_usb_table); 365MODULE_DEVICE_TABLE(usb, kvaser_usb_table);
@@ -379,38 +383,43 @@ static int kvaser_usb_wait_msg(const struct kvaser_usb *dev, u8 id,
379 void *buf; 383 void *buf;
380 int actual_len; 384 int actual_len;
381 int err; 385 int err;
382 int pos = 0; 386 int pos;
387 unsigned long to = jiffies + msecs_to_jiffies(USB_RECV_TIMEOUT);
383 388
384 buf = kzalloc(RX_BUFFER_SIZE, GFP_KERNEL); 389 buf = kzalloc(RX_BUFFER_SIZE, GFP_KERNEL);
385 if (!buf) 390 if (!buf)
386 return -ENOMEM; 391 return -ENOMEM;
387 392
388 err = usb_bulk_msg(dev->udev, 393 do {
389 usb_rcvbulkpipe(dev->udev, 394 err = usb_bulk_msg(dev->udev,
390 dev->bulk_in->bEndpointAddress), 395 usb_rcvbulkpipe(dev->udev,
391 buf, RX_BUFFER_SIZE, &actual_len, 396 dev->bulk_in->bEndpointAddress),
392 USB_RECV_TIMEOUT); 397 buf, RX_BUFFER_SIZE, &actual_len,
393 if (err < 0) 398 USB_RECV_TIMEOUT);
394 goto end; 399 if (err < 0)
400 goto end;
395 401
396 while (pos <= actual_len - MSG_HEADER_LEN) { 402 pos = 0;
397 tmp = buf + pos; 403 while (pos <= actual_len - MSG_HEADER_LEN) {
404 tmp = buf + pos;
398 405
399 if (!tmp->len) 406 if (!tmp->len)
400 break; 407 break;
401 408
402 if (pos + tmp->len > actual_len) { 409 if (pos + tmp->len > actual_len) {
403 dev_err(dev->udev->dev.parent, "Format error\n"); 410 dev_err(dev->udev->dev.parent,
404 break; 411 "Format error\n");
405 } 412 break;
413 }
406 414
407 if (tmp->id == id) { 415 if (tmp->id == id) {
408 memcpy(msg, tmp, tmp->len); 416 memcpy(msg, tmp, tmp->len);
409 goto end; 417 goto end;
410 } 418 }
411 419
412 pos += tmp->len; 420 pos += tmp->len;
413 } 421 }
422 } while (time_before(jiffies, to));
414 423
415 err = -EINVAL; 424 err = -EINVAL;
416 425
diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
new file mode 100644
index 000000000000..5e8b5609c067
--- /dev/null
+++ b/drivers/net/can/xilinx_can.c
@@ -0,0 +1,1208 @@
1/* Xilinx CAN device driver
2 *
3 * Copyright (C) 2012 - 2014 Xilinx, Inc.
4 * Copyright (C) 2009 PetaLogix. All rights reserved.
5 *
6 * Description:
7 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/clk.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/netdevice.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/skbuff.h>
30#include <linux/string.h>
31#include <linux/types.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34#include <linux/can/led.h>
35
36#define DRIVER_NAME "xilinx_can"
37
38/* CAN registers set */
39enum xcan_reg {
40 XCAN_SRR_OFFSET = 0x00, /* Software reset */
41 XCAN_MSR_OFFSET = 0x04, /* Mode select */
42 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
43 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
44 XCAN_ECR_OFFSET = 0x10, /* Error counter */
45 XCAN_ESR_OFFSET = 0x14, /* Error status */
46 XCAN_SR_OFFSET = 0x18, /* Status */
47 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
48 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
49 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
50 XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */
51 XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */
52 XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */
53 XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */
54 XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */
55 XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */
56 XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */
57 XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */
58};
59
60/* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
61#define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
62#define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
63#define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
64#define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
65#define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
66#define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
67#define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
68#define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
69#define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
70#define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
71#define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
72#define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
73#define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
74#define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
75#define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
76#define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
77#define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
78#define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
79#define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
80#define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
81#define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
82#define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
83#define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
84#define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
85#define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
86#define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
87#define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
88#define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
89#define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
90#define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
91#define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
92#define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
93#define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
94#define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
95#define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
96#define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
97#define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
98#define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
99
100#define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
101 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
102 XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
103 XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK)
104
105/* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
106#define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
107#define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
108#define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
109#define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
110#define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
111#define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
112
113/* CAN frame length constants */
114#define XCAN_FRAME_MAX_DATA_LEN 8
115#define XCAN_TIMEOUT (1 * HZ)
116
117/**
118 * struct xcan_priv - This definition define CAN driver instance
119 * @can: CAN private data structure.
120 * @tx_head: Tx CAN packets ready to send on the queue
121 * @tx_tail: Tx CAN packets successfully sended on the queue
122 * @tx_max: Maximum number packets the driver can send
123 * @napi: NAPI structure
124 * @read_reg: For reading data from CAN registers
125 * @write_reg: For writing data to CAN registers
126 * @dev: Network device data structure
127 * @reg_base: Ioremapped address to registers
128 * @irq_flags: For request_irq()
129 * @bus_clk: Pointer to struct clk
130 * @can_clk: Pointer to struct clk
131 */
132struct xcan_priv {
133 struct can_priv can;
134 unsigned int tx_head;
135 unsigned int tx_tail;
136 unsigned int tx_max;
137 struct napi_struct napi;
138 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
139 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
140 u32 val);
141 struct net_device *dev;
142 void __iomem *reg_base;
143 unsigned long irq_flags;
144 struct clk *bus_clk;
145 struct clk *can_clk;
146};
147
148/* CAN Bittiming constants as per Xilinx CAN specs */
149static const struct can_bittiming_const xcan_bittiming_const = {
150 .name = DRIVER_NAME,
151 .tseg1_min = 1,
152 .tseg1_max = 16,
153 .tseg2_min = 1,
154 .tseg2_max = 8,
155 .sjw_max = 4,
156 .brp_min = 1,
157 .brp_max = 256,
158 .brp_inc = 1,
159};
160
161/**
162 * xcan_write_reg_le - Write a value to the device register little endian
163 * @priv: Driver private data structure
164 * @reg: Register offset
165 * @val: Value to write at the Register offset
166 *
167 * Write data to the paricular CAN register
168 */
169static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
170 u32 val)
171{
172 iowrite32(val, priv->reg_base + reg);
173}
174
175/**
176 * xcan_read_reg_le - Read a value from the device register little endian
177 * @priv: Driver private data structure
178 * @reg: Register offset
179 *
180 * Read data from the particular CAN register
181 * Return: value read from the CAN register
182 */
183static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
184{
185 return ioread32(priv->reg_base + reg);
186}
187
188/**
189 * xcan_write_reg_be - Write a value to the device register big endian
190 * @priv: Driver private data structure
191 * @reg: Register offset
192 * @val: Value to write at the Register offset
193 *
194 * Write data to the paricular CAN register
195 */
196static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
197 u32 val)
198{
199 iowrite32be(val, priv->reg_base + reg);
200}
201
202/**
203 * xcan_read_reg_be - Read a value from the device register big endian
204 * @priv: Driver private data structure
205 * @reg: Register offset
206 *
207 * Read data from the particular CAN register
208 * Return: value read from the CAN register
209 */
210static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
211{
212 return ioread32be(priv->reg_base + reg);
213}
214
215/**
216 * set_reset_mode - Resets the CAN device mode
217 * @ndev: Pointer to net_device structure
218 *
219 * This is the driver reset mode routine.The driver
220 * enters into configuration mode.
221 *
222 * Return: 0 on success and failure value on error
223 */
224static int set_reset_mode(struct net_device *ndev)
225{
226 struct xcan_priv *priv = netdev_priv(ndev);
227 unsigned long timeout;
228
229 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
230
231 timeout = jiffies + XCAN_TIMEOUT;
232 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
233 if (time_after(jiffies, timeout)) {
234 netdev_warn(ndev, "timed out for config mode\n");
235 return -ETIMEDOUT;
236 }
237 usleep_range(500, 10000);
238 }
239
240 return 0;
241}
242
243/**
244 * xcan_set_bittiming - CAN set bit timing routine
245 * @ndev: Pointer to net_device structure
246 *
247 * This is the driver set bittiming routine.
248 * Return: 0 on success and failure value on error
249 */
250static int xcan_set_bittiming(struct net_device *ndev)
251{
252 struct xcan_priv *priv = netdev_priv(ndev);
253 struct can_bittiming *bt = &priv->can.bittiming;
254 u32 btr0, btr1;
255 u32 is_config_mode;
256
257 /* Check whether Xilinx CAN is in configuration mode.
258 * It cannot set bit timing if Xilinx CAN is not in configuration mode.
259 */
260 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
261 XCAN_SR_CONFIG_MASK;
262 if (!is_config_mode) {
263 netdev_alert(ndev,
264 "BUG! Cannot set bittiming - CAN is not in config mode\n");
265 return -EPERM;
266 }
267
268 /* Setting Baud Rate prescalar value in BRPR Register */
269 btr0 = (bt->brp - 1);
270
271 /* Setting Time Segment 1 in BTR Register */
272 btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
273
274 /* Setting Time Segment 2 in BTR Register */
275 btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT;
276
277 /* Setting Synchronous jump width in BTR Register */
278 btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT;
279
280 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
281 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
282
283 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
284 priv->read_reg(priv, XCAN_BRPR_OFFSET),
285 priv->read_reg(priv, XCAN_BTR_OFFSET));
286
287 return 0;
288}
289
290/**
291 * xcan_chip_start - This the drivers start routine
292 * @ndev: Pointer to net_device structure
293 *
294 * This is the drivers start routine.
295 * Based on the State of the CAN device it puts
296 * the CAN device into a proper mode.
297 *
298 * Return: 0 on success and failure value on error
299 */
300static int xcan_chip_start(struct net_device *ndev)
301{
302 struct xcan_priv *priv = netdev_priv(ndev);
303 u32 err, reg_msr, reg_sr_mask;
304 unsigned long timeout;
305
306 /* Check if it is in reset mode */
307 err = set_reset_mode(ndev);
308 if (err < 0)
309 return err;
310
311 err = xcan_set_bittiming(ndev);
312 if (err < 0)
313 return err;
314
315 /* Enable interrupts */
316 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);
317
318 /* Check whether it is loopback mode or normal mode */
319 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
320 reg_msr = XCAN_MSR_LBACK_MASK;
321 reg_sr_mask = XCAN_SR_LBACK_MASK;
322 } else {
323 reg_msr = 0x0;
324 reg_sr_mask = XCAN_SR_NORMAL_MASK;
325 }
326
327 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
328 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
329
330 timeout = jiffies + XCAN_TIMEOUT;
331 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
332 if (time_after(jiffies, timeout)) {
333 netdev_warn(ndev,
334 "timed out for correct mode\n");
335 return -ETIMEDOUT;
336 }
337 }
338 netdev_dbg(ndev, "status:#x%08x\n",
339 priv->read_reg(priv, XCAN_SR_OFFSET));
340
341 priv->can.state = CAN_STATE_ERROR_ACTIVE;
342 return 0;
343}
344
345/**
346 * xcan_do_set_mode - This sets the mode of the driver
347 * @ndev: Pointer to net_device structure
348 * @mode: Tells the mode of the driver
349 *
350 * This check the drivers state and calls the
351 * the corresponding modes to set.
352 *
353 * Return: 0 on success and failure value on error
354 */
355static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
356{
357 int ret;
358
359 switch (mode) {
360 case CAN_MODE_START:
361 ret = xcan_chip_start(ndev);
362 if (ret < 0) {
363 netdev_err(ndev, "xcan_chip_start failed!\n");
364 return ret;
365 }
366 netif_wake_queue(ndev);
367 break;
368 default:
369 ret = -EOPNOTSUPP;
370 break;
371 }
372
373 return ret;
374}
375
376/**
377 * xcan_start_xmit - Starts the transmission
378 * @skb: sk_buff pointer that contains data to be Txed
379 * @ndev: Pointer to net_device structure
380 *
381 * This function is invoked from upper layers to initiate transmission. This
382 * function uses the next available free txbuff and populates their fields to
383 * start the transmission.
384 *
385 * Return: 0 on success and failure value on error
386 */
387static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
388{
389 struct xcan_priv *priv = netdev_priv(ndev);
390 struct net_device_stats *stats = &ndev->stats;
391 struct can_frame *cf = (struct can_frame *)skb->data;
392 u32 id, dlc, data[2] = {0, 0};
393
394 if (can_dropped_invalid_skb(ndev, skb))
395 return NETDEV_TX_OK;
396
397 /* Check if the TX buffer is full */
398 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
399 XCAN_SR_TXFLL_MASK)) {
400 netif_stop_queue(ndev);
401 netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n");
402 return NETDEV_TX_BUSY;
403 }
404
405 /* Watch carefully on the bit sequence */
406 if (cf->can_id & CAN_EFF_FLAG) {
407 /* Extended CAN ID format */
408 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
409 XCAN_IDR_ID2_MASK;
410 id |= (((cf->can_id & CAN_EFF_MASK) >>
411 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
412 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
413
414 /* The substibute remote TX request bit should be "1"
415 * for extended frames as in the Xilinx CAN datasheet
416 */
417 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
418
419 if (cf->can_id & CAN_RTR_FLAG)
420 /* Extended frames remote TX request */
421 id |= XCAN_IDR_RTR_MASK;
422 } else {
423 /* Standard CAN ID format */
424 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
425 XCAN_IDR_ID1_MASK;
426
427 if (cf->can_id & CAN_RTR_FLAG)
428 /* Standard frames remote TX request */
429 id |= XCAN_IDR_SRR_MASK;
430 }
431
432 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
433
434 if (cf->can_dlc > 0)
435 data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
436 if (cf->can_dlc > 4)
437 data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
438
439 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
440 priv->tx_head++;
441
442 /* Write the Frame to Xilinx CAN TX FIFO */
443 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);
444 /* If the CAN frame is RTR frame this write triggers tranmission */
445 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);
446 if (!(cf->can_id & CAN_RTR_FLAG)) {
447 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);
448 /* If the CAN frame is Standard/Extended frame this
449 * write triggers tranmission
450 */
451 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);
452 stats->tx_bytes += cf->can_dlc;
453 }
454
455 /* Check if the TX buffer is full */
456 if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
457 netif_stop_queue(ndev);
458
459 return NETDEV_TX_OK;
460}
461
462/**
463 * xcan_rx - Is called from CAN isr to complete the received
464 * frame processing
465 * @ndev: Pointer to net_device structure
466 *
467 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
468 * does minimal processing and invokes "netif_receive_skb" to complete further
469 * processing.
470 * Return: 1 on success and 0 on failure.
471 */
472static int xcan_rx(struct net_device *ndev)
473{
474 struct xcan_priv *priv = netdev_priv(ndev);
475 struct net_device_stats *stats = &ndev->stats;
476 struct can_frame *cf;
477 struct sk_buff *skb;
478 u32 id_xcan, dlc, data[2] = {0, 0};
479
480 skb = alloc_can_skb(ndev, &cf);
481 if (unlikely(!skb)) {
482 stats->rx_dropped++;
483 return 0;
484 }
485
486 /* Read a frame from Xilinx zynq CANPS */
487 id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET);
488 dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >>
489 XCAN_DLCR_DLC_SHIFT;
490
491 /* Change Xilinx CAN data length format to socketCAN data format */
492 cf->can_dlc = get_can_dlc(dlc);
493
494 /* Change Xilinx CAN ID format to socketCAN ID format */
495 if (id_xcan & XCAN_IDR_IDE_MASK) {
496 /* The received frame is an Extended format frame */
497 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
498 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
499 XCAN_IDR_ID2_SHIFT;
500 cf->can_id |= CAN_EFF_FLAG;
501 if (id_xcan & XCAN_IDR_RTR_MASK)
502 cf->can_id |= CAN_RTR_FLAG;
503 } else {
504 /* The received frame is a standard format frame */
505 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
506 XCAN_IDR_ID1_SHIFT;
507 if (id_xcan & XCAN_IDR_SRR_MASK)
508 cf->can_id |= CAN_RTR_FLAG;
509 }
510
511 if (!(id_xcan & XCAN_IDR_SRR_MASK)) {
512 data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET);
513 data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET);
514
515 /* Change Xilinx CAN data format to socketCAN data format */
516 if (cf->can_dlc > 0)
517 *(__be32 *)(cf->data) = cpu_to_be32(data[0]);
518 if (cf->can_dlc > 4)
519 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
520 }
521
522 stats->rx_bytes += cf->can_dlc;
523 stats->rx_packets++;
524 netif_receive_skb(skb);
525
526 return 1;
527}
528
529/**
530 * xcan_err_interrupt - error frame Isr
531 * @ndev: net_device pointer
532 * @isr: interrupt status register value
533 *
534 * This is the CAN error interrupt and it will
535 * check the the type of error and forward the error
536 * frame to upper layers.
537 */
538static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
539{
540 struct xcan_priv *priv = netdev_priv(ndev);
541 struct net_device_stats *stats = &ndev->stats;
542 struct can_frame *cf;
543 struct sk_buff *skb;
544 u32 err_status, status, txerr = 0, rxerr = 0;
545
546 skb = alloc_can_err_skb(ndev, &cf);
547
548 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
549 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
550 txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
551 rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
552 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
553 status = priv->read_reg(priv, XCAN_SR_OFFSET);
554
555 if (isr & XCAN_IXR_BSOFF_MASK) {
556 priv->can.state = CAN_STATE_BUS_OFF;
557 priv->can.can_stats.bus_off++;
558 /* Leave device in Config Mode in bus-off state */
559 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
560 can_bus_off(ndev);
561 if (skb)
562 cf->can_id |= CAN_ERR_BUSOFF;
563 } else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) {
564 priv->can.state = CAN_STATE_ERROR_PASSIVE;
565 priv->can.can_stats.error_passive++;
566 if (skb) {
567 cf->can_id |= CAN_ERR_CRTL;
568 cf->data[1] = (rxerr > 127) ?
569 CAN_ERR_CRTL_RX_PASSIVE :
570 CAN_ERR_CRTL_TX_PASSIVE;
571 cf->data[6] = txerr;
572 cf->data[7] = rxerr;
573 }
574 } else if (status & XCAN_SR_ERRWRN_MASK) {
575 priv->can.state = CAN_STATE_ERROR_WARNING;
576 priv->can.can_stats.error_warning++;
577 if (skb) {
578 cf->can_id |= CAN_ERR_CRTL;
579 cf->data[1] |= (txerr > rxerr) ?
580 CAN_ERR_CRTL_TX_WARNING :
581 CAN_ERR_CRTL_RX_WARNING;
582 cf->data[6] = txerr;
583 cf->data[7] = rxerr;
584 }
585 }
586
587 /* Check for Arbitration lost interrupt */
588 if (isr & XCAN_IXR_ARBLST_MASK) {
589 priv->can.can_stats.arbitration_lost++;
590 if (skb) {
591 cf->can_id |= CAN_ERR_LOSTARB;
592 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
593 }
594 }
595
596 /* Check for RX FIFO Overflow interrupt */
597 if (isr & XCAN_IXR_RXOFLW_MASK) {
598 stats->rx_over_errors++;
599 stats->rx_errors++;
600 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
601 if (skb) {
602 cf->can_id |= CAN_ERR_CRTL;
603 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
604 }
605 }
606
607 /* Check for error interrupt */
608 if (isr & XCAN_IXR_ERROR_MASK) {
609 if (skb) {
610 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
611 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
612 }
613
614 /* Check for Ack error interrupt */
615 if (err_status & XCAN_ESR_ACKER_MASK) {
616 stats->tx_errors++;
617 if (skb) {
618 cf->can_id |= CAN_ERR_ACK;
619 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
620 }
621 }
622
623 /* Check for Bit error interrupt */
624 if (err_status & XCAN_ESR_BERR_MASK) {
625 stats->tx_errors++;
626 if (skb) {
627 cf->can_id |= CAN_ERR_PROT;
628 cf->data[2] = CAN_ERR_PROT_BIT;
629 }
630 }
631
632 /* Check for Stuff error interrupt */
633 if (err_status & XCAN_ESR_STER_MASK) {
634 stats->rx_errors++;
635 if (skb) {
636 cf->can_id |= CAN_ERR_PROT;
637 cf->data[2] = CAN_ERR_PROT_STUFF;
638 }
639 }
640
641 /* Check for Form error interrupt */
642 if (err_status & XCAN_ESR_FMER_MASK) {
643 stats->rx_errors++;
644 if (skb) {
645 cf->can_id |= CAN_ERR_PROT;
646 cf->data[2] = CAN_ERR_PROT_FORM;
647 }
648 }
649
650 /* Check for CRC error interrupt */
651 if (err_status & XCAN_ESR_CRCER_MASK) {
652 stats->rx_errors++;
653 if (skb) {
654 cf->can_id |= CAN_ERR_PROT;
655 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ |
656 CAN_ERR_PROT_LOC_CRC_DEL;
657 }
658 }
659 priv->can.can_stats.bus_error++;
660 }
661
662 if (skb) {
663 stats->rx_packets++;
664 stats->rx_bytes += cf->can_dlc;
665 netif_rx(skb);
666 }
667
668 netdev_dbg(ndev, "%s: error status register:0x%x\n",
669 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
670}
671
672/**
673 * xcan_state_interrupt - It will check the state of the CAN device
674 * @ndev: net_device pointer
675 * @isr: interrupt status register value
676 *
677 * This will checks the state of the CAN device
678 * and puts the device into appropriate state.
679 */
680static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
681{
682 struct xcan_priv *priv = netdev_priv(ndev);
683
684 /* Check for Sleep interrupt if set put CAN device in sleep state */
685 if (isr & XCAN_IXR_SLP_MASK)
686 priv->can.state = CAN_STATE_SLEEPING;
687
688 /* Check for Wake up interrupt if set put CAN device in Active state */
689 if (isr & XCAN_IXR_WKUP_MASK)
690 priv->can.state = CAN_STATE_ERROR_ACTIVE;
691}
692
693/**
694 * xcan_rx_poll - Poll routine for rx packets (NAPI)
695 * @napi: napi structure pointer
696 * @quota: Max number of rx packets to be processed.
697 *
698 * This is the poll routine for rx part.
699 * It will process the packets maximux quota value.
700 *
701 * Return: number of packets received
702 */
703static int xcan_rx_poll(struct napi_struct *napi, int quota)
704{
705 struct net_device *ndev = napi->dev;
706 struct xcan_priv *priv = netdev_priv(ndev);
707 u32 isr, ier;
708 int work_done = 0;
709
710 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
711 while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
712 if (isr & XCAN_IXR_RXOK_MASK) {
713 priv->write_reg(priv, XCAN_ICR_OFFSET,
714 XCAN_IXR_RXOK_MASK);
715 work_done += xcan_rx(ndev);
716 } else {
717 priv->write_reg(priv, XCAN_ICR_OFFSET,
718 XCAN_IXR_RXNEMP_MASK);
719 break;
720 }
721 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
722 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
723 }
724
725 if (work_done)
726 can_led_event(ndev, CAN_LED_EVENT_RX);
727
728 if (work_done < quota) {
729 napi_complete(napi);
730 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
731 ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK);
732 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
733 }
734 return work_done;
735}
736
737/**
738 * xcan_tx_interrupt - Tx Done Isr
739 * @ndev: net_device pointer
740 * @isr: Interrupt status register value
741 */
742static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
743{
744 struct xcan_priv *priv = netdev_priv(ndev);
745 struct net_device_stats *stats = &ndev->stats;
746
747 while ((priv->tx_head - priv->tx_tail > 0) &&
748 (isr & XCAN_IXR_TXOK_MASK)) {
749 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
750 can_get_echo_skb(ndev, priv->tx_tail %
751 priv->tx_max);
752 priv->tx_tail++;
753 stats->tx_packets++;
754 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
755 }
756 can_led_event(ndev, CAN_LED_EVENT_TX);
757 netif_wake_queue(ndev);
758}
759
760/**
761 * xcan_interrupt - CAN Isr
762 * @irq: irq number
763 * @dev_id: device id poniter
764 *
765 * This is the xilinx CAN Isr. It checks for the type of interrupt
766 * and invokes the corresponding ISR.
767 *
768 * Return:
769 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
770 */
771static irqreturn_t xcan_interrupt(int irq, void *dev_id)
772{
773 struct net_device *ndev = (struct net_device *)dev_id;
774 struct xcan_priv *priv = netdev_priv(ndev);
775 u32 isr, ier;
776
777 /* Get the interrupt status from Xilinx CAN */
778 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
779 if (!isr)
780 return IRQ_NONE;
781
782 /* Check for the type of interrupt and Processing it */
783 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
784 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
785 XCAN_IXR_WKUP_MASK));
786 xcan_state_interrupt(ndev, isr);
787 }
788
789 /* Check for Tx interrupt and Processing it */
790 if (isr & XCAN_IXR_TXOK_MASK)
791 xcan_tx_interrupt(ndev, isr);
792
793 /* Check for the type of error interrupt and Processing it */
794 if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
795 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
796 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
797 XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
798 XCAN_IXR_ARBLST_MASK));
799 xcan_err_interrupt(ndev, isr);
800 }
801
802 /* Check for the type of receive interrupt and Processing it */
803 if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) {
804 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
805 ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK);
806 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
807 napi_schedule(&priv->napi);
808 }
809 return IRQ_HANDLED;
810}
811
812/**
813 * xcan_chip_stop - Driver stop routine
814 * @ndev: Pointer to net_device structure
815 *
816 * This is the drivers stop routine. It will disable the
817 * interrupts and put the device into configuration mode.
818 */
819static void xcan_chip_stop(struct net_device *ndev)
820{
821 struct xcan_priv *priv = netdev_priv(ndev);
822 u32 ier;
823
824 /* Disable interrupts and leave the can in configuration mode */
825 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
826 ier &= ~XCAN_INTR_ALL;
827 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
828 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
829 priv->can.state = CAN_STATE_STOPPED;
830}
831
832/**
833 * xcan_open - Driver open routine
834 * @ndev: Pointer to net_device structure
835 *
836 * This is the driver open routine.
837 * Return: 0 on success and failure value on error
838 */
839static int xcan_open(struct net_device *ndev)
840{
841 struct xcan_priv *priv = netdev_priv(ndev);
842 int ret;
843
844 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
845 ndev->name, ndev);
846 if (ret < 0) {
847 netdev_err(ndev, "irq allocation for CAN failed\n");
848 goto err;
849 }
850
851 ret = clk_prepare_enable(priv->can_clk);
852 if (ret) {
853 netdev_err(ndev, "unable to enable device clock\n");
854 goto err_irq;
855 }
856
857 ret = clk_prepare_enable(priv->bus_clk);
858 if (ret) {
859 netdev_err(ndev, "unable to enable bus clock\n");
860 goto err_can_clk;
861 }
862
863 /* Set chip into reset mode */
864 ret = set_reset_mode(ndev);
865 if (ret < 0) {
866 netdev_err(ndev, "mode resetting failed!\n");
867 goto err_bus_clk;
868 }
869
870 /* Common open */
871 ret = open_candev(ndev);
872 if (ret)
873 goto err_bus_clk;
874
875 ret = xcan_chip_start(ndev);
876 if (ret < 0) {
877 netdev_err(ndev, "xcan_chip_start failed!\n");
878 goto err_candev;
879 }
880
881 can_led_event(ndev, CAN_LED_EVENT_OPEN);
882 napi_enable(&priv->napi);
883 netif_start_queue(ndev);
884
885 return 0;
886
887err_candev:
888 close_candev(ndev);
889err_bus_clk:
890 clk_disable_unprepare(priv->bus_clk);
891err_can_clk:
892 clk_disable_unprepare(priv->can_clk);
893err_irq:
894 free_irq(ndev->irq, ndev);
895err:
896 return ret;
897}
898
899/**
900 * xcan_close - Driver close routine
901 * @ndev: Pointer to net_device structure
902 *
903 * Return: 0 always
904 */
905static int xcan_close(struct net_device *ndev)
906{
907 struct xcan_priv *priv = netdev_priv(ndev);
908
909 netif_stop_queue(ndev);
910 napi_disable(&priv->napi);
911 xcan_chip_stop(ndev);
912 clk_disable_unprepare(priv->bus_clk);
913 clk_disable_unprepare(priv->can_clk);
914 free_irq(ndev->irq, ndev);
915 close_candev(ndev);
916
917 can_led_event(ndev, CAN_LED_EVENT_STOP);
918
919 return 0;
920}
921
922/**
923 * xcan_get_berr_counter - error counter routine
924 * @ndev: Pointer to net_device structure
925 * @bec: Pointer to can_berr_counter structure
926 *
927 * This is the driver error counter routine.
928 * Return: 0 on success and failure value on error
929 */
930static int xcan_get_berr_counter(const struct net_device *ndev,
931 struct can_berr_counter *bec)
932{
933 struct xcan_priv *priv = netdev_priv(ndev);
934 int ret;
935
936 ret = clk_prepare_enable(priv->can_clk);
937 if (ret)
938 goto err;
939
940 ret = clk_prepare_enable(priv->bus_clk);
941 if (ret)
942 goto err_clk;
943
944 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
945 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
946 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
947
948 clk_disable_unprepare(priv->bus_clk);
949 clk_disable_unprepare(priv->can_clk);
950
951 return 0;
952
953err_clk:
954 clk_disable_unprepare(priv->can_clk);
955err:
956 return ret;
957}
958
959
960static const struct net_device_ops xcan_netdev_ops = {
961 .ndo_open = xcan_open,
962 .ndo_stop = xcan_close,
963 .ndo_start_xmit = xcan_start_xmit,
964};
965
966/**
967 * xcan_suspend - Suspend method for the driver
968 * @dev: Address of the platform_device structure
969 *
970 * Put the driver into low power mode.
971 * Return: 0 always
972 */
973static int __maybe_unused xcan_suspend(struct device *dev)
974{
975 struct platform_device *pdev = dev_get_drvdata(dev);
976 struct net_device *ndev = platform_get_drvdata(pdev);
977 struct xcan_priv *priv = netdev_priv(ndev);
978
979 if (netif_running(ndev)) {
980 netif_stop_queue(ndev);
981 netif_device_detach(ndev);
982 }
983
984 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);
985 priv->can.state = CAN_STATE_SLEEPING;
986
987 clk_disable(priv->bus_clk);
988 clk_disable(priv->can_clk);
989
990 return 0;
991}
992
993/**
994 * xcan_resume - Resume from suspend
995 * @dev: Address of the platformdevice structure
996 *
997 * Resume operation after suspend.
998 * Return: 0 on success and failure value on error
999 */
1000static int __maybe_unused xcan_resume(struct device *dev)
1001{
1002 struct platform_device *pdev = dev_get_drvdata(dev);
1003 struct net_device *ndev = platform_get_drvdata(pdev);
1004 struct xcan_priv *priv = netdev_priv(ndev);
1005 int ret;
1006
1007 ret = clk_enable(priv->bus_clk);
1008 if (ret) {
1009 dev_err(dev, "Cannot enable clock.\n");
1010 return ret;
1011 }
1012 ret = clk_enable(priv->can_clk);
1013 if (ret) {
1014 dev_err(dev, "Cannot enable clock.\n");
1015 clk_disable_unprepare(priv->bus_clk);
1016 return ret;
1017 }
1018
1019 priv->write_reg(priv, XCAN_MSR_OFFSET, 0);
1020 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
1021 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1022
1023 if (netif_running(ndev)) {
1024 netif_device_attach(ndev);
1025 netif_start_queue(ndev);
1026 }
1027
1028 return 0;
1029}
1030
1031static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume);
1032
1033/**
1034 * xcan_probe - Platform registration call
1035 * @pdev: Handle to the platform device structure
1036 *
1037 * This function does all the memory allocation and registration for the CAN
1038 * device.
1039 *
1040 * Return: 0 on success and failure value on error
1041 */
1042static int xcan_probe(struct platform_device *pdev)
1043{
1044 struct resource *res; /* IO mem resources */
1045 struct net_device *ndev;
1046 struct xcan_priv *priv;
1047 void __iomem *addr;
1048 int ret, rx_max, tx_max;
1049
1050 /* Get the virtual base address for the device */
1051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1052 addr = devm_ioremap_resource(&pdev->dev, res);
1053 if (IS_ERR(addr)) {
1054 ret = PTR_ERR(addr);
1055 goto err;
1056 }
1057
1058 ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max);
1059 if (ret < 0)
1060 goto err;
1061
1062 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max);
1063 if (ret < 0)
1064 goto err;
1065
1066 /* Create a CAN device instance */
1067 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
1068 if (!ndev)
1069 return -ENOMEM;
1070
1071 priv = netdev_priv(ndev);
1072 priv->dev = ndev;
1073 priv->can.bittiming_const = &xcan_bittiming_const;
1074 priv->can.do_set_mode = xcan_do_set_mode;
1075 priv->can.do_get_berr_counter = xcan_get_berr_counter;
1076 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1077 CAN_CTRLMODE_BERR_REPORTING;
1078 priv->reg_base = addr;
1079 priv->tx_max = tx_max;
1080
1081 /* Get IRQ for the device */
1082 ndev->irq = platform_get_irq(pdev, 0);
1083 ndev->flags |= IFF_ECHO; /* We support local echo */
1084
1085 platform_set_drvdata(pdev, ndev);
1086 SET_NETDEV_DEV(ndev, &pdev->dev);
1087 ndev->netdev_ops = &xcan_netdev_ops;
1088
1089 /* Getting the CAN can_clk info */
1090 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1091 if (IS_ERR(priv->can_clk)) {
1092 dev_err(&pdev->dev, "Device clock not found.\n");
1093 ret = PTR_ERR(priv->can_clk);
1094 goto err_free;
1095 }
1096 /* Check for type of CAN device */
1097 if (of_device_is_compatible(pdev->dev.of_node,
1098 "xlnx,zynq-can-1.0")) {
1099 priv->bus_clk = devm_clk_get(&pdev->dev, "pclk");
1100 if (IS_ERR(priv->bus_clk)) {
1101 dev_err(&pdev->dev, "bus clock not found\n");
1102 ret = PTR_ERR(priv->bus_clk);
1103 goto err_free;
1104 }
1105 } else {
1106 priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
1107 if (IS_ERR(priv->bus_clk)) {
1108 dev_err(&pdev->dev, "bus clock not found\n");
1109 ret = PTR_ERR(priv->bus_clk);
1110 goto err_free;
1111 }
1112 }
1113
1114 ret = clk_prepare_enable(priv->can_clk);
1115 if (ret) {
1116 dev_err(&pdev->dev, "unable to enable device clock\n");
1117 goto err_free;
1118 }
1119
1120 ret = clk_prepare_enable(priv->bus_clk);
1121 if (ret) {
1122 dev_err(&pdev->dev, "unable to enable bus clock\n");
1123 goto err_unprepare_disable_dev;
1124 }
1125
1126 priv->write_reg = xcan_write_reg_le;
1127 priv->read_reg = xcan_read_reg_le;
1128
1129 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
1130 priv->write_reg = xcan_write_reg_be;
1131 priv->read_reg = xcan_read_reg_be;
1132 }
1133
1134 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1135
1136 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
1137
1138 ret = register_candev(ndev);
1139 if (ret) {
1140 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
1141 goto err_unprepare_disable_busclk;
1142 }
1143
1144 devm_can_led_init(ndev);
1145 clk_disable_unprepare(priv->bus_clk);
1146 clk_disable_unprepare(priv->can_clk);
1147 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
1148 priv->reg_base, ndev->irq, priv->can.clock.freq,
1149 priv->tx_max);
1150
1151 return 0;
1152
1153err_unprepare_disable_busclk:
1154 clk_disable_unprepare(priv->bus_clk);
1155err_unprepare_disable_dev:
1156 clk_disable_unprepare(priv->can_clk);
1157err_free:
1158 free_candev(ndev);
1159err:
1160 return ret;
1161}
1162
1163/**
1164 * xcan_remove - Unregister the device after releasing the resources
1165 * @pdev: Handle to the platform device structure
1166 *
1167 * This function frees all the resources allocated to the device.
1168 * Return: 0 always
1169 */
1170static int xcan_remove(struct platform_device *pdev)
1171{
1172 struct net_device *ndev = platform_get_drvdata(pdev);
1173 struct xcan_priv *priv = netdev_priv(ndev);
1174
1175 if (set_reset_mode(ndev) < 0)
1176 netdev_err(ndev, "mode resetting failed!\n");
1177
1178 unregister_candev(ndev);
1179 netif_napi_del(&priv->napi);
1180 free_candev(ndev);
1181
1182 return 0;
1183}
1184
1185/* Match table for OF platform binding */
1186static struct of_device_id xcan_of_match[] = {
1187 { .compatible = "xlnx,zynq-can-1.0", },
1188 { .compatible = "xlnx,axi-can-1.00.a", },
1189 { /* end of list */ },
1190};
1191MODULE_DEVICE_TABLE(of, xcan_of_match);
1192
1193static struct platform_driver xcan_driver = {
1194 .probe = xcan_probe,
1195 .remove = xcan_remove,
1196 .driver = {
1197 .owner = THIS_MODULE,
1198 .name = DRIVER_NAME,
1199 .pm = &xcan_dev_pm_ops,
1200 .of_match_table = xcan_of_match,
1201 },
1202};
1203
1204module_platform_driver(xcan_driver);
1205
1206MODULE_LICENSE("GPL");
1207MODULE_AUTHOR("Xilinx Inc");
1208MODULE_DESCRIPTION("Xilinx CAN interface");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 03:27:31 -0500