diff options
Diffstat (limited to 'drivers/net/can')
-rw-r--r-- | drivers/net/can/bfin_can.c | 126 |
1 files changed, 60 insertions, 66 deletions
diff --git a/drivers/net/can/bfin_can.c b/drivers/net/can/bfin_can.c index e7a6363e736b..9cbf615e5673 100644 --- a/drivers/net/can/bfin_can.c +++ b/drivers/net/can/bfin_can.c | |||
@@ -78,8 +78,8 @@ static int bfin_can_set_bittiming(struct net_device *dev) | |||
78 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) | 78 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) |
79 | timing |= SAM; | 79 | timing |= SAM; |
80 | 80 | ||
81 | bfin_write(®->clock, clk); | 81 | writew(clk, ®->clock); |
82 | bfin_write(®->timing, timing); | 82 | writew(timing, ®->timing); |
83 | 83 | ||
84 | netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing); | 84 | netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing); |
85 | 85 | ||
@@ -94,16 +94,14 @@ static void bfin_can_set_reset_mode(struct net_device *dev) | |||
94 | int i; | 94 | int i; |
95 | 95 | ||
96 | /* disable interrupts */ | 96 | /* disable interrupts */ |
97 | bfin_write(®->mbim1, 0); | 97 | writew(0, ®->mbim1); |
98 | bfin_write(®->mbim2, 0); | 98 | writew(0, ®->mbim2); |
99 | bfin_write(®->gim, 0); | 99 | writew(0, ®->gim); |
100 | 100 | ||
101 | /* reset can and enter configuration mode */ | 101 | /* reset can and enter configuration mode */ |
102 | bfin_write(®->control, SRS | CCR); | 102 | writew(SRS | CCR, ®->control); |
103 | SSYNC(); | 103 | writew(CCR, ®->control); |
104 | bfin_write(®->control, CCR); | 104 | while (!(readw(®->control) & CCA)) { |
105 | SSYNC(); | ||
106 | while (!(bfin_read(®->control) & CCA)) { | ||
107 | udelay(10); | 105 | udelay(10); |
108 | if (--timeout == 0) { | 106 | if (--timeout == 0) { |
109 | netdev_err(dev, "fail to enter configuration mode\n"); | 107 | netdev_err(dev, "fail to enter configuration mode\n"); |
@@ -116,34 +114,33 @@ static void bfin_can_set_reset_mode(struct net_device *dev) | |||
116 | * by writing to CAN Mailbox Configuration Registers 1 and 2 | 114 | * by writing to CAN Mailbox Configuration Registers 1 and 2 |
117 | * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled | 115 | * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled |
118 | */ | 116 | */ |
119 | bfin_write(®->mc1, 0); | 117 | writew(0, ®->mc1); |
120 | bfin_write(®->mc2, 0); | 118 | writew(0, ®->mc2); |
121 | 119 | ||
122 | /* Set Mailbox Direction */ | 120 | /* Set Mailbox Direction */ |
123 | bfin_write(®->md1, 0xFFFF); /* mailbox 1-16 are RX */ | 121 | writew(0xFFFF, ®->md1); /* mailbox 1-16 are RX */ |
124 | bfin_write(®->md2, 0); /* mailbox 17-32 are TX */ | 122 | writew(0, ®->md2); /* mailbox 17-32 are TX */ |
125 | 123 | ||
126 | /* RECEIVE_STD_CHL */ | 124 | /* RECEIVE_STD_CHL */ |
127 | for (i = 0; i < 2; i++) { | 125 | for (i = 0; i < 2; i++) { |
128 | bfin_write(®->chl[RECEIVE_STD_CHL + i].id0, 0); | 126 | writew(0, ®->chl[RECEIVE_STD_CHL + i].id0); |
129 | bfin_write(®->chl[RECEIVE_STD_CHL + i].id1, AME); | 127 | writew(AME, ®->chl[RECEIVE_STD_CHL + i].id1); |
130 | bfin_write(®->chl[RECEIVE_STD_CHL + i].dlc, 0); | 128 | writew(0, ®->chl[RECEIVE_STD_CHL + i].dlc); |
131 | bfin_write(®->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF); | 129 | writew(0x1FFF, ®->msk[RECEIVE_STD_CHL + i].amh); |
132 | bfin_write(®->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF); | 130 | writew(0xFFFF, ®->msk[RECEIVE_STD_CHL + i].aml); |
133 | } | 131 | } |
134 | 132 | ||
135 | /* RECEIVE_EXT_CHL */ | 133 | /* RECEIVE_EXT_CHL */ |
136 | for (i = 0; i < 2; i++) { | 134 | for (i = 0; i < 2; i++) { |
137 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].id0, 0); | 135 | writew(0, ®->chl[RECEIVE_EXT_CHL + i].id0); |
138 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE); | 136 | writew(AME | IDE, ®->chl[RECEIVE_EXT_CHL + i].id1); |
139 | bfin_write(®->chl[RECEIVE_EXT_CHL + i].dlc, 0); | 137 | writew(0, ®->chl[RECEIVE_EXT_CHL + i].dlc); |
140 | bfin_write(®->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF); | 138 | writew(0x1FFF, ®->msk[RECEIVE_EXT_CHL + i].amh); |
141 | bfin_write(®->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF); | 139 | writew(0xFFFF, ®->msk[RECEIVE_EXT_CHL + i].aml); |
142 | } | 140 | } |
143 | 141 | ||
144 | bfin_write(®->mc2, BIT(TRANSMIT_CHL - 16)); | 142 | writew(BIT(TRANSMIT_CHL - 16), ®->mc2); |
145 | bfin_write(®->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); | 143 | writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mc1); |
146 | SSYNC(); | ||
147 | 144 | ||
148 | priv->can.state = CAN_STATE_STOPPED; | 145 | priv->can.state = CAN_STATE_STOPPED; |
149 | } | 146 | } |
@@ -157,9 +154,9 @@ static void bfin_can_set_normal_mode(struct net_device *dev) | |||
157 | /* | 154 | /* |
158 | * leave configuration mode | 155 | * leave configuration mode |
159 | */ | 156 | */ |
160 | bfin_write(®->control, bfin_read(®->control) & ~CCR); | 157 | writew(readw(®->control) & ~CCR, ®->control); |
161 | 158 | ||
162 | while (bfin_read(®->status) & CCA) { | 159 | while (readw(®->status) & CCA) { |
163 | udelay(10); | 160 | udelay(10); |
164 | if (--timeout == 0) { | 161 | if (--timeout == 0) { |
165 | netdev_err(dev, "fail to leave configuration mode\n"); | 162 | netdev_err(dev, "fail to leave configuration mode\n"); |
@@ -170,26 +167,25 @@ static void bfin_can_set_normal_mode(struct net_device *dev) | |||
170 | /* | 167 | /* |
171 | * clear _All_ tx and rx interrupts | 168 | * clear _All_ tx and rx interrupts |
172 | */ | 169 | */ |
173 | bfin_write(®->mbtif1, 0xFFFF); | 170 | writew(0xFFFF, ®->mbtif1); |
174 | bfin_write(®->mbtif2, 0xFFFF); | 171 | writew(0xFFFF, ®->mbtif2); |
175 | bfin_write(®->mbrif1, 0xFFFF); | 172 | writew(0xFFFF, ®->mbrif1); |
176 | bfin_write(®->mbrif2, 0xFFFF); | 173 | writew(0xFFFF, ®->mbrif2); |
177 | 174 | ||
178 | /* | 175 | /* |
179 | * clear global interrupt status register | 176 | * clear global interrupt status register |
180 | */ | 177 | */ |
181 | bfin_write(®->gis, 0x7FF); /* overwrites with '1' */ | 178 | writew(0x7FF, ®->gis); /* overwrites with '1' */ |
182 | 179 | ||
183 | /* | 180 | /* |
184 | * Initialize Interrupts | 181 | * Initialize Interrupts |
185 | * - set bits in the mailbox interrupt mask register | 182 | * - set bits in the mailbox interrupt mask register |
186 | * - global interrupt mask | 183 | * - global interrupt mask |
187 | */ | 184 | */ |
188 | bfin_write(®->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); | 185 | writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mbim1); |
189 | bfin_write(®->mbim2, BIT(TRANSMIT_CHL - 16)); | 186 | writew(BIT(TRANSMIT_CHL - 16), ®->mbim2); |
190 | 187 | ||
191 | bfin_write(®->gim, EPIM | BOIM | RMLIM); | 188 | writew(EPIM | BOIM | RMLIM, ®->gim); |
192 | SSYNC(); | ||
193 | } | 189 | } |
194 | 190 | ||
195 | static void bfin_can_start(struct net_device *dev) | 191 | static void bfin_can_start(struct net_device *dev) |
@@ -226,7 +222,7 @@ static int bfin_can_get_berr_counter(const struct net_device *dev, | |||
226 | struct bfin_can_priv *priv = netdev_priv(dev); | 222 | struct bfin_can_priv *priv = netdev_priv(dev); |
227 | struct bfin_can_regs __iomem *reg = priv->membase; | 223 | struct bfin_can_regs __iomem *reg = priv->membase; |
228 | 224 | ||
229 | u16 cec = bfin_read(®->cec); | 225 | u16 cec = readw(®->cec); |
230 | 226 | ||
231 | bec->txerr = cec >> 8; | 227 | bec->txerr = cec >> 8; |
232 | bec->rxerr = cec; | 228 | bec->rxerr = cec; |
@@ -252,28 +248,28 @@ static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
252 | 248 | ||
253 | /* fill id */ | 249 | /* fill id */ |
254 | if (id & CAN_EFF_FLAG) { | 250 | if (id & CAN_EFF_FLAG) { |
255 | bfin_write(®->chl[TRANSMIT_CHL].id0, id); | 251 | writew(id, ®->chl[TRANSMIT_CHL].id0); |
256 | val = ((id & 0x1FFF0000) >> 16) | IDE; | 252 | val = ((id & 0x1FFF0000) >> 16) | IDE; |
257 | } else | 253 | } else |
258 | val = (id << 2); | 254 | val = (id << 2); |
259 | if (id & CAN_RTR_FLAG) | 255 | if (id & CAN_RTR_FLAG) |
260 | val |= RTR; | 256 | val |= RTR; |
261 | bfin_write(®->chl[TRANSMIT_CHL].id1, val | AME); | 257 | writew(val | AME, ®->chl[TRANSMIT_CHL].id1); |
262 | 258 | ||
263 | /* fill payload */ | 259 | /* fill payload */ |
264 | for (i = 0; i < 8; i += 2) { | 260 | for (i = 0; i < 8; i += 2) { |
265 | val = ((7 - i) < dlc ? (data[7 - i]) : 0) + | 261 | val = ((7 - i) < dlc ? (data[7 - i]) : 0) + |
266 | ((6 - i) < dlc ? (data[6 - i] << 8) : 0); | 262 | ((6 - i) < dlc ? (data[6 - i] << 8) : 0); |
267 | bfin_write(®->chl[TRANSMIT_CHL].data[i], val); | 263 | writew(val, ®->chl[TRANSMIT_CHL].data[i]); |
268 | } | 264 | } |
269 | 265 | ||
270 | /* fill data length code */ | 266 | /* fill data length code */ |
271 | bfin_write(®->chl[TRANSMIT_CHL].dlc, dlc); | 267 | writew(dlc, ®->chl[TRANSMIT_CHL].dlc); |
272 | 268 | ||
273 | can_put_echo_skb(skb, dev, 0); | 269 | can_put_echo_skb(skb, dev, 0); |
274 | 270 | ||
275 | /* set transmit request */ | 271 | /* set transmit request */ |
276 | bfin_write(®->trs2, BIT(TRANSMIT_CHL - 16)); | 272 | writew(BIT(TRANSMIT_CHL - 16), ®->trs2); |
277 | 273 | ||
278 | return 0; | 274 | return 0; |
279 | } | 275 | } |
@@ -296,26 +292,26 @@ static void bfin_can_rx(struct net_device *dev, u16 isrc) | |||
296 | /* get id */ | 292 | /* get id */ |
297 | if (isrc & BIT(RECEIVE_EXT_CHL)) { | 293 | if (isrc & BIT(RECEIVE_EXT_CHL)) { |
298 | /* extended frame format (EFF) */ | 294 | /* extended frame format (EFF) */ |
299 | cf->can_id = ((bfin_read(®->chl[RECEIVE_EXT_CHL].id1) | 295 | cf->can_id = ((readw(®->chl[RECEIVE_EXT_CHL].id1) |
300 | & 0x1FFF) << 16) | 296 | & 0x1FFF) << 16) |
301 | + bfin_read(®->chl[RECEIVE_EXT_CHL].id0); | 297 | + readw(®->chl[RECEIVE_EXT_CHL].id0); |
302 | cf->can_id |= CAN_EFF_FLAG; | 298 | cf->can_id |= CAN_EFF_FLAG; |
303 | obj = RECEIVE_EXT_CHL; | 299 | obj = RECEIVE_EXT_CHL; |
304 | } else { | 300 | } else { |
305 | /* standard frame format (SFF) */ | 301 | /* standard frame format (SFF) */ |
306 | cf->can_id = (bfin_read(®->chl[RECEIVE_STD_CHL].id1) | 302 | cf->can_id = (readw(®->chl[RECEIVE_STD_CHL].id1) |
307 | & 0x1ffc) >> 2; | 303 | & 0x1ffc) >> 2; |
308 | obj = RECEIVE_STD_CHL; | 304 | obj = RECEIVE_STD_CHL; |
309 | } | 305 | } |
310 | if (bfin_read(®->chl[obj].id1) & RTR) | 306 | if (readw(®->chl[obj].id1) & RTR) |
311 | cf->can_id |= CAN_RTR_FLAG; | 307 | cf->can_id |= CAN_RTR_FLAG; |
312 | 308 | ||
313 | /* get data length code */ | 309 | /* get data length code */ |
314 | cf->can_dlc = get_can_dlc(bfin_read(®->chl[obj].dlc) & 0xF); | 310 | cf->can_dlc = get_can_dlc(readw(®->chl[obj].dlc) & 0xF); |
315 | 311 | ||
316 | /* get payload */ | 312 | /* get payload */ |
317 | for (i = 0; i < 8; i += 2) { | 313 | for (i = 0; i < 8; i += 2) { |
318 | val = bfin_read(®->chl[obj].data[i]); | 314 | val = readw(®->chl[obj].data[i]); |
319 | cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0; | 315 | cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0; |
320 | cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0; | 316 | cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0; |
321 | } | 317 | } |
@@ -369,7 +365,7 @@ static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status) | |||
369 | 365 | ||
370 | if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING || | 366 | if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING || |
371 | state == CAN_STATE_ERROR_PASSIVE)) { | 367 | state == CAN_STATE_ERROR_PASSIVE)) { |
372 | u16 cec = bfin_read(®->cec); | 368 | u16 cec = readw(®->cec); |
373 | u8 rxerr = cec; | 369 | u8 rxerr = cec; |
374 | u8 txerr = cec >> 8; | 370 | u8 txerr = cec >> 8; |
375 | 371 | ||
@@ -420,23 +416,23 @@ static irqreturn_t bfin_can_interrupt(int irq, void *dev_id) | |||
420 | struct net_device_stats *stats = &dev->stats; | 416 | struct net_device_stats *stats = &dev->stats; |
421 | u16 status, isrc; | 417 | u16 status, isrc; |
422 | 418 | ||
423 | if ((irq == priv->tx_irq) && bfin_read(®->mbtif2)) { | 419 | if ((irq == priv->tx_irq) && readw(®->mbtif2)) { |
424 | /* transmission complete interrupt */ | 420 | /* transmission complete interrupt */ |
425 | bfin_write(®->mbtif2, 0xFFFF); | 421 | writew(0xFFFF, ®->mbtif2); |
426 | stats->tx_packets++; | 422 | stats->tx_packets++; |
427 | stats->tx_bytes += bfin_read(®->chl[TRANSMIT_CHL].dlc); | 423 | stats->tx_bytes += readw(®->chl[TRANSMIT_CHL].dlc); |
428 | can_get_echo_skb(dev, 0); | 424 | can_get_echo_skb(dev, 0); |
429 | netif_wake_queue(dev); | 425 | netif_wake_queue(dev); |
430 | } else if ((irq == priv->rx_irq) && bfin_read(®->mbrif1)) { | 426 | } else if ((irq == priv->rx_irq) && readw(®->mbrif1)) { |
431 | /* receive interrupt */ | 427 | /* receive interrupt */ |
432 | isrc = bfin_read(®->mbrif1); | 428 | isrc = readw(®->mbrif1); |
433 | bfin_write(®->mbrif1, 0xFFFF); | 429 | writew(0xFFFF, ®->mbrif1); |
434 | bfin_can_rx(dev, isrc); | 430 | bfin_can_rx(dev, isrc); |
435 | } else if ((irq == priv->err_irq) && bfin_read(®->gis)) { | 431 | } else if ((irq == priv->err_irq) && readw(®->gis)) { |
436 | /* error interrupt */ | 432 | /* error interrupt */ |
437 | isrc = bfin_read(®->gis); | 433 | isrc = readw(®->gis); |
438 | status = bfin_read(®->esr); | 434 | status = readw(®->esr); |
439 | bfin_write(®->gis, 0x7FF); | 435 | writew(0x7FF, ®->gis); |
440 | bfin_can_err(dev, isrc, status); | 436 | bfin_can_err(dev, isrc, status); |
441 | } else { | 437 | } else { |
442 | return IRQ_NONE; | 438 | return IRQ_NONE; |
@@ -641,9 +637,8 @@ static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg) | |||
641 | 637 | ||
642 | if (netif_running(dev)) { | 638 | if (netif_running(dev)) { |
643 | /* enter sleep mode */ | 639 | /* enter sleep mode */ |
644 | bfin_write(®->control, bfin_read(®->control) | SMR); | 640 | writew(readw(®->control) | SMR, ®->control); |
645 | SSYNC(); | 641 | while (!(readw(®->intr) & SMACK)) { |
646 | while (!(bfin_read(®->intr) & SMACK)) { | ||
647 | udelay(10); | 642 | udelay(10); |
648 | if (--timeout == 0) { | 643 | if (--timeout == 0) { |
649 | netdev_err(dev, "fail to enter sleep mode\n"); | 644 | netdev_err(dev, "fail to enter sleep mode\n"); |
@@ -663,8 +658,7 @@ static int bfin_can_resume(struct platform_device *pdev) | |||
663 | 658 | ||
664 | if (netif_running(dev)) { | 659 | if (netif_running(dev)) { |
665 | /* leave sleep mode */ | 660 | /* leave sleep mode */ |
666 | bfin_write(®->intr, 0); | 661 | writew(0, ®->intr); |
667 | SSYNC(); | ||
668 | } | 662 | } |
669 | 663 | ||
670 | return 0; | 664 | return 0; |