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-rw-r--r--drivers/net/can/mscan/Kconfig24
-rw-r--r--drivers/net/can/mscan/Makefile5
-rw-r--r--drivers/net/can/mscan/mpc5xxx_can.c421
-rw-r--r--drivers/net/can/mscan/mscan.c701
-rw-r--r--drivers/net/can/mscan/mscan.h302
5 files changed, 1453 insertions, 0 deletions
diff --git a/drivers/net/can/mscan/Kconfig b/drivers/net/can/mscan/Kconfig
new file mode 100644
index 000000000000..27d1d398e25e
--- /dev/null
+++ b/drivers/net/can/mscan/Kconfig
@@ -0,0 +1,24 @@
1config CAN_MSCAN
2 depends on CAN_DEV && (PPC || M68K || M68KNOMMU)
3 tristate "Support for Freescale MSCAN based chips"
4 ---help---
5 The Motorola Scalable Controller Area Network (MSCAN) definition
6 is based on the MSCAN12 definition which is the specific
7 implementation of the Motorola Scalable CAN concept targeted for
8 the Motorola MC68HC12 Microcontroller Family.
9
10if CAN_MSCAN
11
12config CAN_MPC5XXX
13 tristate "Freescale MPC5xxx onboard CAN controller"
14 depends on (PPC_MPC52xx || PPC_MPC512x)
15 ---help---
16 If you say yes here you get support for Freescale's MPC5xxx
17 onboard CAN controller. Currently, the MPC5200, MPC5200B and
18 MPC5121 (Rev. 2 and later) are supported.
19
20 This driver can also be built as a module. If so, the module
21 will be called mscan-mpc5xxx.ko.
22
23endif
24
diff --git a/drivers/net/can/mscan/Makefile b/drivers/net/can/mscan/Makefile
new file mode 100644
index 000000000000..c9fab17cd8b4
--- /dev/null
+++ b/drivers/net/can/mscan/Makefile
@@ -0,0 +1,5 @@
1
2obj-$(CONFIG_CAN_MPC5XXX) += mscan-mpc5xxx.o
3mscan-mpc5xxx-objs := mscan.o mpc5xxx_can.o
4
5ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
new file mode 100644
index 000000000000..03e7c48465a2
--- /dev/null
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -0,0 +1,421 @@
1/*
2 * CAN bus driver for the Freescale MPC5xxx embedded CPU.
3 *
4 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
5 * Varma Electronics Oy
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
7 * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/interrupt.h>
26#include <linux/platform_device.h>
27#include <linux/netdevice.h>
28#include <linux/can.h>
29#include <linux/can/dev.h>
30#include <linux/of_platform.h>
31#include <sysdev/fsl_soc.h>
32#include <linux/clk.h>
33#include <linux/io.h>
34#include <asm/mpc52xx.h>
35
36#include "mscan.h"
37
38#define DRV_NAME "mpc5xxx_can"
39
40struct mpc5xxx_can_data {
41 unsigned int type;
42 u32 (*get_clock)(struct of_device *ofdev, const char *clock_name,
43 int *mscan_clksrc);
44};
45
46#ifdef CONFIG_PPC_MPC52xx
47static struct of_device_id __devinitdata mpc52xx_cdm_ids[] = {
48 { .compatible = "fsl,mpc5200-cdm", },
49 {}
50};
51
52static u32 __devinit mpc52xx_can_get_clock(struct of_device *ofdev,
53 const char *clock_name,
54 int *mscan_clksrc)
55{
56 unsigned int pvr;
57 struct mpc52xx_cdm __iomem *cdm;
58 struct device_node *np_cdm;
59 unsigned int freq;
60 u32 val;
61
62 pvr = mfspr(SPRN_PVR);
63
64 /*
65 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
66 * (IP_CLK) can be selected as MSCAN clock source. According to
67 * the MPC5200 user's manual, the oscillator clock is the better
68 * choice as it has less jitter. For this reason, it is selected
69 * by default. Unfortunately, it can not be selected for the old
70 * MPC5200 Rev. A chips due to a hardware bug (check errata).
71 */
72 if (clock_name && strcmp(clock_name, "ip") == 0)
73 *mscan_clksrc = MSCAN_CLKSRC_BUS;
74 else
75 *mscan_clksrc = MSCAN_CLKSRC_XTAL;
76
77 freq = mpc5xxx_get_bus_frequency(ofdev->node);
78 if (!freq)
79 return 0;
80
81 if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
82 return freq;
83
84 /* Determine SYS_XTAL_IN frequency from the clock domain settings */
85 np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
86 if (!np_cdm) {
87 dev_err(&ofdev->dev, "can't get clock node!\n");
88 return 0;
89 }
90 cdm = of_iomap(np_cdm, 0);
91
92 if (in_8(&cdm->ipb_clk_sel) & 0x1)
93 freq *= 2;
94 val = in_be32(&cdm->rstcfg);
95
96 freq *= (val & (1 << 5)) ? 8 : 4;
97 freq /= (val & (1 << 6)) ? 12 : 16;
98
99 of_node_put(np_cdm);
100 iounmap(cdm);
101
102 return freq;
103}
104#else /* !CONFIG_PPC_MPC52xx */
105static u32 __devinit mpc52xx_can_get_clock(struct of_device *ofdev,
106 const char *clock_name,
107 int *mscan_clksrc)
108{
109 return 0;
110}
111#endif /* CONFIG_PPC_MPC52xx */
112
113#ifdef CONFIG_PPC_MPC512x
114struct mpc512x_clockctl {
115 u32 spmr; /* System PLL Mode Reg */
116 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
117 u32 scfr1; /* System Clk Freq Reg 1 */
118 u32 scfr2; /* System Clk Freq Reg 2 */
119 u32 reserved;
120 u32 bcr; /* Bread Crumb Reg */
121 u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */
122 u32 spccr; /* SPDIF Clk Ctrl Reg */
123 u32 cccr; /* CFM Clk Ctrl Reg */
124 u32 dccr; /* DIU Clk Cnfg Reg */
125 u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */
126};
127
128static struct of_device_id __devinitdata mpc512x_clock_ids[] = {
129 { .compatible = "fsl,mpc5121-clock", },
130 {}
131};
132
133static u32 __devinit mpc512x_can_get_clock(struct of_device *ofdev,
134 const char *clock_name,
135 int *mscan_clksrc)
136{
137 struct mpc512x_clockctl __iomem *clockctl;
138 struct device_node *np_clock;
139 struct clk *sys_clk, *ref_clk;
140 int plen, clockidx, clocksrc = -1;
141 u32 sys_freq, val, clockdiv = 1, freq = 0;
142 const u32 *pval;
143
144 np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
145 if (!np_clock) {
146 dev_err(&ofdev->dev, "couldn't find clock node\n");
147 return -ENODEV;
148 }
149 clockctl = of_iomap(np_clock, 0);
150 if (!clockctl) {
151 dev_err(&ofdev->dev, "couldn't map clock registers\n");
152 return 0;
153 }
154
155 /* Determine the MSCAN device index from the physical address */
156 pval = of_get_property(ofdev->node, "reg", &plen);
157 BUG_ON(!pval || plen < sizeof(*pval));
158 clockidx = (*pval & 0x80) ? 1 : 0;
159 if (*pval & 0x2000)
160 clockidx += 2;
161
162 /*
163 * Clock source and divider selection: 3 different clock sources
164 * can be selected: "ip", "ref" or "sys". For the latter two, a
165 * clock divider can be defined as well. If the clock source is
166 * not specified by the device tree, we first try to find an
167 * optimal CAN source clock based on the system clock. If that
168 * is not posslible, the reference clock will be used.
169 */
170 if (clock_name && !strcmp(clock_name, "ip")) {
171 *mscan_clksrc = MSCAN_CLKSRC_IPS;
172 freq = mpc5xxx_get_bus_frequency(ofdev->node);
173 } else {
174 *mscan_clksrc = MSCAN_CLKSRC_BUS;
175
176 pval = of_get_property(ofdev->node,
177 "fsl,mscan-clock-divider", &plen);
178 if (pval && plen == sizeof(*pval))
179 clockdiv = *pval;
180 if (!clockdiv)
181 clockdiv = 1;
182
183 if (!clock_name || !strcmp(clock_name, "sys")) {
184 sys_clk = clk_get(&ofdev->dev, "sys_clk");
185 if (!sys_clk) {
186 dev_err(&ofdev->dev, "couldn't get sys_clk\n");
187 goto exit_unmap;
188 }
189 /* Get and round up/down sys clock rate */
190 sys_freq = 1000000 *
191 ((clk_get_rate(sys_clk) + 499999) / 1000000);
192
193 if (!clock_name) {
194 /* A multiple of 16 MHz would be optimal */
195 if ((sys_freq % 16000000) == 0) {
196 clocksrc = 0;
197 clockdiv = sys_freq / 16000000;
198 freq = sys_freq / clockdiv;
199 }
200 } else {
201 clocksrc = 0;
202 freq = sys_freq / clockdiv;
203 }
204 }
205
206 if (clocksrc < 0) {
207 ref_clk = clk_get(&ofdev->dev, "ref_clk");
208 if (!ref_clk) {
209 dev_err(&ofdev->dev, "couldn't get ref_clk\n");
210 goto exit_unmap;
211 }
212 clocksrc = 1;
213 freq = clk_get_rate(ref_clk) / clockdiv;
214 }
215 }
216
217 /* Disable clock */
218 out_be32(&clockctl->mccr[clockidx], 0x0);
219 if (clocksrc >= 0) {
220 /* Set source and divider */
221 val = (clocksrc << 14) | ((clockdiv - 1) << 17);
222 out_be32(&clockctl->mccr[clockidx], val);
223 /* Enable clock */
224 out_be32(&clockctl->mccr[clockidx], val | 0x10000);
225 }
226
227 /* Enable MSCAN clock domain */
228 val = in_be32(&clockctl->sccr[1]);
229 if (!(val & (1 << 25)))
230 out_be32(&clockctl->sccr[1], val | (1 << 25));
231
232 dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
233 *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
234 clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);
235
236exit_unmap:
237 of_node_put(np_clock);
238 iounmap(clockctl);
239
240 return freq;
241}
242#else /* !CONFIG_PPC_MPC512x */
243static u32 __devinit mpc512x_can_get_clock(struct of_device *ofdev,
244 const char *clock_name,
245 int *mscan_clksrc)
246{
247 return 0;
248}
249#endif /* CONFIG_PPC_MPC512x */
250
251static int __devinit mpc5xxx_can_probe(struct of_device *ofdev,
252 const struct of_device_id *id)
253{
254 struct mpc5xxx_can_data *data = (struct mpc5xxx_can_data *)id->data;
255 struct device_node *np = ofdev->node;
256 struct net_device *dev;
257 struct mscan_priv *priv;
258 void __iomem *base;
259 const char *clock_name = NULL;
260 int irq, mscan_clksrc = 0;
261 int err = -ENOMEM;
262
263 base = of_iomap(np, 0);
264 if (!base) {
265 dev_err(&ofdev->dev, "couldn't ioremap\n");
266 return err;
267 }
268
269 irq = irq_of_parse_and_map(np, 0);
270 if (!irq) {
271 dev_err(&ofdev->dev, "no irq found\n");
272 err = -ENODEV;
273 goto exit_unmap_mem;
274 }
275
276 dev = alloc_mscandev();
277 if (!dev)
278 goto exit_dispose_irq;
279
280 priv = netdev_priv(dev);
281 priv->reg_base = base;
282 dev->irq = irq;
283
284 clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
285
286 BUG_ON(!data);
287 priv->type = data->type;
288 priv->can.clock.freq = data->get_clock(ofdev, clock_name,
289 &mscan_clksrc);
290 if (!priv->can.clock.freq) {
291 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
292 goto exit_free_mscan;
293 }
294
295 SET_NETDEV_DEV(dev, &ofdev->dev);
296
297 err = register_mscandev(dev, mscan_clksrc);
298 if (err) {
299 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
300 DRV_NAME, err);
301 goto exit_free_mscan;
302 }
303
304 dev_set_drvdata(&ofdev->dev, dev);
305
306 dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
307 priv->reg_base, dev->irq, priv->can.clock.freq);
308
309 return 0;
310
311exit_free_mscan:
312 free_candev(dev);
313exit_dispose_irq:
314 irq_dispose_mapping(irq);
315exit_unmap_mem:
316 iounmap(base);
317
318 return err;
319}
320
321static int __devexit mpc5xxx_can_remove(struct of_device *ofdev)
322{
323 struct net_device *dev = dev_get_drvdata(&ofdev->dev);
324 struct mscan_priv *priv = netdev_priv(dev);
325
326 dev_set_drvdata(&ofdev->dev, NULL);
327
328 unregister_mscandev(dev);
329 iounmap(priv->reg_base);
330 irq_dispose_mapping(dev->irq);
331 free_candev(dev);
332
333 return 0;
334}
335
336#ifdef CONFIG_PM
337static struct mscan_regs saved_regs;
338static int mpc5xxx_can_suspend(struct of_device *ofdev, pm_message_t state)
339{
340 struct net_device *dev = dev_get_drvdata(&ofdev->dev);
341 struct mscan_priv *priv = netdev_priv(dev);
342 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
343
344 _memcpy_fromio(&saved_regs, regs, sizeof(*regs));
345
346 return 0;
347}
348
349static int mpc5xxx_can_resume(struct of_device *ofdev)
350{
351 struct net_device *dev = dev_get_drvdata(&ofdev->dev);
352 struct mscan_priv *priv = netdev_priv(dev);
353 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
354
355 regs->canctl0 |= MSCAN_INITRQ;
356 while (!(regs->canctl1 & MSCAN_INITAK))
357 udelay(10);
358
359 regs->canctl1 = saved_regs.canctl1;
360 regs->canbtr0 = saved_regs.canbtr0;
361 regs->canbtr1 = saved_regs.canbtr1;
362 regs->canidac = saved_regs.canidac;
363
364 /* restore masks, buffers etc. */
365 _memcpy_toio(&regs->canidar1_0, (void *)&saved_regs.canidar1_0,
366 sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
367
368 regs->canctl0 &= ~MSCAN_INITRQ;
369 regs->cantbsel = saved_regs.cantbsel;
370 regs->canrier = saved_regs.canrier;
371 regs->cantier = saved_regs.cantier;
372 regs->canctl0 = saved_regs.canctl0;
373
374 return 0;
375}
376#endif
377
378static struct mpc5xxx_can_data __devinitdata mpc5200_can_data = {
379 .type = MSCAN_TYPE_MPC5200,
380 .get_clock = mpc52xx_can_get_clock,
381};
382
383static struct mpc5xxx_can_data __devinitdata mpc5121_can_data = {
384 .type = MSCAN_TYPE_MPC5121,
385 .get_clock = mpc512x_can_get_clock,
386};
387
388static struct of_device_id __devinitdata mpc5xxx_can_table[] = {
389 { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
390 /* Note that only MPC5121 Rev. 2 (and later) is supported */
391 { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
392 {},
393};
394
395static struct of_platform_driver mpc5xxx_can_driver = {
396 .owner = THIS_MODULE,
397 .name = "mpc5xxx_can",
398 .probe = mpc5xxx_can_probe,
399 .remove = __devexit_p(mpc5xxx_can_remove),
400#ifdef CONFIG_PM
401 .suspend = mpc5xxx_can_suspend,
402 .resume = mpc5xxx_can_resume,
403#endif
404 .match_table = mpc5xxx_can_table,
405};
406
407static int __init mpc5xxx_can_init(void)
408{
409 return of_register_platform_driver(&mpc5xxx_can_driver);
410}
411module_init(mpc5xxx_can_init);
412
413static void __exit mpc5xxx_can_exit(void)
414{
415 return of_unregister_platform_driver(&mpc5xxx_can_driver);
416};
417module_exit(mpc5xxx_can_exit);
418
419MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
420MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
421MODULE_LICENSE("GPL v2");
diff --git a/drivers/net/can/mscan/mscan.c b/drivers/net/can/mscan/mscan.c
new file mode 100644
index 000000000000..6b7dd578d417
--- /dev/null
+++ b/drivers/net/can/mscan/mscan.c
@@ -0,0 +1,701 @@
1/*
2 * CAN bus driver for the alone generic (as possible as) MSCAN controller.
3 *
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
5 * Varma Electronics Oy
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
7 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/netdevice.h>
28#include <linux/if_arp.h>
29#include <linux/if_ether.h>
30#include <linux/list.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34#include <linux/io.h>
35
36#include "mscan.h"
37
38static struct can_bittiming_const mscan_bittiming_const = {
39 .name = "mscan",
40 .tseg1_min = 4,
41 .tseg1_max = 16,
42 .tseg2_min = 2,
43 .tseg2_max = 8,
44 .sjw_max = 4,
45 .brp_min = 1,
46 .brp_max = 64,
47 .brp_inc = 1,
48};
49
50struct mscan_state {
51 u8 mode;
52 u8 canrier;
53 u8 cantier;
54};
55
56static enum can_state state_map[] = {
57 CAN_STATE_ERROR_ACTIVE,
58 CAN_STATE_ERROR_WARNING,
59 CAN_STATE_ERROR_PASSIVE,
60 CAN_STATE_BUS_OFF
61};
62
63static int mscan_set_mode(struct net_device *dev, u8 mode)
64{
65 struct mscan_priv *priv = netdev_priv(dev);
66 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
67 int ret = 0;
68 int i;
69 u8 canctl1;
70
71 if (mode != MSCAN_NORMAL_MODE) {
72 if (priv->tx_active) {
73 /* Abort transfers before going to sleep */#
74 out_8(&regs->cantarq, priv->tx_active);
75 /* Suppress TX done interrupts */
76 out_8(&regs->cantier, 0);
77 }
78
79 canctl1 = in_8(&regs->canctl1);
80 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
81 setbits8(&regs->canctl0, MSCAN_SLPRQ);
82 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
83 if (in_8(&regs->canctl1) & MSCAN_SLPAK)
84 break;
85 udelay(100);
86 }
87 /*
88 * The mscan controller will fail to enter sleep mode,
89 * while there are irregular activities on bus, like
90 * somebody keeps retransmitting. This behavior is
91 * undocumented and seems to differ between mscan built
92 * in mpc5200b and mpc5200. We proceed in that case,
93 * since otherwise the slprq will be kept set and the
94 * controller will get stuck. NOTE: INITRQ or CSWAI
95 * will abort all active transmit actions, if still
96 * any, at once.
97 */
98 if (i >= MSCAN_SET_MODE_RETRIES)
99 dev_dbg(dev->dev.parent,
100 "device failed to enter sleep mode. "
101 "We proceed anyhow.\n");
102 else
103 priv->can.state = CAN_STATE_SLEEPING;
104 }
105
106 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
107 setbits8(&regs->canctl0, MSCAN_INITRQ);
108 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
109 if (in_8(&regs->canctl1) & MSCAN_INITAK)
110 break;
111 }
112 if (i >= MSCAN_SET_MODE_RETRIES)
113 ret = -ENODEV;
114 }
115 if (!ret)
116 priv->can.state = CAN_STATE_STOPPED;
117
118 if (mode & MSCAN_CSWAI)
119 setbits8(&regs->canctl0, MSCAN_CSWAI);
120
121 } else {
122 canctl1 = in_8(&regs->canctl1);
123 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
124 clrbits8(&regs->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
125 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
126 canctl1 = in_8(&regs->canctl1);
127 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
128 break;
129 }
130 if (i >= MSCAN_SET_MODE_RETRIES)
131 ret = -ENODEV;
132 else
133 priv->can.state = CAN_STATE_ERROR_ACTIVE;
134 }
135 }
136 return ret;
137}
138
139static int mscan_start(struct net_device *dev)
140{
141 struct mscan_priv *priv = netdev_priv(dev);
142 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
143 u8 canrflg;
144 int err;
145
146 out_8(&regs->canrier, 0);
147
148 INIT_LIST_HEAD(&priv->tx_head);
149 priv->prev_buf_id = 0;
150 priv->cur_pri = 0;
151 priv->tx_active = 0;
152 priv->shadow_canrier = 0;
153 priv->flags = 0;
154
155 if (priv->type == MSCAN_TYPE_MPC5121) {
156 /* Clear pending bus-off condition */
157 if (in_8(&regs->canmisc) & MSCAN_BOHOLD)
158 out_8(&regs->canmisc, MSCAN_BOHOLD);
159 }
160
161 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
162 if (err)
163 return err;
164
165 canrflg = in_8(&regs->canrflg);
166 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
167 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
168 MSCAN_STATE_TX(canrflg))];
169 out_8(&regs->cantier, 0);
170
171 /* Enable receive interrupts. */
172 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
173
174 return 0;
175}
176
177static int mscan_restart(struct net_device *dev)
178{
179 struct mscan_priv *priv = netdev_priv(dev);
180
181 if (priv->type == MSCAN_TYPE_MPC5121) {
182 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
183
184 priv->can.state = CAN_STATE_ERROR_ACTIVE;
185 WARN(!(in_8(&regs->canmisc) & MSCAN_BOHOLD),
186 "bus-off state expected");
187 out_8(&regs->canmisc, MSCAN_BOHOLD);
188 /* Re-enable receive interrupts. */
189 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
190 } else {
191 if (priv->can.state <= CAN_STATE_BUS_OFF)
192 mscan_set_mode(dev, MSCAN_INIT_MODE);
193 return mscan_start(dev);
194 }
195
196 return 0;
197}
198
199static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
200{
201 struct can_frame *frame = (struct can_frame *)skb->data;
202 struct mscan_priv *priv = netdev_priv(dev);
203 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
204 int i, rtr, buf_id;
205 u32 can_id;
206
207 if (can_dropped_invalid_skb(dev, skb))
208 return NETDEV_TX_OK;
209
210 out_8(&regs->cantier, 0);
211
212 i = ~priv->tx_active & MSCAN_TXE;
213 buf_id = ffs(i) - 1;
214 switch (hweight8(i)) {
215 case 0:
216 netif_stop_queue(dev);
217 dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n");
218 return NETDEV_TX_BUSY;
219 case 1:
220 /*
221 * if buf_id < 3, then current frame will be send out of order,
222 * since buffer with lower id have higher priority (hell..)
223 */
224 netif_stop_queue(dev);
225 case 2:
226 if (buf_id < priv->prev_buf_id) {
227 priv->cur_pri++;
228 if (priv->cur_pri == 0xff) {
229 set_bit(F_TX_WAIT_ALL, &priv->flags);
230 netif_stop_queue(dev);
231 }
232 }
233 set_bit(F_TX_PROGRESS, &priv->flags);
234 break;
235 }
236 priv->prev_buf_id = buf_id;
237 out_8(&regs->cantbsel, i);
238
239 rtr = frame->can_id & CAN_RTR_FLAG;
240
241 /* RTR is always the lowest bit of interest, then IDs follow */
242 if (frame->can_id & CAN_EFF_FLAG) {
243 can_id = (frame->can_id & CAN_EFF_MASK)
244 << (MSCAN_EFF_RTR_SHIFT + 1);
245 if (rtr)
246 can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
247 out_be16(&regs->tx.idr3_2, can_id);
248
249 can_id >>= 16;
250 /* EFF_FLAGS are inbetween the IDs :( */
251 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
252 | MSCAN_EFF_FLAGS;
253 } else {
254 can_id = (frame->can_id & CAN_SFF_MASK)
255 << (MSCAN_SFF_RTR_SHIFT + 1);
256 if (rtr)
257 can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
258 }
259 out_be16(&regs->tx.idr1_0, can_id);
260
261 if (!rtr) {
262 void __iomem *data = &regs->tx.dsr1_0;
263 u16 *payload = (u16 *)frame->data;
264
265 /* It is safe to write into dsr[dlc+1] */
266 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) {
267 out_be16(data, *payload++);
268 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
269 }
270 }
271
272 out_8(&regs->tx.dlr, frame->can_dlc);
273 out_8(&regs->tx.tbpr, priv->cur_pri);
274
275 /* Start transmission. */
276 out_8(&regs->cantflg, 1 << buf_id);
277
278 if (!test_bit(F_TX_PROGRESS, &priv->flags))
279 dev->trans_start = jiffies;
280
281 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
282
283 can_put_echo_skb(skb, dev, buf_id);
284
285 /* Enable interrupt. */
286 priv->tx_active |= 1 << buf_id;
287 out_8(&regs->cantier, priv->tx_active);
288
289 return NETDEV_TX_OK;
290}
291
292/* This function returns the old state to see where we came from */
293static enum can_state check_set_state(struct net_device *dev, u8 canrflg)
294{
295 struct mscan_priv *priv = netdev_priv(dev);
296 enum can_state state, old_state = priv->can.state;
297
298 if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) {
299 state = state_map[max(MSCAN_STATE_RX(canrflg),
300 MSCAN_STATE_TX(canrflg))];
301 priv->can.state = state;
302 }
303 return old_state;
304}
305
306static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
307{
308 struct mscan_priv *priv = netdev_priv(dev);
309 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
310 u32 can_id;
311 int i;
312
313 can_id = in_be16(&regs->rx.idr1_0);
314 if (can_id & (1 << 3)) {
315 frame->can_id = CAN_EFF_FLAG;
316 can_id = ((can_id << 16) | in_be16(&regs->rx.idr3_2));
317 can_id = ((can_id & 0xffe00000) |
318 ((can_id & 0x7ffff) << 2)) >> 2;
319 } else {
320 can_id >>= 4;
321 frame->can_id = 0;
322 }
323
324 frame->can_id |= can_id >> 1;
325 if (can_id & 1)
326 frame->can_id |= CAN_RTR_FLAG;
327
328 frame->can_dlc = get_can_dlc(in_8(&regs->rx.dlr) & 0xf);
329
330 if (!(frame->can_id & CAN_RTR_FLAG)) {
331 void __iomem *data = &regs->rx.dsr1_0;
332 u16 *payload = (u16 *)frame->data;
333
334 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) {
335 *payload++ = in_be16(data);
336 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
337 }
338 }
339
340 out_8(&regs->canrflg, MSCAN_RXF);
341}
342
343static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
344 u8 canrflg)
345{
346 struct mscan_priv *priv = netdev_priv(dev);
347 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
348 struct net_device_stats *stats = &dev->stats;
349 enum can_state old_state;
350
351 dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg);
352 frame->can_id = CAN_ERR_FLAG;
353
354 if (canrflg & MSCAN_OVRIF) {
355 frame->can_id |= CAN_ERR_CRTL;
356 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
357 stats->rx_over_errors++;
358 stats->rx_errors++;
359 } else {
360 frame->data[1] = 0;
361 }
362
363 old_state = check_set_state(dev, canrflg);
364 /* State changed */
365 if (old_state != priv->can.state) {
366 switch (priv->can.state) {
367 case CAN_STATE_ERROR_WARNING:
368 frame->can_id |= CAN_ERR_CRTL;
369 priv->can.can_stats.error_warning++;
370 if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) <
371 (canrflg & MSCAN_RSTAT_MSK))
372 frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
373 if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) <
374 (canrflg & MSCAN_TSTAT_MSK))
375 frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
376 break;
377 case CAN_STATE_ERROR_PASSIVE:
378 frame->can_id |= CAN_ERR_CRTL;
379 priv->can.can_stats.error_passive++;
380 frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
381 break;
382 case CAN_STATE_BUS_OFF:
383 frame->can_id |= CAN_ERR_BUSOFF;
384 /*
385 * The MSCAN on the MPC5200 does recover from bus-off
386 * automatically. To avoid that we stop the chip doing
387 * a light-weight stop (we are in irq-context).
388 */
389 if (priv->type != MSCAN_TYPE_MPC5121) {
390 out_8(&regs->cantier, 0);
391 out_8(&regs->canrier, 0);
392 setbits8(&regs->canctl0,
393 MSCAN_SLPRQ | MSCAN_INITRQ);
394 }
395 can_bus_off(dev);
396 break;
397 default:
398 break;
399 }
400 }
401 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
402 frame->can_dlc = CAN_ERR_DLC;
403 out_8(&regs->canrflg, MSCAN_ERR_IF);
404}
405
406static int mscan_rx_poll(struct napi_struct *napi, int quota)
407{
408 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
409 struct net_device *dev = napi->dev;
410 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
411 struct net_device_stats *stats = &dev->stats;
412 int npackets = 0;
413 int ret = 1;
414 struct sk_buff *skb;
415 struct can_frame *frame;
416 u8 canrflg;
417
418 while (npackets < quota) {
419 canrflg = in_8(&regs->canrflg);
420 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
421 break;
422
423 skb = alloc_can_skb(dev, &frame);
424 if (!skb) {
425 if (printk_ratelimit())
426 dev_notice(dev->dev.parent, "packet dropped\n");
427 stats->rx_dropped++;
428 out_8(&regs->canrflg, canrflg);
429 continue;
430 }
431
432 if (canrflg & MSCAN_RXF)
433 mscan_get_rx_frame(dev, frame);
434 else if (canrflg & MSCAN_ERR_IF)
435 mscan_get_err_frame(dev, frame, canrflg);
436
437 stats->rx_packets++;
438 stats->rx_bytes += frame->can_dlc;
439 npackets++;
440 netif_receive_skb(skb);
441 }
442
443 if (!(in_8(&regs->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) {
444 napi_complete(&priv->napi);
445 clear_bit(F_RX_PROGRESS, &priv->flags);
446 if (priv->can.state < CAN_STATE_BUS_OFF)
447 out_8(&regs->canrier, priv->shadow_canrier);
448 ret = 0;
449 }
450 return ret;
451}
452
453static irqreturn_t mscan_isr(int irq, void *dev_id)
454{
455 struct net_device *dev = (struct net_device *)dev_id;
456 struct mscan_priv *priv = netdev_priv(dev);
457 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
458 struct net_device_stats *stats = &dev->stats;
459 u8 cantier, cantflg, canrflg;
460 irqreturn_t ret = IRQ_NONE;
461
462 cantier = in_8(&regs->cantier) & MSCAN_TXE;
463 cantflg = in_8(&regs->cantflg) & cantier;
464
465 if (cantier && cantflg) {
466 struct list_head *tmp, *pos;
467
468 list_for_each_safe(pos, tmp, &priv->tx_head) {
469 struct tx_queue_entry *entry =
470 list_entry(pos, struct tx_queue_entry, list);
471 u8 mask = entry->mask;
472
473 if (!(cantflg & mask))
474 continue;
475
476 out_8(&regs->cantbsel, mask);
477 stats->tx_bytes += in_8(&regs->tx.dlr);
478 stats->tx_packets++;
479 can_get_echo_skb(dev, entry->id);
480 priv->tx_active &= ~mask;
481 list_del(pos);
482 }
483
484 if (list_empty(&priv->tx_head)) {
485 clear_bit(F_TX_WAIT_ALL, &priv->flags);
486 clear_bit(F_TX_PROGRESS, &priv->flags);
487 priv->cur_pri = 0;
488 } else {
489 dev->trans_start = jiffies;
490 }
491
492 if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
493 netif_wake_queue(dev);
494
495 out_8(&regs->cantier, priv->tx_active);
496 ret = IRQ_HANDLED;
497 }
498
499 canrflg = in_8(&regs->canrflg);
500 if ((canrflg & ~MSCAN_STAT_MSK) &&
501 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
502 if (canrflg & ~MSCAN_STAT_MSK) {
503 priv->shadow_canrier = in_8(&regs->canrier);
504 out_8(&regs->canrier, 0);
505 napi_schedule(&priv->napi);
506 ret = IRQ_HANDLED;
507 } else {
508 clear_bit(F_RX_PROGRESS, &priv->flags);
509 }
510 }
511 return ret;
512}
513
514static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
515{
516 struct mscan_priv *priv = netdev_priv(dev);
517 int ret = 0;
518
519 if (!priv->open_time)
520 return -EINVAL;
521
522 switch (mode) {
523 case CAN_MODE_START:
524 ret = mscan_restart(dev);
525 if (ret)
526 break;
527 if (netif_queue_stopped(dev))
528 netif_wake_queue(dev);
529 break;
530
531 default:
532 ret = -EOPNOTSUPP;
533 break;
534 }
535 return ret;
536}
537
538static int mscan_do_set_bittiming(struct net_device *dev)
539{
540 struct mscan_priv *priv = netdev_priv(dev);
541 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
542 struct can_bittiming *bt = &priv->can.bittiming;
543 u8 btr0, btr1;
544
545 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
546 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
547 BTR1_SET_TSEG2(bt->phase_seg2) |
548 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
549
550 dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n",
551 btr0, btr1);
552
553 out_8(&regs->canbtr0, btr0);
554 out_8(&regs->canbtr1, btr1);
555
556 return 0;
557}
558
559static int mscan_open(struct net_device *dev)
560{
561 int ret;
562 struct mscan_priv *priv = netdev_priv(dev);
563 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
564
565 /* common open */
566 ret = open_candev(dev);
567 if (ret)
568 return ret;
569
570 napi_enable(&priv->napi);
571
572 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
573 if (ret < 0) {
574 dev_err(dev->dev.parent, "failed to attach interrupt\n");
575 goto exit_napi_disable;
576 }
577
578 priv->open_time = jiffies;
579
580 clrbits8(&regs->canctl1, MSCAN_LISTEN);
581
582 ret = mscan_start(dev);
583 if (ret)
584 goto exit_free_irq;
585
586 netif_start_queue(dev);
587
588 return 0;
589
590exit_free_irq:
591 priv->open_time = 0;
592 free_irq(dev->irq, dev);
593exit_napi_disable:
594 napi_disable(&priv->napi);
595 close_candev(dev);
596 return ret;
597}
598
599static int mscan_close(struct net_device *dev)
600{
601 struct mscan_priv *priv = netdev_priv(dev);
602 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
603
604 netif_stop_queue(dev);
605 napi_disable(&priv->napi);
606
607 out_8(&regs->cantier, 0);
608 out_8(&regs->canrier, 0);
609 mscan_set_mode(dev, MSCAN_INIT_MODE);
610 close_candev(dev);
611 free_irq(dev->irq, dev);
612 priv->open_time = 0;
613
614 return 0;
615}
616
617static const struct net_device_ops mscan_netdev_ops = {
618 .ndo_open = mscan_open,
619 .ndo_stop = mscan_close,
620 .ndo_start_xmit = mscan_start_xmit,
621};
622
623int register_mscandev(struct net_device *dev, int mscan_clksrc)
624{
625 struct mscan_priv *priv = netdev_priv(dev);
626 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
627 u8 ctl1;
628
629 ctl1 = in_8(&regs->canctl1);
630 if (mscan_clksrc)
631 ctl1 |= MSCAN_CLKSRC;
632 else
633 ctl1 &= ~MSCAN_CLKSRC;
634
635 if (priv->type == MSCAN_TYPE_MPC5121)
636 ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */
637
638 ctl1 |= MSCAN_CANE;
639 out_8(&regs->canctl1, ctl1);
640 udelay(100);
641
642 /* acceptance mask/acceptance code (accept everything) */
643 out_be16(&regs->canidar1_0, 0);
644 out_be16(&regs->canidar3_2, 0);
645 out_be16(&regs->canidar5_4, 0);
646 out_be16(&regs->canidar7_6, 0);
647
648 out_be16(&regs->canidmr1_0, 0xffff);
649 out_be16(&regs->canidmr3_2, 0xffff);
650 out_be16(&regs->canidmr5_4, 0xffff);
651 out_be16(&regs->canidmr7_6, 0xffff);
652 /* Two 32 bit Acceptance Filters */
653 out_8(&regs->canidac, MSCAN_AF_32BIT);
654
655 mscan_set_mode(dev, MSCAN_INIT_MODE);
656
657 return register_candev(dev);
658}
659
660void unregister_mscandev(struct net_device *dev)
661{
662 struct mscan_priv *priv = netdev_priv(dev);
663 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
664 mscan_set_mode(dev, MSCAN_INIT_MODE);
665 clrbits8(&regs->canctl1, MSCAN_CANE);
666 unregister_candev(dev);
667}
668
669struct net_device *alloc_mscandev(void)
670{
671 struct net_device *dev;
672 struct mscan_priv *priv;
673 int i;
674
675 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
676 if (!dev)
677 return NULL;
678 priv = netdev_priv(dev);
679
680 dev->netdev_ops = &mscan_netdev_ops;
681
682 dev->flags |= IFF_ECHO; /* we support local echo */
683
684 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
685
686 priv->can.bittiming_const = &mscan_bittiming_const;
687 priv->can.do_set_bittiming = mscan_do_set_bittiming;
688 priv->can.do_set_mode = mscan_do_set_mode;
689 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
690
691 for (i = 0; i < TX_QUEUE_SIZE; i++) {
692 priv->tx_queue[i].id = i;
693 priv->tx_queue[i].mask = 1 << i;
694 }
695
696 return dev;
697}
698
699MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
700MODULE_LICENSE("GPL v2");
701MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");
diff --git a/drivers/net/can/mscan/mscan.h b/drivers/net/can/mscan/mscan.h
new file mode 100644
index 000000000000..4ff966473bc9
--- /dev/null
+++ b/drivers/net/can/mscan/mscan.h
@@ -0,0 +1,302 @@
1/*
2 * Definitions of consts/structs to drive the Freescale MSCAN.
3 *
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
5 * Varma Electronics Oy
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the version 2 of the GNU General Public License
9 * as published by the Free Software Foundation
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __MSCAN_H__
22#define __MSCAN_H__
23
24#include <linux/types.h>
25
26/* MSCAN control register 0 (CANCTL0) bits */
27#define MSCAN_RXFRM 0x80
28#define MSCAN_RXACT 0x40
29#define MSCAN_CSWAI 0x20
30#define MSCAN_SYNCH 0x10
31#define MSCAN_TIME 0x08
32#define MSCAN_WUPE 0x04
33#define MSCAN_SLPRQ 0x02
34#define MSCAN_INITRQ 0x01
35
36/* MSCAN control register 1 (CANCTL1) bits */
37#define MSCAN_CANE 0x80
38#define MSCAN_CLKSRC 0x40
39#define MSCAN_LOOPB 0x20
40#define MSCAN_LISTEN 0x10
41#define MSCAN_BORM 0x08
42#define MSCAN_WUPM 0x04
43#define MSCAN_SLPAK 0x02
44#define MSCAN_INITAK 0x01
45
46/* Use the MPC5XXX MSCAN variant? */
47#ifdef CONFIG_PPC
48#define MSCAN_FOR_MPC5XXX
49#endif
50
51#ifdef MSCAN_FOR_MPC5XXX
52#define MSCAN_CLKSRC_BUS 0
53#define MSCAN_CLKSRC_XTAL MSCAN_CLKSRC
54#define MSCAN_CLKSRC_IPS MSCAN_CLKSRC
55#else
56#define MSCAN_CLKSRC_BUS MSCAN_CLKSRC
57#define MSCAN_CLKSRC_XTAL 0
58#endif
59
60/* MSCAN receiver flag register (CANRFLG) bits */
61#define MSCAN_WUPIF 0x80
62#define MSCAN_CSCIF 0x40
63#define MSCAN_RSTAT1 0x20
64#define MSCAN_RSTAT0 0x10
65#define MSCAN_TSTAT1 0x08
66#define MSCAN_TSTAT0 0x04
67#define MSCAN_OVRIF 0x02
68#define MSCAN_RXF 0x01
69#define MSCAN_ERR_IF (MSCAN_OVRIF | MSCAN_CSCIF)
70#define MSCAN_RSTAT_MSK (MSCAN_RSTAT1 | MSCAN_RSTAT0)
71#define MSCAN_TSTAT_MSK (MSCAN_TSTAT1 | MSCAN_TSTAT0)
72#define MSCAN_STAT_MSK (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
73
74#define MSCAN_STATE_BUS_OFF (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
75 MSCAN_TSTAT1 | MSCAN_TSTAT0)
76#define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
77#define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
78#define MSCAN_STATE_ACTIVE 0
79#define MSCAN_STATE_WARNING 1
80#define MSCAN_STATE_PASSIVE 2
81#define MSCAN_STATE_BUSOFF 3
82
83/* MSCAN receiver interrupt enable register (CANRIER) bits */
84#define MSCAN_WUPIE 0x80
85#define MSCAN_CSCIE 0x40
86#define MSCAN_RSTATE1 0x20
87#define MSCAN_RSTATE0 0x10
88#define MSCAN_TSTATE1 0x08
89#define MSCAN_TSTATE0 0x04
90#define MSCAN_OVRIE 0x02
91#define MSCAN_RXFIE 0x01
92
93/* MSCAN transmitter flag register (CANTFLG) bits */
94#define MSCAN_TXE2 0x04
95#define MSCAN_TXE1 0x02
96#define MSCAN_TXE0 0x01
97#define MSCAN_TXE (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
98
99/* MSCAN transmitter interrupt enable register (CANTIER) bits */
100#define MSCAN_TXIE2 0x04
101#define MSCAN_TXIE1 0x02
102#define MSCAN_TXIE0 0x01
103#define MSCAN_TXIE (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
104
105/* MSCAN transmitter message abort request (CANTARQ) bits */
106#define MSCAN_ABTRQ2 0x04
107#define MSCAN_ABTRQ1 0x02
108#define MSCAN_ABTRQ0 0x01
109
110/* MSCAN transmitter message abort ack (CANTAAK) bits */
111#define MSCAN_ABTAK2 0x04
112#define MSCAN_ABTAK1 0x02
113#define MSCAN_ABTAK0 0x01
114
115/* MSCAN transmit buffer selection (CANTBSEL) bits */
116#define MSCAN_TX2 0x04
117#define MSCAN_TX1 0x02
118#define MSCAN_TX0 0x01
119
120/* MSCAN ID acceptance control register (CANIDAC) bits */
121#define MSCAN_IDAM1 0x20
122#define MSCAN_IDAM0 0x10
123#define MSCAN_IDHIT2 0x04
124#define MSCAN_IDHIT1 0x02
125#define MSCAN_IDHIT0 0x01
126
127#define MSCAN_AF_32BIT 0x00
128#define MSCAN_AF_16BIT MSCAN_IDAM0
129#define MSCAN_AF_8BIT MSCAN_IDAM1
130#define MSCAN_AF_CLOSED (MSCAN_IDAM0|MSCAN_IDAM1)
131#define MSCAN_AF_MASK (~(MSCAN_IDAM0|MSCAN_IDAM1))
132
133/* MSCAN Miscellaneous Register (CANMISC) bits */
134#define MSCAN_BOHOLD 0x01
135
136/* MSCAN Identifier Register (IDR) bits */
137#define MSCAN_SFF_RTR_SHIFT 4
138#define MSCAN_EFF_RTR_SHIFT 0
139#define MSCAN_EFF_FLAGS 0x18 /* IDE + SRR */
140
141#ifdef MSCAN_FOR_MPC5XXX
142#define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
143#define _MSCAN_RESERVED_DSR_SIZE 2
144#else
145#define _MSCAN_RESERVED_(n, num)
146#define _MSCAN_RESERVED_DSR_SIZE 0
147#endif
148
149/* Structure of the hardware registers */
150struct mscan_regs {
151 /* (see doc S12MSCANV3/D) MPC5200 MSCAN */
152 u8 canctl0; /* + 0x00 0x00 */
153 u8 canctl1; /* + 0x01 0x01 */
154 _MSCAN_RESERVED_(1, 2); /* + 0x02 */
155 u8 canbtr0; /* + 0x04 0x02 */
156 u8 canbtr1; /* + 0x05 0x03 */
157 _MSCAN_RESERVED_(2, 2); /* + 0x06 */
158 u8 canrflg; /* + 0x08 0x04 */
159 u8 canrier; /* + 0x09 0x05 */
160 _MSCAN_RESERVED_(3, 2); /* + 0x0a */
161 u8 cantflg; /* + 0x0c 0x06 */
162 u8 cantier; /* + 0x0d 0x07 */
163 _MSCAN_RESERVED_(4, 2); /* + 0x0e */
164 u8 cantarq; /* + 0x10 0x08 */
165 u8 cantaak; /* + 0x11 0x09 */
166 _MSCAN_RESERVED_(5, 2); /* + 0x12 */
167 u8 cantbsel; /* + 0x14 0x0a */
168 u8 canidac; /* + 0x15 0x0b */
169 u8 reserved; /* + 0x16 0x0c */
170 _MSCAN_RESERVED_(6, 2); /* + 0x17 */
171 u8 canmisc; /* + 0x19 0x0d */
172 _MSCAN_RESERVED_(7, 2); /* + 0x1a */
173 u8 canrxerr; /* + 0x1c 0x0e */
174 u8 cantxerr; /* + 0x1d 0x0f */
175 _MSCAN_RESERVED_(8, 2); /* + 0x1e */
176 u16 canidar1_0; /* + 0x20 0x10 */
177 _MSCAN_RESERVED_(9, 2); /* + 0x22 */
178 u16 canidar3_2; /* + 0x24 0x12 */
179 _MSCAN_RESERVED_(10, 2); /* + 0x26 */
180 u16 canidmr1_0; /* + 0x28 0x14 */
181 _MSCAN_RESERVED_(11, 2); /* + 0x2a */
182 u16 canidmr3_2; /* + 0x2c 0x16 */
183 _MSCAN_RESERVED_(12, 2); /* + 0x2e */
184 u16 canidar5_4; /* + 0x30 0x18 */
185 _MSCAN_RESERVED_(13, 2); /* + 0x32 */
186 u16 canidar7_6; /* + 0x34 0x1a */
187 _MSCAN_RESERVED_(14, 2); /* + 0x36 */
188 u16 canidmr5_4; /* + 0x38 0x1c */
189 _MSCAN_RESERVED_(15, 2); /* + 0x3a */
190 u16 canidmr7_6; /* + 0x3c 0x1e */
191 _MSCAN_RESERVED_(16, 2); /* + 0x3e */
192 struct {
193 u16 idr1_0; /* + 0x40 0x20 */
194 _MSCAN_RESERVED_(17, 2); /* + 0x42 */
195 u16 idr3_2; /* + 0x44 0x22 */
196 _MSCAN_RESERVED_(18, 2); /* + 0x46 */
197 u16 dsr1_0; /* + 0x48 0x24 */
198 _MSCAN_RESERVED_(19, 2); /* + 0x4a */
199 u16 dsr3_2; /* + 0x4c 0x26 */
200 _MSCAN_RESERVED_(20, 2); /* + 0x4e */
201 u16 dsr5_4; /* + 0x50 0x28 */
202 _MSCAN_RESERVED_(21, 2); /* + 0x52 */
203 u16 dsr7_6; /* + 0x54 0x2a */
204 _MSCAN_RESERVED_(22, 2); /* + 0x56 */
205 u8 dlr; /* + 0x58 0x2c */
206 u8 reserved; /* + 0x59 0x2d */
207 _MSCAN_RESERVED_(23, 2); /* + 0x5a */
208 u16 time; /* + 0x5c 0x2e */
209 } rx;
210 _MSCAN_RESERVED_(24, 2); /* + 0x5e */
211 struct {
212 u16 idr1_0; /* + 0x60 0x30 */
213 _MSCAN_RESERVED_(25, 2); /* + 0x62 */
214 u16 idr3_2; /* + 0x64 0x32 */
215 _MSCAN_RESERVED_(26, 2); /* + 0x66 */
216 u16 dsr1_0; /* + 0x68 0x34 */
217 _MSCAN_RESERVED_(27, 2); /* + 0x6a */
218 u16 dsr3_2; /* + 0x6c 0x36 */
219 _MSCAN_RESERVED_(28, 2); /* + 0x6e */
220 u16 dsr5_4; /* + 0x70 0x38 */
221 _MSCAN_RESERVED_(29, 2); /* + 0x72 */
222 u16 dsr7_6; /* + 0x74 0x3a */
223 _MSCAN_RESERVED_(30, 2); /* + 0x76 */
224 u8 dlr; /* + 0x78 0x3c */
225 u8 tbpr; /* + 0x79 0x3d */
226 _MSCAN_RESERVED_(31, 2); /* + 0x7a */
227 u16 time; /* + 0x7c 0x3e */
228 } tx;
229 _MSCAN_RESERVED_(32, 2); /* + 0x7e */
230} __attribute__ ((packed));
231
232#undef _MSCAN_RESERVED_
233#define MSCAN_REGION sizeof(struct mscan)
234
235#define MSCAN_NORMAL_MODE 0
236#define MSCAN_SLEEP_MODE MSCAN_SLPRQ
237#define MSCAN_INIT_MODE (MSCAN_INITRQ | MSCAN_SLPRQ)
238#define MSCAN_POWEROFF_MODE (MSCAN_CSWAI | MSCAN_SLPRQ)
239#define MSCAN_SET_MODE_RETRIES 255
240#define MSCAN_ECHO_SKB_MAX 3
241#define MSCAN_RX_INTS_ENABLE (MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | \
242 MSCAN_RSTATE1 | MSCAN_RSTATE0 | \
243 MSCAN_TSTATE1 | MSCAN_TSTATE0)
244
245/* MSCAN type variants */
246enum {
247 MSCAN_TYPE_MPC5200,
248 MSCAN_TYPE_MPC5121
249};
250
251#define BTR0_BRP_MASK 0x3f
252#define BTR0_SJW_SHIFT 6
253#define BTR0_SJW_MASK (0x3 << BTR0_SJW_SHIFT)
254
255#define BTR1_TSEG1_MASK 0xf
256#define BTR1_TSEG2_SHIFT 4
257#define BTR1_TSEG2_MASK (0x7 << BTR1_TSEG2_SHIFT)
258#define BTR1_SAM_SHIFT 7
259
260#define BTR0_SET_BRP(brp) (((brp) - 1) & BTR0_BRP_MASK)
261#define BTR0_SET_SJW(sjw) ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
262 BTR0_SJW_MASK)
263
264#define BTR1_SET_TSEG1(tseg1) (((tseg1) - 1) & BTR1_TSEG1_MASK)
265#define BTR1_SET_TSEG2(tseg2) ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
266 BTR1_TSEG2_MASK)
267#define BTR1_SET_SAM(sam) ((sam) ? 1 << BTR1_SAM_SHIFT : 0)
268
269#define F_RX_PROGRESS 0
270#define F_TX_PROGRESS 1
271#define F_TX_WAIT_ALL 2
272
273#define TX_QUEUE_SIZE 3
274
275struct tx_queue_entry {
276 struct list_head list;
277 u8 mask;
278 u8 id;
279};
280
281struct mscan_priv {
282 struct can_priv can; /* must be the first member */
283 unsigned int type; /* MSCAN type variants */
284 long open_time;
285 unsigned long flags;
286 void __iomem *reg_base; /* ioremap'ed address to registers */
287 u8 shadow_statflg;
288 u8 shadow_canrier;
289 u8 cur_pri;
290 u8 prev_buf_id;
291 u8 tx_active;
292
293 struct list_head tx_head;
294 struct tx_queue_entry tx_queue[TX_QUEUE_SIZE];
295 struct napi_struct napi;
296};
297
298extern struct net_device *alloc_mscandev(void);
299extern int register_mscandev(struct net_device *dev, int mscan_clksrc);
300extern void unregister_mscandev(struct net_device *dev);
301
302#endif /* __MSCAN_H__ */
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