aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/bnx2x_fw_defs.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/bnx2x_fw_defs.h')
-rw-r--r--drivers/net/bnx2x_fw_defs.h379
1 files changed, 274 insertions, 105 deletions
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
index e2df23803598..931dcace5628 100644
--- a/drivers/net/bnx2x_fw_defs.h
+++ b/drivers/net/bnx2x_fw_defs.h
@@ -12,48 +12,117 @@
12 (IS_E1H_OFFSET ? 0x7000 : 0x1000) 12 (IS_E1H_OFFSET ? 0x7000 : 0x1000)
13#define CSTORM_ASSERT_LIST_OFFSET(idx) \ 13#define CSTORM_ASSERT_LIST_OFFSET(idx) \
14 (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 14 (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
15#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 15#define CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(function, index) \
16 (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \ 16 (IS_E1H_OFFSET ? (0x8622 + ((function>>1) * 0x40) + \
17 ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ 17 ((function&1) * 0x100) + (index * 0x4)) : (0x3562 + (function * \
18 0x40) + (index * 0x4))) 18 0x40) + (index * 0x4)))
19#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 19#define CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(function, index) \
20 (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \ 20 (IS_E1H_OFFSET ? (0x8822 + ((function>>1) * 0x80) + \
21 ((function&1) * 0x100)) : (0x1900 + (function * 0x40))) 21 ((function&1) * 0x200) + (index * 0x4)) : (0x35e2 + (function * \
22#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ 22 0x80) + (index * 0x4)))
23 (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \ 23#define CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(function) \
24 ((function&1) * 0x100)) : (0x1908 + (function * 0x40))) 24 (IS_E1H_OFFSET ? (0x8600 + ((function>>1) * 0x40) + \
25 ((function&1) * 0x100)) : (0x3540 + (function * 0x40)))
26#define CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(function) \
27 (IS_E1H_OFFSET ? (0x8800 + ((function>>1) * 0x80) + \
28 ((function&1) * 0x200)) : (0x35c0 + (function * 0x80)))
29#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(function) \
30 (IS_E1H_OFFSET ? (0x8608 + ((function>>1) * 0x40) + \
31 ((function&1) * 0x100)) : (0x3548 + (function * 0x40)))
32#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(function) \
33 (IS_E1H_OFFSET ? (0x8808 + ((function>>1) * 0x80) + \
34 ((function&1) * 0x200)) : (0x35c8 + (function * 0x80)))
25#define CSTORM_FUNCTION_MODE_OFFSET \ 35#define CSTORM_FUNCTION_MODE_OFFSET \
26 (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff) 36 (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
27#define CSTORM_HC_BTR_OFFSET(port) \ 37#define CSTORM_HC_BTR_C_OFFSET(port) \
28 (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) 38 (IS_E1H_OFFSET ? (0x8c04 + (port * 0xf0)) : (0x36c4 + (port * 0xc0)))
29#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ 39#define CSTORM_HC_BTR_U_OFFSET(port) \
30 (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ 40 (IS_E1H_OFFSET ? (0x8de4 + (port * 0xf0)) : (0x3844 + (port * 0xc0)))
31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ 41#define CSTORM_ISCSI_CQ_SIZE_OFFSET(function) \
42 (IS_E1H_OFFSET ? (0x6680 + (function * 0x8)) : (0x25a0 + \
43 (function * 0x8)))
44#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
45 (IS_E1H_OFFSET ? (0x66c0 + (function * 0x8)) : (0x25b0 + \
46 (function * 0x8)))
47#define CSTORM_ISCSI_EQ_CONS_OFFSET(function, eqIdx) \
48 (IS_E1H_OFFSET ? (0x6040 + (function * 0xc0) + (eqIdx * 0x18)) : \
49 (0x2410 + (function * 0xc0) + (eqIdx * 0x18)))
50#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(function, eqIdx) \
51 (IS_E1H_OFFSET ? (0x6044 + (function * 0xc0) + (eqIdx * 0x18)) : \
52 (0x2414 + (function * 0xc0) + (eqIdx * 0x18)))
53#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(function, eqIdx) \
54 (IS_E1H_OFFSET ? (0x604c + (function * 0xc0) + (eqIdx * 0x18)) : \
55 (0x241c + (function * 0xc0) + (eqIdx * 0x18)))
56#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(function, eqIdx) \
57 (IS_E1H_OFFSET ? (0x6057 + (function * 0xc0) + (eqIdx * 0x18)) : \
58 (0x2427 + (function * 0xc0) + (eqIdx * 0x18)))
59#define CSTORM_ISCSI_EQ_PROD_OFFSET(function, eqIdx) \
60 (IS_E1H_OFFSET ? (0x6042 + (function * 0xc0) + (eqIdx * 0x18)) : \
61 (0x2412 + (function * 0xc0) + (eqIdx * 0x18)))
62#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(function, eqIdx) \
63 (IS_E1H_OFFSET ? (0x6056 + (function * 0xc0) + (eqIdx * 0x18)) : \
64 (0x2426 + (function * 0xc0) + (eqIdx * 0x18)))
65#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(function, eqIdx) \
66 (IS_E1H_OFFSET ? (0x6054 + (function * 0xc0) + (eqIdx * 0x18)) : \
67 (0x2424 + (function * 0xc0) + (eqIdx * 0x18)))
68#define CSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
69 (IS_E1H_OFFSET ? (0x6640 + (function * 0x8)) : (0x2590 + \
70 (function * 0x8)))
71#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
72 (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x2404 + \
73 (function * 0x8)))
74#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
75 (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x2402 + \
76 (function * 0x8)))
77#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
78 (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x2400 + \
79 (function * 0x8)))
80#define CSTORM_SB_HC_DISABLE_C_OFFSET(port, cpu_id, index) \
81 (IS_E1H_OFFSET ? (0x811a + (port * 0x280) + (cpu_id * 0x28) + \
82 (index * 0x4)) : (0x305a + (port * 0x280) + (cpu_id * 0x28) + \
83 (index * 0x4)))
84#define CSTORM_SB_HC_DISABLE_U_OFFSET(port, cpu_id, index) \
85 (IS_E1H_OFFSET ? (0xb01a + (port * 0x800) + (cpu_id * 0x80) + \
86 (index * 0x4)) : (0x401a + (port * 0x800) + (cpu_id * 0x80) + \
32 (index * 0x4))) 87 (index * 0x4)))
33#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ 88#define CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, cpu_id, index) \
34 (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ 89 (IS_E1H_OFFSET ? (0x8118 + (port * 0x280) + (cpu_id * 0x28) + \
35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ 90 (index * 0x4)) : (0x3058 + (port * 0x280) + (cpu_id * 0x28) + \
36 (index * 0x4))) 91 (index * 0x4)))
37#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ 92#define CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, cpu_id, index) \
38 (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ 93 (IS_E1H_OFFSET ? (0xb018 + (port * 0x800) + (cpu_id * 0x80) + \
39 (0x1400 + (port * 0x280) + (cpu_id * 0x28))) 94 (index * 0x4)) : (0x4018 + (port * 0x800) + (cpu_id * 0x80) + \
40#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ 95 (index * 0x4)))
41 (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ 96#define CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, cpu_id) \
42 (0x1408 + (port * 0x280) + (cpu_id * 0x28))) 97 (IS_E1H_OFFSET ? (0x8100 + (port * 0x280) + (cpu_id * 0x28)) : \
98 (0x3040 + (port * 0x280) + (cpu_id * 0x28)))
99#define CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, cpu_id) \
100 (IS_E1H_OFFSET ? (0xb000 + (port * 0x800) + (cpu_id * 0x80)) : \
101 (0x4000 + (port * 0x800) + (cpu_id * 0x80)))
102#define CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, cpu_id) \
103 (IS_E1H_OFFSET ? (0x8108 + (port * 0x280) + (cpu_id * 0x28)) : \
104 (0x3048 + (port * 0x280) + (cpu_id * 0x28)))
105#define CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, cpu_id) \
106 (IS_E1H_OFFSET ? (0xb008 + (port * 0x800) + (cpu_id * 0x80)) : \
107 (0x4008 + (port * 0x800) + (cpu_id * 0x80)))
108#define CSTORM_SB_STATUS_BLOCK_C_SIZE 0x10
109#define CSTORM_SB_STATUS_BLOCK_U_SIZE 0x60
43#define CSTORM_STATS_FLAGS_OFFSET(function) \ 110#define CSTORM_STATS_FLAGS_OFFSET(function) \
44 (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \ 111 (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
45 (function * 0x8))) 112 (function * 0x8)))
46#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ 113#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
47 (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff) 114 (IS_E1H_OFFSET ? (0x3200 + (function * 0x20)) : 0xffffffff)
48#define TSTORM_ASSERT_LIST_INDEX_OFFSET \ 115#define TSTORM_ASSERT_LIST_INDEX_OFFSET \
49 (IS_E1H_OFFSET ? 0xa000 : 0x1000) 116 (IS_E1H_OFFSET ? 0xa000 : 0x1000)
50#define TSTORM_ASSERT_LIST_OFFSET(idx) \ 117#define TSTORM_ASSERT_LIST_OFFSET(idx) \
51 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 118 (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ 119#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53 (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \ 120 (IS_E1H_OFFSET ? (0x33a0 + (port * 0x1a0) + (client_id * 0x10)) \
54 : (0x9c0 + (port * 0x130) + (client_id * 0x10))) 121 : (0x9c0 + (port * 0x120) + (client_id * 0x10)))
55#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \ 122#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \
56 (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff) 123 (IS_E1H_OFFSET ? 0x1ed8 : 0xffffffff)
124#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
125 (IS_E1H_OFFSET ? 0x1eda : 0xffffffff)
57#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 126#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
58 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ 127 (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
59 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ 128 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@@ -65,95 +134,133 @@
65 (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \ 134 (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
66 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) 135 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
67#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ 136#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
68 (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \ 137 (IS_E1H_OFFSET ? (0x2940 + (function * 0x8)) : (0x4928 + \
69 (function * 0x8))) 138 (function * 0x8)))
70#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ 139#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
71 (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \ 140 (IS_E1H_OFFSET ? (0x3000 + (function * 0x40)) : (0x1500 + \
72 (function * 0x38))) 141 (function * 0x40)))
73#define TSTORM_FUNCTION_MODE_OFFSET \ 142#define TSTORM_FUNCTION_MODE_OFFSET \
74 (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff) 143 (IS_E1H_OFFSET ? 0x1ed0 : 0xffffffff)
75#define TSTORM_HC_BTR_OFFSET(port) \ 144#define TSTORM_HC_BTR_OFFSET(port) \
76 (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) 145 (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
77#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ 146#define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
78 (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \ 147 (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
79 (function * 0x80))) 148 (function * 0x80)))
80#define TSTORM_INDIRECTION_TABLE_SIZE 0x80 149#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
150#define TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(function, pblEntry) \
151 (IS_E1H_OFFSET ? (0x60c0 + (function * 0x40) + (pblEntry * 0x8)) \
152 : (0x4c30 + (function * 0x40) + (pblEntry * 0x8)))
153#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
154 (IS_E1H_OFFSET ? (0x6340 + (function * 0x8)) : (0x4cd0 + \
155 (function * 0x8)))
156#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
157 (IS_E1H_OFFSET ? (0x6004 + (function * 0x8)) : (0x4c04 + \
158 (function * 0x8)))
159#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
160 (IS_E1H_OFFSET ? (0x6002 + (function * 0x8)) : (0x4c02 + \
161 (function * 0x8)))
162#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
163 (IS_E1H_OFFSET ? (0x6000 + (function * 0x8)) : (0x4c00 + \
164 (function * 0x8)))
165#define TSTORM_ISCSI_RQ_SIZE_OFFSET(function) \
166 (IS_E1H_OFFSET ? (0x6080 + (function * 0x8)) : (0x4c20 + \
167 (function * 0x8)))
168#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
169 (IS_E1H_OFFSET ? (0x6040 + (function * 0x8)) : (0x4c10 + \
170 (function * 0x8)))
171#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(function) \
172 (IS_E1H_OFFSET ? (0x6042 + (function * 0x8)) : (0x4c12 + \
173 (function * 0x8)))
174#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(function) \
175 (IS_E1H_OFFSET ? (0x6044 + (function * 0x8)) : (0x4c14 + \
176 (function * 0x8)))
81#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ 177#define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
82 (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \ 178 (IS_E1H_OFFSET ? (0x3008 + (function * 0x40)) : (0x1508 + \
83 (function * 0x38))) 179 (function * 0x40)))
84#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ 180#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
85 (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \ 181 (IS_E1H_OFFSET ? (0x2010 + (port * 0x490) + (stats_counter_id * \
86 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50))) 182 0x40)) : (0x4010 + (port * 0x490) + (stats_counter_id * 0x40)))
87#define TSTORM_STATS_FLAGS_OFFSET(function) \ 183#define TSTORM_STATS_FLAGS_OFFSET(function) \
88 (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \ 184 (IS_E1H_OFFSET ? (0x29c0 + (function * 0x8)) : (0x4948 + \
89 (function * 0x8))) 185 (function * 0x8)))
90#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20) 186#define TSTORM_TCP_MAX_CWND_OFFSET(function) \
91#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10) 187 (IS_E1H_OFFSET ? (0x4004 + (function * 0x8)) : (0x1fb4 + \
92#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200) 188 (function * 0x8)))
189#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa000 : 0x3000)
190#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2000 : 0x1000)
93#define USTORM_ASSERT_LIST_INDEX_OFFSET \ 191#define USTORM_ASSERT_LIST_INDEX_OFFSET \
94 (IS_E1H_OFFSET ? 0x8960 : 0x1000) 192 (IS_E1H_OFFSET ? 0x8000 : 0x1000)
95#define USTORM_ASSERT_LIST_OFFSET(idx) \ 193#define USTORM_ASSERT_LIST_OFFSET(idx) \
96 (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 194 (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
97#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ 195#define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
98 (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \ 196 (IS_E1H_OFFSET ? (0x1010 + (port * 0x680) + (clientId * 0x40)) : \
99 (0x5330 + (port * 0x260) + (clientId * 0x20))) 197 (0x4010 + (port * 0x360) + (clientId * 0x30)))
100#define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 198#define USTORM_CQE_PAGE_NEXT_OFFSET(port, clientId) \
101 (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \ 199 (IS_E1H_OFFSET ? (0x1028 + (port * 0x680) + (clientId * 0x40)) : \
102 ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ 200 (0x4028 + (port * 0x360) + (clientId * 0x30)))
103 0x40) + (index * 0x4))) 201#define USTORM_ETH_PAUSE_ENABLED_OFFSET(port) \
104#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ 202 (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
105 (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \
106 ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
107#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
108 (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \
109 ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
110#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \ 203#define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \
111 (IS_E1H_OFFSET ? (0x8020 + (port * 0x4b0) + (clientId * 0x30)) : \ 204 (IS_E1H_OFFSET ? (0x1030 + (port * 0x680) + (clientId * 0x40)) : \
112 0xffffffff) 205 0xffffffff)
113#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ 206#define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
114 (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1d98 + \ 207 (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1dd0 + \
115 (function * 0x8))) 208 (function * 0x8)))
116#define USTORM_FUNCTION_MODE_OFFSET \ 209#define USTORM_FUNCTION_MODE_OFFSET \
117 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) 210 (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
118#define USTORM_HC_BTR_OFFSET(port) \ 211#define USTORM_ISCSI_CQ_SIZE_OFFSET(function) \
119 (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) 212 (IS_E1H_OFFSET ? (0x7044 + (function * 0x8)) : (0x2414 + \
213 (function * 0x8)))
214#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(function) \
215 (IS_E1H_OFFSET ? (0x7046 + (function * 0x8)) : (0x2416 + \
216 (function * 0x8)))
217#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(function) \
218 (IS_E1H_OFFSET ? (0x7688 + (function * 0x8)) : (0x29c8 + \
219 (function * 0x8)))
220#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(function) \
221 (IS_E1H_OFFSET ? (0x7648 + (function * 0x8)) : (0x29b8 + \
222 (function * 0x8)))
223#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
224 (IS_E1H_OFFSET ? (0x7004 + (function * 0x8)) : (0x2404 + \
225 (function * 0x8)))
226#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
227 (IS_E1H_OFFSET ? (0x7002 + (function * 0x8)) : (0x2402 + \
228 (function * 0x8)))
229#define USTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
230 (IS_E1H_OFFSET ? (0x7000 + (function * 0x8)) : (0x2400 + \
231 (function * 0x8)))
232#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
233 (IS_E1H_OFFSET ? (0x7040 + (function * 0x8)) : (0x2410 + \
234 (function * 0x8)))
235#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(function) \
236 (IS_E1H_OFFSET ? (0x7080 + (function * 0x8)) : (0x2420 + \
237 (function * 0x8)))
238#define USTORM_ISCSI_RQ_SIZE_OFFSET(function) \
239 (IS_E1H_OFFSET ? (0x7084 + (function * 0x8)) : (0x2424 + \
240 (function * 0x8)))
120#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ 241#define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
121 (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \ 242 (IS_E1H_OFFSET ? (0x1018 + (port * 0x680) + (clientId * 0x40)) : \
122 (0x5328 + (port * 0x260) + (clientId * 0x20))) 243 (0x4018 + (port * 0x360) + (clientId * 0x30)))
123#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ 244#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
124 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \ 245 (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x1da8 + \
125 (function * 0x8))) 246 (function * 0x8)))
126#define USTORM_PAUSE_ENABLED_OFFSET(port) \
127 (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff)
128#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ 247#define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
129 (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \ 248 (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \
130 0x28)) : (0x4740 + (port * 0x2d0) + (stats_counter_id * 0x28))) 249 0x28)) : (0x1500 + (port * 0x2d0) + (stats_counter_id * 0x28)))
131#define USTORM_RX_PRODS_OFFSET(port, client_id) \ 250#define USTORM_RX_PRODS_OFFSET(port, client_id) \
132 (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \ 251 (IS_E1H_OFFSET ? (0x1000 + (port * 0x680) + (client_id * 0x40)) \
133 : (0x5318 + (port * 0x260) + (client_id * 0x20))) 252 : (0x4000 + (port * 0x360) + (client_id * 0x30)))
134#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
135 (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
136 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
137 (index * 0x4)))
138#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
139 (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
140 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
141 (index * 0x4)))
142#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
143 (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
144 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
145#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
146 (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
147 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
148#define USTORM_STATS_FLAGS_OFFSET(function) \ 253#define USTORM_STATS_FLAGS_OFFSET(function) \
149 (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1d80 + \ 254 (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1db8 + \
150 (function * 0x8))) 255 (function * 0x8)))
256#define USTORM_TPA_BTR_OFFSET (IS_E1H_OFFSET ? 0x3da5 : 0x5095)
257#define USTORM_TPA_BTR_SIZE 0x1
151#define XSTORM_ASSERT_LIST_INDEX_OFFSET \ 258#define XSTORM_ASSERT_LIST_INDEX_OFFSET \
152 (IS_E1H_OFFSET ? 0x9000 : 0x1000) 259 (IS_E1H_OFFSET ? 0x9000 : 0x1000)
153#define XSTORM_ASSERT_LIST_OFFSET(idx) \ 260#define XSTORM_ASSERT_LIST_OFFSET(idx) \
154 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) 261 (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
155#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ 262#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
156 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50))) 263 (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3a80 + (port * 0x50)))
157#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ 264#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
158 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ 265 (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
159 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ 266 ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
@@ -165,22 +272,73 @@
165 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ 272 (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
166 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) 273 ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
167#define XSTORM_E1HOV_OFFSET(function) \ 274#define XSTORM_E1HOV_OFFSET(function) \
168 (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff) 275 (IS_E1H_OFFSET ? (0x2c10 + (function * 0x8)) : 0xffffffff)
169#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ 276#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
170 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \ 277 (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3a50 + \
171 (function * 0x8))) 278 (function * 0x8)))
172#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ 279#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
173 (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \ 280 (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3b60 + \
174 (function * 0x90))) 281 (function * 0x90)))
175#define XSTORM_FUNCTION_MODE_OFFSET \ 282#define XSTORM_FUNCTION_MODE_OFFSET \
176 (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff) 283 (IS_E1H_OFFSET ? 0x2c50 : 0xffffffff)
177#define XSTORM_HC_BTR_OFFSET(port) \ 284#define XSTORM_HC_BTR_OFFSET(port) \
178 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) 285 (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
286#define XSTORM_ISCSI_HQ_SIZE_OFFSET(function) \
287 (IS_E1H_OFFSET ? (0x80c0 + (function * 0x8)) : (0x1c30 + \
288 (function * 0x8)))
289#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(function) \
290 (IS_E1H_OFFSET ? (0x8080 + (function * 0x8)) : (0x1c20 + \
291 (function * 0x8)))
292#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(function) \
293 (IS_E1H_OFFSET ? (0x8081 + (function * 0x8)) : (0x1c21 + \
294 (function * 0x8)))
295#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(function) \
296 (IS_E1H_OFFSET ? (0x8082 + (function * 0x8)) : (0x1c22 + \
297 (function * 0x8)))
298#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(function) \
299 (IS_E1H_OFFSET ? (0x8083 + (function * 0x8)) : (0x1c23 + \
300 (function * 0x8)))
301#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(function) \
302 (IS_E1H_OFFSET ? (0x8084 + (function * 0x8)) : (0x1c24 + \
303 (function * 0x8)))
304#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(function) \
305 (IS_E1H_OFFSET ? (0x8085 + (function * 0x8)) : (0x1c25 + \
306 (function * 0x8)))
307#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(function) \
308 (IS_E1H_OFFSET ? (0x8086 + (function * 0x8)) : (0x1c26 + \
309 (function * 0x8)))
310#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(function) \
311 (IS_E1H_OFFSET ? (0x8004 + (function * 0x8)) : (0x1c04 + \
312 (function * 0x8)))
313#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(function) \
314 (IS_E1H_OFFSET ? (0x8002 + (function * 0x8)) : (0x1c02 + \
315 (function * 0x8)))
316#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(function) \
317 (IS_E1H_OFFSET ? (0x8000 + (function * 0x8)) : (0x1c00 + \
318 (function * 0x8)))
319#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(function) \
320 (IS_E1H_OFFSET ? (0x80c4 + (function * 0x8)) : (0x1c34 + \
321 (function * 0x8)))
322#define XSTORM_ISCSI_SQ_SIZE_OFFSET(function) \
323 (IS_E1H_OFFSET ? (0x80c2 + (function * 0x8)) : (0x1c32 + \
324 (function * 0x8)))
325#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(function) \
326 (IS_E1H_OFFSET ? (0x8043 + (function * 0x8)) : (0x1c13 + \
327 (function * 0x8)))
328#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(function) \
329 (IS_E1H_OFFSET ? (0x8042 + (function * 0x8)) : (0x1c12 + \
330 (function * 0x8)))
331#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(function) \
332 (IS_E1H_OFFSET ? (0x8041 + (function * 0x8)) : (0x1c11 + \
333 (function * 0x8)))
334#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(function) \
335 (IS_E1H_OFFSET ? (0x8040 + (function * 0x8)) : (0x1c10 + \
336 (function * 0x8)))
179#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ 337#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
180 (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \ 338 (IS_E1H_OFFSET ? (0xc000 + (port * 0x360) + (stats_counter_id * \
181 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38))) 339 0x30)) : (0x3378 + (port * 0x360) + (stats_counter_id * 0x30)))
182#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ 340#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
183 (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \ 341 (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3b20 + \
184 (function * 0x90))) 342 (function * 0x90)))
185#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ 343#define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
186 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ 344 (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
@@ -189,8 +347,15 @@
189 (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \ 347 (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
190 (function * 0x10))) 348 (function * 0x10)))
191#define XSTORM_STATS_FLAGS_OFFSET(function) \ 349#define XSTORM_STATS_FLAGS_OFFSET(function) \
192 (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \ 350 (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3a40 + \
193 (function * 0x8))) 351 (function * 0x8)))
352#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port) \
353 (IS_E1H_OFFSET ? (0x4000 + (port * 0x8)) : (0x1960 + (port * 0x8)))
354#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port) \
355 (IS_E1H_OFFSET ? (0x4001 + (port * 0x8)) : (0x1961 + (port * 0x8)))
356#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(function) \
357 (IS_E1H_OFFSET ? (0x4060 + ((function>>1) * 0x8) + ((function&1) \
358 * 0x4)) : (0x1978 + (function * 0x4)))
194#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 359#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
195 360
196/** 361/**
@@ -211,6 +376,9 @@
211#define TCP_IPV4_HASH_TYPE 2 376#define TCP_IPV4_HASH_TYPE 2
212#define IPV6_HASH_TYPE 3 377#define IPV6_HASH_TYPE 3
213#define TCP_IPV6_HASH_TYPE 4 378#define TCP_IPV6_HASH_TYPE 4
379#define VLAN_PRI_HASH_TYPE 5
380#define E1HOV_PRI_HASH_TYPE 6
381#define DSCP_HASH_TYPE 7
214 382
215 383
216/* Ethernet Ring parameters */ 384/* Ethernet Ring parameters */
@@ -218,30 +386,26 @@
218#define FIRST_BD_IN_PKT 0 386#define FIRST_BD_IN_PKT 0
219#define PARSE_BD_INDEX 1 387#define PARSE_BD_INDEX 1
220#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) 388#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
221 389#define U_ETH_NUM_OF_SGES_TO_FETCH 8
390#define U_ETH_MAX_SGES_FOR_PACKET 3
222 391
223/* Rx ring params */ 392/* Rx ring params */
224#define U_ETH_LOCAL_BD_RING_SIZE 16 393#define U_ETH_LOCAL_BD_RING_SIZE 8
225#define U_ETH_LOCAL_SGE_RING_SIZE 12 394#define U_ETH_LOCAL_SGE_RING_SIZE 10
226#define U_ETH_SGL_SIZE 8 395#define U_ETH_SGL_SIZE 8
227 396
228 397
229#define U_ETH_BDS_PER_PAGE_MASK \
230 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
231#define U_ETH_CQE_PER_PAGE_MASK \
232 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
233#define U_ETH_SGES_PER_PAGE_MASK \
234 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
235
236#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ 398#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
237 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) 399 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
238 400
239 401#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
240#define TU_ETH_CQES_PER_PAGE \
241 (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
242#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) 402#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
243#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) 403#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
244 404
405#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
406#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
407#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
408
245#define U_ETH_UNDEFINED_Q 0xFF 409#define U_ETH_UNDEFINED_Q 0xFF
246 410
247/* values of command IDs in the ramrod message */ 411/* values of command IDs in the ramrod message */
@@ -266,8 +430,8 @@
266#define T_ETH_CRC32_HASH_SEED 0x00000000 430#define T_ETH_CRC32_HASH_SEED 0x00000000
267 431
268/* Maximal L2 clients supported */ 432/* Maximal L2 clients supported */
269#define ETH_MAX_RX_CLIENTS_E1 19 433#define ETH_MAX_RX_CLIENTS_E1 18
270#define ETH_MAX_RX_CLIENTS_E1H 25 434#define ETH_MAX_RX_CLIENTS_E1H 26
271 435
272/* Maximal aggregation queues supported */ 436/* Maximal aggregation queues supported */
273#define ETH_MAX_AGGREGATION_QUEUES_E1 32 437#define ETH_MAX_AGGREGATION_QUEUES_E1 32
@@ -276,6 +440,9 @@
276/* ETH RSS modes */ 440/* ETH RSS modes */
277#define ETH_RSS_MODE_DISABLED 0 441#define ETH_RSS_MODE_DISABLED 0
278#define ETH_RSS_MODE_REGULAR 1 442#define ETH_RSS_MODE_REGULAR 1
443#define ETH_RSS_MODE_VLAN_PRI 2
444#define ETH_RSS_MODE_E1HOV_PRI 3
445#define ETH_RSS_MODE_IP_DSCP 4
279 446
280 447
281/** 448/**
@@ -332,12 +499,14 @@
332#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3 499#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
333#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4 500#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
334#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5 501#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
502#define HC_INDEX_DEF_C_ETH_FCOE_CQ_CONS 6
335 503
336#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0 504#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
337#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1 505#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
338#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2 506#define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
339#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3 507#define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
340 508#define HC_INDEX_DEF_U_ETH_FCOE_RX_CQ_CONS 4
509#define HC_INDEX_DEF_U_ETH_FCOE_RX_BD_CONS 5
341 510
342/* used by the driver to get the SB offset */ 511/* used by the driver to get the SB offset */
343#define USTORM_ID 0 512#define USTORM_ID 0
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 07:28:54 -0500