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-rw-r--r--drivers/net/bnx2x/bnx2x_reg.h181
1 files changed, 171 insertions, 10 deletions
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index f8436e0c1316..65f3b1260766 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -54,16 +54,20 @@
54/* [RW 10] The number of free blocks below which the full signal to class 0 54/* [RW 10] The number of free blocks below which the full signal to class 0
55 * is asserted */ 55 * is asserted */
56#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0 56#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
57/* [RW 10] The number of free blocks above which the full signal to class 0 57#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
58/* [RW 11] The number of free blocks above which the full signal to class 0
58 * is de-asserted */ 59 * is de-asserted */
59#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4 60#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
60/* [RW 10] The number of free blocks below which the full signal to class 1 61#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
62/* [RW 11] The number of free blocks below which the full signal to class 1
61 * is asserted */ 63 * is asserted */
62#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8 64#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
63/* [RW 10] The number of free blocks above which the full signal to class 1 65#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
66/* [RW 11] The number of free blocks above which the full signal to class 1
64 * is de-asserted */ 67 * is de-asserted */
65#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc 68#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
66/* [RW 10] The number of free blocks below which the full signal to the LB 69#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
70/* [RW 11] The number of free blocks below which the full signal to the LB
67 * port is asserted */ 71 * port is asserted */
68#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0 72#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
69/* [RW 10] The number of free blocks above which the full signal to the LB 73/* [RW 10] The number of free blocks above which the full signal to the LB
@@ -75,15 +79,49 @@
75/* [RW 10] The number of free blocks below which the High_llfc signal to 79/* [RW 10] The number of free blocks below which the High_llfc signal to
76 interface #n is asserted. */ 80 interface #n is asserted. */
77#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c 81#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
78/* [RW 23] LL RAM data. */ 82/* [RW 11] The number of blocks guarantied for the LB port */
79#define BRB1_REG_LL_RAM 0x61000 83#define BRB1_REG_LB_GUARANTIED 0x601ec
84/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
85 * before signaling XON. */
86#define BRB1_REG_LB_GUARANTIED_HYST 0x60264
87/* [RW 24] LL RAM data. */
88#define BRB1_REG_LL_RAM 0x61000
80/* [RW 10] The number of free blocks above which the Low_llfc signal to 89/* [RW 10] The number of free blocks above which the Low_llfc signal to
81 interface #n is de-asserted. */ 90 interface #n is de-asserted. */
82#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c 91#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
83/* [RW 10] The number of free blocks below which the Low_llfc signal to 92/* [RW 10] The number of free blocks below which the Low_llfc signal to
84 interface #n is asserted. */ 93 interface #n is asserted. */
85#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c 94#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
86/* [RW 10] The number of blocks guarantied for the MAC port */ 95/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
96 * register is applicable only when per_class_guaranty_mode is set. */
97#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
98/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
99 * 1 before signaling XON. The register is applicable only when
100 * per_class_guaranty_mode is set. */
101#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
102/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
103 * register is applicable only when per_class_guaranty_mode is set. */
104#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
105/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
106 * before signaling XON. The register is applicable only when
107 * per_class_guaranty_mode is set. */
108#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
109/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
110 * is applicable only when per_class_guaranty_mode is set. */
111#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
112/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
113 * 1 before signaling XON. The register is applicable only when
114 * per_class_guaranty_mode is set. */
115#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
116/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
117 * register is applicable only when per_class_guaranty_mode is set. */
118#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
119/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
120 * 1 before signaling XON. The register is applicable only when
121 * per_class_guaranty_mode is set. */
122#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
123/* [RW 11] The number of blocks guarantied for the MAC port. The register is
124 * applicable only when per_class_guaranty_mode is reset. */
87#define BRB1_REG_MAC_GUARANTIED_0 0x601e8 125#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
88#define BRB1_REG_MAC_GUARANTIED_1 0x60240 126#define BRB1_REG_MAC_GUARANTIED_1 0x60240
89/* [R 24] The number of full blocks. */ 127/* [R 24] The number of full blocks. */
@@ -100,15 +138,19 @@
100/* [RW 10] The number of free blocks below which the pause signal to class 0 138/* [RW 10] The number of free blocks below which the pause signal to class 0
101 * is asserted */ 139 * is asserted */
102#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0 140#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
103/* [RW 10] The number of free blocks above which the pause signal to class 0 141#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
142/* [RW 11] The number of free blocks above which the pause signal to class 0
104 * is de-asserted */ 143 * is de-asserted */
105#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4 144#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
106/* [RW 10] The number of free blocks below which the pause signal to class 1 145#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
146/* [RW 11] The number of free blocks below which the pause signal to class 1
107 * is asserted */ 147 * is asserted */
108#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8 148#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
109/* [RW 10] The number of free blocks above which the pause signal to class 1 149#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
150/* [RW 11] The number of free blocks above which the pause signal to class 1
110 * is de-asserted */ 151 * is de-asserted */
111#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc 152#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
153#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
112/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 154/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
113#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 155#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
114#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 156#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
@@ -1655,12 +1697,31 @@
1655 * is compared to the value on ctrl_md_devad. Drives output 1697 * is compared to the value on ctrl_md_devad. Drives output
1656 * misc_xgxs0_phy_addr. Global register. */ 1698 * misc_xgxs0_phy_addr. Global register. */
1657#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc 1699#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1700/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1701 side. This should be less than or equal to phy_port_mode; if some of the
1702 ports are not used. This enables reduction of frequency on the core side.
1703 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1704 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1705 input for the XMAC_MP core; and should be changed only while reset is
1706 held low. Reset on Hard reset. */
1707#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1708/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1709 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1710 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1711 XMAC_MP core; and should be changed only while reset is held low. Reset
1712 on Hard reset. */
1713#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
1658/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0. 1714/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1659 * Reads from this register will clear bits 31:0. */ 1715 * Reads from this register will clear bits 31:0. */
1660#define MSTAT_REG_RX_STAT_GR64_LO 0x200 1716#define MSTAT_REG_RX_STAT_GR64_LO 0x200
1661/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits 1717/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1662 * 31:0. Reads from this register will clear bits 31:0. */ 1718 * 31:0. Reads from this register will clear bits 31:0. */
1663#define MSTAT_REG_TX_STAT_GTXPOK_LO 0 1719#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1720#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1721#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1722#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1723#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1724#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1664#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0) 1725#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1665#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0) 1726#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1666#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) 1727#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
@@ -1903,6 +1964,12 @@
1903#define NIG_REG_P0_HWPFC_ENABLE 0x18078 1964#define NIG_REG_P0_HWPFC_ENABLE 0x18078
1904#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480 1965#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
1905#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440 1966#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
1967/* [RW 1] Input enable for RX MAC interface. */
1968#define NIG_REG_P0_MAC_IN_EN 0x185ac
1969/* [RW 1] Output enable for TX MAC interface */
1970#define NIG_REG_P0_MAC_OUT_EN 0x185b0
1971/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
1972#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
1906/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 1973/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1907 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 1974 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1908 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 1975 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
@@ -1939,6 +2006,7 @@
1939 * than one bit may be set; allowing multiple priorities to be mapped to one 2006 * than one bit may be set; allowing multiple priorities to be mapped to one
1940 * COS. */ 2007 * COS. */
1941#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc 2008#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
2009/* [R 1] RX FIFO for receiving data from MAC is empty. */
1942/* [RW 15] Specify which of the credit registers the client is to be mapped 2010/* [RW 15] Specify which of the credit registers the client is to be mapped
1943 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For 2011 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
1944 * clients that are not subject to WFQ credit blocking - their 2012 * clients that are not subject to WFQ credit blocking - their
@@ -1981,6 +2049,11 @@
1981#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c 2049#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
1982#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0 2050#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
1983#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460 2051#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
2052#define NIG_REG_P1_MAC_IN_EN 0x185c0
2053/* [RW 1] Output enable for TX MAC interface */
2054#define NIG_REG_P1_MAC_OUT_EN 0x185c4
2055/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2056#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
1984/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2057/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1985 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2058 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1986 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2059 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
@@ -2002,6 +2075,52 @@
2002 * than one bit may be set; allowing multiple priorities to be mapped to one 2075 * than one bit may be set; allowing multiple priorities to be mapped to one
2003 * COS. */ 2076 * COS. */
2004#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8 2077#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
2078/* [R 1] RX FIFO for receiving data from MAC is empty. */
2079#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2080/* [R 1] TLLH FIFO is empty. */
2081#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2082/* [RW 32] Specify which of the credit registers the client is to be mapped
2083 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2084 * for client 0; bits [35:32] are for client 8. For clients that are not
2085 * subject to WFQ credit blocking - their specifications here are not used.
2086 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2087 * input clients to ETS arbiter. The reset default is set for management and
2088 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2089 * use credit registers 0-5 respectively (0x543210876). Note that credit
2090 * registers can not be shared between clients. Note also that there are
2091 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2092 * credit registers 0-5 are valid. This register should be configured
2093 * appropriately before enabling WFQ. */
2094#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2095/* [RW 4] Specify which of the credit registers the client is to be mapped
2096 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2097 * for client 0; bits [35:32] are for client 8. For clients that are not
2098 * subject to WFQ credit blocking - their specifications here are not used.
2099 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2100 * input clients to ETS arbiter. The reset default is set for management and
2101 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2102 * use credit registers 0-5 respectively (0x543210876). Note that credit
2103 * registers can not be shared between clients. Note also that there are
2104 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2105 * credit registers 0-5 are valid. This register should be configured
2106 * appropriately before enabling WFQ. */
2107#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2108/* [RW 9] Specify whether the client competes directly in the strict
2109 * priority arbiter. The bits are mapped according to client ID (client IDs
2110 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2111 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2112 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2113 * Default value is set to enable strict priorities for all clients. */
2114#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2115/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2116 * bits are mapped according to client ID (client IDs are defined in
2117 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2118 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2119 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2120 * 0 for not using WFQ credit blocking. */
2121#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
2122/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2123 * reach. */
2005/* [RW 1] Pause enable for port0. This register may get 1 only when 2124/* [RW 1] Pause enable for port0. This register may get 1 only when
2006 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same 2125 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2007 port */ 2126 port */
@@ -4427,6 +4546,17 @@
4427 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - 4546 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4428 header pointer. */ 4547 header pointer. */
4429#define UCM_REG_XX_TABLE 0xe0300 4548#define UCM_REG_XX_TABLE 0xe0300
4549#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
4550#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
4551#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
4552#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
4553#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
4554#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
4555#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
4556#define UMAC_REG_COMMAND_CONFIG 0x8
4557/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
4558 * logic to check frames. */
4559#define UMAC_REG_MAXFR 0x14
4430/* [RW 8] The event id for aggregated interrupt 0 */ 4560/* [RW 8] The event id for aggregated interrupt 0 */
4431#define USDM_REG_AGG_INT_EVENT_0 0xc4038 4561#define USDM_REG_AGG_INT_EVENT_0 0xc4038
4432#define USDM_REG_AGG_INT_EVENT_1 0xc403c 4562#define USDM_REG_AGG_INT_EVENT_1 0xc403c
@@ -4939,6 +5069,28 @@
4939#define XCM_REG_XX_MSG_NUM 0x20428 5069#define XCM_REG_XX_MSG_NUM 0x20428
4940/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 5070/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4941#define XCM_REG_XX_OVFL_EVNT_ID 0x20058 5071#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
5072#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5073#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
5074#define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3)
5075#define XMAC_CTRL_REG_RX_EN (0x1<<1)
5076#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5077#define XMAC_CTRL_REG_TX_EN (0x1<<0)
5078#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5079#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5080#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5081#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5082#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5083#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5084#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5085#define XMAC_REG_CTRL 0
5086#define XMAC_REG_PAUSE_CTRL 0x68
5087#define XMAC_REG_PFC_CTRL 0x70
5088#define XMAC_REG_PFC_CTRL_HI 0x74
5089#define XMAC_REG_RX_LSS_STATUS 0x58
5090/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5091 * CRC in strip mode */
5092#define XMAC_REG_RX_MAX_SIZE 0x40
5093#define XMAC_REG_TX_CTRL 0x20
4942/* [RW 16] Indirect access to the XX table of the XX protection mechanism. 5094/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4943 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 5095 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4944 header pointer. */ 5096 header pointer. */
@@ -5011,6 +5163,8 @@
5011#define XSDM_REG_NUM_OF_Q8_CMD 0x166264 5163#define XSDM_REG_NUM_OF_Q8_CMD 0x166264
5012/* [ST 32] The number of commands received in queue 9 */ 5164/* [ST 32] The number of commands received in queue 9 */
5013#define XSDM_REG_NUM_OF_Q9_CMD 0x166268 5165#define XSDM_REG_NUM_OF_Q9_CMD 0x166268
5166/* [RW 13] The start address in the internal RAM for queue counters */
5167#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
5014/* [W 17] Generate an operation after completion; bit-16 is 5168/* [W 17] Generate an operation after completion; bit-16 is
5015 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and 5169 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5016 * bits 4:0 are the T124Param[4:0] */ 5170 * bits 4:0 are the T124Param[4:0] */
@@ -5312,6 +5466,9 @@
5312#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13) 5466#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
5313#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 5467#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5314#define MISC_REGISTERS_RESET_REG_2_SET 0x594 5468#define MISC_REGISTERS_RESET_REG_2_SET 0x594
5469#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
5470#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
5471#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
5315#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 5472#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5316#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 5473#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5317#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 5474#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
@@ -5503,9 +5660,13 @@
5503#define GRCBASE_HC 0x108000 5660#define GRCBASE_HC 0x108000
5504#define GRCBASE_PXP2 0x120000 5661#define GRCBASE_PXP2 0x120000
5505#define GRCBASE_PBF 0x140000 5662#define GRCBASE_PBF 0x140000
5663#define GRCBASE_UMAC0 0x160000
5664#define GRCBASE_UMAC1 0x160400
5506#define GRCBASE_XPB 0x161000 5665#define GRCBASE_XPB 0x161000
5507#define GRCBASE_MSTAT0 0x162000 5666#define GRCBASE_MSTAT0 0x162000
5508#define GRCBASE_MSTAT1 0x162800 5667#define GRCBASE_MSTAT1 0x162800
5668#define GRCBASE_XMAC0 0x163000
5669#define GRCBASE_XMAC1 0x163800
5509#define GRCBASE_TIMERS 0x164000 5670#define GRCBASE_TIMERS 0x164000
5510#define GRCBASE_XSDM 0x166000 5671#define GRCBASE_XSDM 0x166000
5511#define GRCBASE_QM 0x168000 5672#define GRCBASE_QM 0x168000
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 09:11:18 -0400