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path: root/drivers/net/bnx2x/bnx2x_main.c
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Diffstat (limited to 'drivers/net/bnx2x/bnx2x_main.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_main.c7265
1 files changed, 4761 insertions, 2504 deletions
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index f8c3f08e4ce7..74be989f51c5 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -1,6 +1,6 @@
1/* bnx2x_main.c: Broadcom Everest network driver. 1/* bnx2x_main.c: Broadcom Everest network driver.
2 * 2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation 3 * Copyright (c) 2007-2011 Broadcom Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
@@ -23,7 +23,6 @@
23#include <linux/errno.h> 23#include <linux/errno.h>
24#include <linux/ioport.h> 24#include <linux/ioport.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/vmalloc.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/pci.h> 27#include <linux/pci.h>
29#include <linux/init.h> 28#include <linux/init.h>
@@ -50,13 +49,14 @@
50#include <linux/zlib.h> 49#include <linux/zlib.h>
51#include <linux/io.h> 50#include <linux/io.h>
52#include <linux/stringify.h> 51#include <linux/stringify.h>
52#include <linux/vmalloc.h>
53 53
54#define BNX2X_MAIN 54#define BNX2X_MAIN
55#include "bnx2x.h" 55#include "bnx2x.h"
56#include "bnx2x_init.h" 56#include "bnx2x_init.h"
57#include "bnx2x_init_ops.h" 57#include "bnx2x_init_ops.h"
58#include "bnx2x_cmn.h" 58#include "bnx2x_cmn.h"
59 59#include "bnx2x_dcb.h"
60 60
61#include <linux/firmware.h> 61#include <linux/firmware.h>
62#include "bnx2x_fw_file_hdr.h" 62#include "bnx2x_fw_file_hdr.h"
@@ -66,8 +66,9 @@
66 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 66 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
67 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 67 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
68 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 68 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
69#define FW_FILE_NAME_E1 "bnx2x-e1-" FW_FILE_VERSION ".fw" 69#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
70#define FW_FILE_NAME_E1H "bnx2x-e1h-" FW_FILE_VERSION ".fw" 70#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
71#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
71 72
72/* Time in jiffies before concluding the transmitter is hung */ 73/* Time in jiffies before concluding the transmitter is hung */
73#define TX_TIMEOUT (5*HZ) 74#define TX_TIMEOUT (5*HZ)
@@ -77,18 +78,20 @@ static char version[] __devinitdata =
77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 78 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
78 79
79MODULE_AUTHOR("Eliezer Tamir"); 80MODULE_AUTHOR("Eliezer Tamir");
80MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver"); 81MODULE_DESCRIPTION("Broadcom NetXtreme II "
82 "BCM57710/57711/57711E/57712/57712E Driver");
81MODULE_LICENSE("GPL"); 83MODULE_LICENSE("GPL");
82MODULE_VERSION(DRV_MODULE_VERSION); 84MODULE_VERSION(DRV_MODULE_VERSION);
83MODULE_FIRMWARE(FW_FILE_NAME_E1); 85MODULE_FIRMWARE(FW_FILE_NAME_E1);
84MODULE_FIRMWARE(FW_FILE_NAME_E1H); 86MODULE_FIRMWARE(FW_FILE_NAME_E1H);
87MODULE_FIRMWARE(FW_FILE_NAME_E2);
85 88
86static int multi_mode = 1; 89static int multi_mode = 1;
87module_param(multi_mode, int, 0); 90module_param(multi_mode, int, 0);
88MODULE_PARM_DESC(multi_mode, " Multi queue mode " 91MODULE_PARM_DESC(multi_mode, " Multi queue mode "
89 "(0 Disable; 1 Enable (default))"); 92 "(0 Disable; 1 Enable (default))");
90 93
91static int num_queues; 94int num_queues;
92module_param(num_queues, int, 0); 95module_param(num_queues, int, 0);
93MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1" 96MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
94 " (default is as a number of CPUs)"); 97 " (default is as a number of CPUs)");
@@ -120,10 +123,16 @@ MODULE_PARM_DESC(debug, " Default debug msglevel");
120 123
121static struct workqueue_struct *bnx2x_wq; 124static struct workqueue_struct *bnx2x_wq;
122 125
126#ifdef BCM_CNIC
127static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
128#endif
129
123enum bnx2x_board_type { 130enum bnx2x_board_type {
124 BCM57710 = 0, 131 BCM57710 = 0,
125 BCM57711 = 1, 132 BCM57711 = 1,
126 BCM57711E = 2, 133 BCM57711E = 2,
134 BCM57712 = 3,
135 BCM57712E = 4
127}; 136};
128 137
129/* indexed by board_type, above */ 138/* indexed by board_type, above */
@@ -132,14 +141,17 @@ static struct {
132} board_info[] __devinitdata = { 141} board_info[] __devinitdata = {
133 { "Broadcom NetXtreme II BCM57710 XGb" }, 142 { "Broadcom NetXtreme II BCM57710 XGb" },
134 { "Broadcom NetXtreme II BCM57711 XGb" }, 143 { "Broadcom NetXtreme II BCM57711 XGb" },
135 { "Broadcom NetXtreme II BCM57711E XGb" } 144 { "Broadcom NetXtreme II BCM57711E XGb" },
145 { "Broadcom NetXtreme II BCM57712 XGb" },
146 { "Broadcom NetXtreme II BCM57712E XGb" }
136}; 147};
137 148
138
139static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = { 149static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
140 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 150 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
141 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 151 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
142 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 152 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
153 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
154 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
143 { 0 } 155 { 0 }
144}; 156};
145 157
@@ -149,10 +161,248 @@ MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
149* General service functions 161* General service functions
150****************************************************************************/ 162****************************************************************************/
151 163
164static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
165 u32 addr, dma_addr_t mapping)
166{
167 REG_WR(bp, addr, U64_LO(mapping));
168 REG_WR(bp, addr + 4, U64_HI(mapping));
169}
170
171static inline void __storm_memset_fill(struct bnx2x *bp,
172 u32 addr, size_t size, u32 val)
173{
174 int i;
175 for (i = 0; i < size/4; i++)
176 REG_WR(bp, addr + (i * 4), val);
177}
178
179static inline void storm_memset_ustats_zero(struct bnx2x *bp,
180 u8 port, u16 stat_id)
181{
182 size_t size = sizeof(struct ustorm_per_client_stats);
183
184 u32 addr = BAR_USTRORM_INTMEM +
185 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
186
187 __storm_memset_fill(bp, addr, size, 0);
188}
189
190static inline void storm_memset_tstats_zero(struct bnx2x *bp,
191 u8 port, u16 stat_id)
192{
193 size_t size = sizeof(struct tstorm_per_client_stats);
194
195 u32 addr = BAR_TSTRORM_INTMEM +
196 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
197
198 __storm_memset_fill(bp, addr, size, 0);
199}
200
201static inline void storm_memset_xstats_zero(struct bnx2x *bp,
202 u8 port, u16 stat_id)
203{
204 size_t size = sizeof(struct xstorm_per_client_stats);
205
206 u32 addr = BAR_XSTRORM_INTMEM +
207 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
208
209 __storm_memset_fill(bp, addr, size, 0);
210}
211
212
213static inline void storm_memset_spq_addr(struct bnx2x *bp,
214 dma_addr_t mapping, u16 abs_fid)
215{
216 u32 addr = XSEM_REG_FAST_MEMORY +
217 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
218
219 __storm_memset_dma_mapping(bp, addr, mapping);
220}
221
222static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
223{
224 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
225}
226
227static inline void storm_memset_func_cfg(struct bnx2x *bp,
228 struct tstorm_eth_function_common_config *tcfg,
229 u16 abs_fid)
230{
231 size_t size = sizeof(struct tstorm_eth_function_common_config);
232
233 u32 addr = BAR_TSTRORM_INTMEM +
234 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
235
236 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
237}
238
239static inline void storm_memset_xstats_flags(struct bnx2x *bp,
240 struct stats_indication_flags *flags,
241 u16 abs_fid)
242{
243 size_t size = sizeof(struct stats_indication_flags);
244
245 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
246
247 __storm_memset_struct(bp, addr, size, (u32 *)flags);
248}
249
250static inline void storm_memset_tstats_flags(struct bnx2x *bp,
251 struct stats_indication_flags *flags,
252 u16 abs_fid)
253{
254 size_t size = sizeof(struct stats_indication_flags);
255
256 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
257
258 __storm_memset_struct(bp, addr, size, (u32 *)flags);
259}
260
261static inline void storm_memset_ustats_flags(struct bnx2x *bp,
262 struct stats_indication_flags *flags,
263 u16 abs_fid)
264{
265 size_t size = sizeof(struct stats_indication_flags);
266
267 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
268
269 __storm_memset_struct(bp, addr, size, (u32 *)flags);
270}
271
272static inline void storm_memset_cstats_flags(struct bnx2x *bp,
273 struct stats_indication_flags *flags,
274 u16 abs_fid)
275{
276 size_t size = sizeof(struct stats_indication_flags);
277
278 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
279
280 __storm_memset_struct(bp, addr, size, (u32 *)flags);
281}
282
283static inline void storm_memset_xstats_addr(struct bnx2x *bp,
284 dma_addr_t mapping, u16 abs_fid)
285{
286 u32 addr = BAR_XSTRORM_INTMEM +
287 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
288
289 __storm_memset_dma_mapping(bp, addr, mapping);
290}
291
292static inline void storm_memset_tstats_addr(struct bnx2x *bp,
293 dma_addr_t mapping, u16 abs_fid)
294{
295 u32 addr = BAR_TSTRORM_INTMEM +
296 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
297
298 __storm_memset_dma_mapping(bp, addr, mapping);
299}
300
301static inline void storm_memset_ustats_addr(struct bnx2x *bp,
302 dma_addr_t mapping, u16 abs_fid)
303{
304 u32 addr = BAR_USTRORM_INTMEM +
305 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
306
307 __storm_memset_dma_mapping(bp, addr, mapping);
308}
309
310static inline void storm_memset_cstats_addr(struct bnx2x *bp,
311 dma_addr_t mapping, u16 abs_fid)
312{
313 u32 addr = BAR_CSTRORM_INTMEM +
314 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
315
316 __storm_memset_dma_mapping(bp, addr, mapping);
317}
318
319static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
320 u16 pf_id)
321{
322 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
323 pf_id);
324 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
325 pf_id);
326 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
327 pf_id);
328 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
329 pf_id);
330}
331
332static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
333 u8 enable)
334{
335 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
336 enable);
337 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
338 enable);
339 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
340 enable);
341 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
342 enable);
343}
344
345static inline void storm_memset_eq_data(struct bnx2x *bp,
346 struct event_ring_data *eq_data,
347 u16 pfid)
348{
349 size_t size = sizeof(struct event_ring_data);
350
351 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
352
353 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
354}
355
356static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
357 u16 pfid)
358{
359 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
360 REG_WR16(bp, addr, eq_prod);
361}
362
363static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
364 u16 fw_sb_id, u8 sb_index,
365 u8 ticks)
366{
367
368 int index_offset = CHIP_IS_E2(bp) ?
369 offsetof(struct hc_status_block_data_e2, index_data) :
370 offsetof(struct hc_status_block_data_e1x, index_data);
371 u32 addr = BAR_CSTRORM_INTMEM +
372 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
373 index_offset +
374 sizeof(struct hc_index_data)*sb_index +
375 offsetof(struct hc_index_data, timeout);
376 REG_WR8(bp, addr, ticks);
377 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
378 port, fw_sb_id, sb_index, ticks);
379}
380static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
381 u16 fw_sb_id, u8 sb_index,
382 u8 disable)
383{
384 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
385 int index_offset = CHIP_IS_E2(bp) ?
386 offsetof(struct hc_status_block_data_e2, index_data) :
387 offsetof(struct hc_status_block_data_e1x, index_data);
388 u32 addr = BAR_CSTRORM_INTMEM +
389 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
390 index_offset +
391 sizeof(struct hc_index_data)*sb_index +
392 offsetof(struct hc_index_data, flags);
393 u16 flags = REG_RD16(bp, addr);
394 /* clear and set */
395 flags &= ~HC_INDEX_DATA_HC_ENABLED;
396 flags |= enable_flag;
397 REG_WR16(bp, addr, flags);
398 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
399 port, fw_sb_id, sb_index, disable);
400}
401
152/* used only at init 402/* used only at init
153 * locking is done by mcp 403 * locking is done by mcp
154 */ 404 */
155void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 405static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
156{ 406{
157 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 407 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
158 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 408 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
@@ -172,6 +422,76 @@ static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
172 return val; 422 return val;
173} 423}
174 424
425#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
426#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
427#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
428#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
429#define DMAE_DP_DST_NONE "dst_addr [none]"
430
431static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
432 int msglvl)
433{
434 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
435
436 switch (dmae->opcode & DMAE_COMMAND_DST) {
437 case DMAE_CMD_DST_PCI:
438 if (src_type == DMAE_CMD_SRC_PCI)
439 DP(msglvl, "DMAE: opcode 0x%08x\n"
440 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
441 "comp_addr [%x:%08x], comp_val 0x%08x\n",
442 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
443 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
444 dmae->comp_addr_hi, dmae->comp_addr_lo,
445 dmae->comp_val);
446 else
447 DP(msglvl, "DMAE: opcode 0x%08x\n"
448 "src [%08x], len [%d*4], dst [%x:%08x]\n"
449 "comp_addr [%x:%08x], comp_val 0x%08x\n",
450 dmae->opcode, dmae->src_addr_lo >> 2,
451 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
452 dmae->comp_addr_hi, dmae->comp_addr_lo,
453 dmae->comp_val);
454 break;
455 case DMAE_CMD_DST_GRC:
456 if (src_type == DMAE_CMD_SRC_PCI)
457 DP(msglvl, "DMAE: opcode 0x%08x\n"
458 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
459 "comp_addr [%x:%08x], comp_val 0x%08x\n",
460 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
461 dmae->len, dmae->dst_addr_lo >> 2,
462 dmae->comp_addr_hi, dmae->comp_addr_lo,
463 dmae->comp_val);
464 else
465 DP(msglvl, "DMAE: opcode 0x%08x\n"
466 "src [%08x], len [%d*4], dst [%08x]\n"
467 "comp_addr [%x:%08x], comp_val 0x%08x\n",
468 dmae->opcode, dmae->src_addr_lo >> 2,
469 dmae->len, dmae->dst_addr_lo >> 2,
470 dmae->comp_addr_hi, dmae->comp_addr_lo,
471 dmae->comp_val);
472 break;
473 default:
474 if (src_type == DMAE_CMD_SRC_PCI)
475 DP(msglvl, "DMAE: opcode 0x%08x\n"
476 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
477 "dst_addr [none]\n"
478 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
479 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
480 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
481 dmae->comp_val);
482 else
483 DP(msglvl, "DMAE: opcode 0x%08x\n"
484 DP_LEVEL "src_addr [%08x] len [%d * 4] "
485 "dst_addr [none]\n"
486 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
487 dmae->opcode, dmae->src_addr_lo >> 2,
488 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
489 dmae->comp_val);
490 break;
491 }
492
493}
494
175const u32 dmae_reg_go_c[] = { 495const u32 dmae_reg_go_c[] = {
176 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 496 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
177 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 497 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
@@ -195,85 +515,139 @@ void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
195 REG_WR(bp, dmae_reg_go_c[idx], 1); 515 REG_WR(bp, dmae_reg_go_c[idx], 1);
196} 516}
197 517
198void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 518u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
199 u32 len32)
200{ 519{
201 struct dmae_command dmae; 520 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
202 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 521 DMAE_CMD_C_ENABLE);
203 int cnt = 200; 522}
204 523
205 if (!bp->dmae_ready) { 524u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
206 u32 *data = bnx2x_sp(bp, wb_data[0]); 525{
526 return opcode & ~DMAE_CMD_SRC_RESET;
527}
207 528
208 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)" 529u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
209 " using indirect\n", dst_addr, len32); 530 bool with_comp, u8 comp_type)
210 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 531{
211 return; 532 u32 opcode = 0;
212 }
213 533
214 memset(&dmae, 0, sizeof(struct dmae_command)); 534 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
535 (dst_type << DMAE_COMMAND_DST_SHIFT));
536
537 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
538
539 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
540 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
541 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
542 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
215 543
216 dmae.opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
217 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
218 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
219#ifdef __BIG_ENDIAN 544#ifdef __BIG_ENDIAN
220 DMAE_CMD_ENDIANITY_B_DW_SWAP | 545 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
221#else 546#else
222 DMAE_CMD_ENDIANITY_DW_SWAP | 547 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
223#endif 548#endif
224 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) | 549 if (with_comp)
225 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT)); 550 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
226 dmae.src_addr_lo = U64_LO(dma_addr); 551 return opcode;
227 dmae.src_addr_hi = U64_HI(dma_addr); 552}
228 dmae.dst_addr_lo = dst_addr >> 2; 553
229 dmae.dst_addr_hi = 0; 554static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
230 dmae.len = len32; 555 struct dmae_command *dmae,
231 dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 556 u8 src_type, u8 dst_type)
232 dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 557{
233 dmae.comp_val = DMAE_COMP_VAL; 558 memset(dmae, 0, sizeof(struct dmae_command));
234 559
235 DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n" 560 /* set the opcode */
236 DP_LEVEL "src_addr [%x:%08x] len [%d *4] " 561 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
237 "dst_addr [%x:%08x (%08x)]\n" 562 true, DMAE_COMP_PCI);
238 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", 563
239 dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo, 564 /* fill in the completion parameters */
240 dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, dst_addr, 565 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
241 dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val); 566 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
242 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n", 567 dmae->comp_val = DMAE_COMP_VAL;
568}
569
570/* issue a dmae command over the init-channel and wailt for completion */
571static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
572 struct dmae_command *dmae)
573{
574 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
575 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
576 int rc = 0;
577
578 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
243 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 579 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
244 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 580 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
245 581
246 mutex_lock(&bp->dmae_mutex); 582 /* lock the dmae channel */
583 spin_lock_bh(&bp->dmae_lock);
247 584
585 /* reset completion */
248 *wb_comp = 0; 586 *wb_comp = 0;
249 587
250 bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp)); 588 /* post the command on the channel used for initializations */
589 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
251 590
591 /* wait for completion */
252 udelay(5); 592 udelay(5);
253 593 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
254 while (*wb_comp != DMAE_COMP_VAL) {
255 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 594 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
256 595
257 if (!cnt) { 596 if (!cnt) {
258 BNX2X_ERR("DMAE timeout!\n"); 597 BNX2X_ERR("DMAE timeout!\n");
259 break; 598 rc = DMAE_TIMEOUT;
599 goto unlock;
260 } 600 }
261 cnt--; 601 cnt--;
262 /* adjust delay for emulation/FPGA */ 602 udelay(50);
263 if (CHIP_REV_IS_SLOW(bp)) 603 }
264 msleep(100); 604 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
265 else 605 BNX2X_ERR("DMAE PCI error!\n");
266 udelay(5); 606 rc = DMAE_PCI_ERROR;
267 } 607 }
268 608
269 mutex_unlock(&bp->dmae_mutex); 609 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
610 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
611 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
612
613unlock:
614 spin_unlock_bh(&bp->dmae_lock);
615 return rc;
616}
617
618void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
619 u32 len32)
620{
621 struct dmae_command dmae;
622
623 if (!bp->dmae_ready) {
624 u32 *data = bnx2x_sp(bp, wb_data[0]);
625
626 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
627 " using indirect\n", dst_addr, len32);
628 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
629 return;
630 }
631
632 /* set opcode and fixed command fields */
633 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
634
635 /* fill in addresses and len */
636 dmae.src_addr_lo = U64_LO(dma_addr);
637 dmae.src_addr_hi = U64_HI(dma_addr);
638 dmae.dst_addr_lo = dst_addr >> 2;
639 dmae.dst_addr_hi = 0;
640 dmae.len = len32;
641
642 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
643
644 /* issue the command and wait for completion */
645 bnx2x_issue_dmae_with_comp(bp, &dmae);
270} 646}
271 647
272void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 648void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
273{ 649{
274 struct dmae_command dmae; 650 struct dmae_command dmae;
275 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
276 int cnt = 200;
277 651
278 if (!bp->dmae_ready) { 652 if (!bp->dmae_ready) {
279 u32 *data = bnx2x_sp(bp, wb_data[0]); 653 u32 *data = bnx2x_sp(bp, wb_data[0]);
@@ -286,66 +660,24 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
286 return; 660 return;
287 } 661 }
288 662
289 memset(&dmae, 0, sizeof(struct dmae_command)); 663 /* set opcode and fixed command fields */
664 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
290 665
291 dmae.opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI | 666 /* fill in addresses and len */
292 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
293 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
294#ifdef __BIG_ENDIAN
295 DMAE_CMD_ENDIANITY_B_DW_SWAP |
296#else
297 DMAE_CMD_ENDIANITY_DW_SWAP |
298#endif
299 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
300 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
301 dmae.src_addr_lo = src_addr >> 2; 667 dmae.src_addr_lo = src_addr >> 2;
302 dmae.src_addr_hi = 0; 668 dmae.src_addr_hi = 0;
303 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 669 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
304 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 670 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
305 dmae.len = len32; 671 dmae.len = len32;
306 dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
307 dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
308 dmae.comp_val = DMAE_COMP_VAL;
309
310 DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
311 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
312 "dst_addr [%x:%08x (%08x)]\n"
313 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
314 dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
315 dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, src_addr,
316 dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
317
318 mutex_lock(&bp->dmae_mutex);
319 672
320 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4); 673 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
321 *wb_comp = 0;
322
323 bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
324
325 udelay(5);
326
327 while (*wb_comp != DMAE_COMP_VAL) {
328
329 if (!cnt) {
330 BNX2X_ERR("DMAE timeout!\n");
331 break;
332 }
333 cnt--;
334 /* adjust delay for emulation/FPGA */
335 if (CHIP_REV_IS_SLOW(bp))
336 msleep(100);
337 else
338 udelay(5);
339 }
340 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
341 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
342 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
343 674
344 mutex_unlock(&bp->dmae_mutex); 675 /* issue the command and wait for completion */
676 bnx2x_issue_dmae_with_comp(bp, &dmae);
345} 677}
346 678
347void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 679static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
348 u32 addr, u32 len) 680 u32 addr, u32 len)
349{ 681{
350 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 682 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
351 int offset = 0; 683 int offset = 0;
@@ -508,19 +840,24 @@ static void bnx2x_fw_dump(struct bnx2x *bp)
508 u32 mark, offset; 840 u32 mark, offset;
509 __be32 data[9]; 841 __be32 data[9];
510 int word; 842 int word;
511 843 u32 trace_shmem_base;
512 if (BP_NOMCP(bp)) { 844 if (BP_NOMCP(bp)) {
513 BNX2X_ERR("NO MCP - can not dump\n"); 845 BNX2X_ERR("NO MCP - can not dump\n");
514 return; 846 return;
515 } 847 }
516 848
517 addr = bp->common.shmem_base - 0x0800 + 4; 849 if (BP_PATH(bp) == 0)
850 trace_shmem_base = bp->common.shmem_base;
851 else
852 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
853 addr = trace_shmem_base - 0x0800 + 4;
518 mark = REG_RD(bp, addr); 854 mark = REG_RD(bp, addr);
519 mark = MCP_REG_MCPR_SCRATCH + ((mark + 0x3) & ~0x3) - 0x08000000; 855 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
856 + ((mark + 0x3) & ~0x3) - 0x08000000;
520 pr_err("begin fw dump (mark 0x%x)\n", mark); 857 pr_err("begin fw dump (mark 0x%x)\n", mark);
521 858
522 pr_err(""); 859 pr_err("");
523 for (offset = mark; offset <= bp->common.shmem_base; offset += 0x8*4) { 860 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
524 for (word = 0; word < 8; word++) 861 for (word = 0; word < 8; word++)
525 data[word] = htonl(REG_RD(bp, offset + 4*word)); 862 data[word] = htonl(REG_RD(bp, offset + 4*word));
526 data[8] = 0x0; 863 data[8] = 0x0;
@@ -538,7 +875,12 @@ static void bnx2x_fw_dump(struct bnx2x *bp)
538void bnx2x_panic_dump(struct bnx2x *bp) 875void bnx2x_panic_dump(struct bnx2x *bp)
539{ 876{
540 int i; 877 int i;
541 u16 j, start, end; 878 u16 j;
879 struct hc_sp_status_block_data sp_sb_data;
880 int func = BP_FUNC(bp);
881#ifdef BNX2X_STOP_ON_ERROR
882 u16 start = 0, end = 0;
883#endif
542 884
543 bp->stats_state = STATS_STATE_DISABLED; 885 bp->stats_state = STATS_STATE_DISABLED;
544 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 886 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
@@ -547,47 +889,150 @@ void bnx2x_panic_dump(struct bnx2x *bp)
547 889
548 /* Indices */ 890 /* Indices */
549 /* Common */ 891 /* Common */
550 BNX2X_ERR("def_c_idx(0x%x) def_u_idx(0x%x) def_x_idx(0x%x)" 892 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
551 " def_t_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
552 " spq_prod_idx(0x%x)\n", 893 " spq_prod_idx(0x%x)\n",
553 bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx, 894 bp->def_idx, bp->def_att_idx,
554 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx); 895 bp->attn_state, bp->spq_prod_idx);
555 896 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
556 /* Rx */ 897 bp->def_status_blk->atten_status_block.attn_bits,
557 for_each_queue(bp, i) { 898 bp->def_status_blk->atten_status_block.attn_bits_ack,
899 bp->def_status_blk->atten_status_block.status_block_id,
900 bp->def_status_blk->atten_status_block.attn_bits_index);
901 BNX2X_ERR(" def (");
902 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
903 pr_cont("0x%x%s",
904 bp->def_status_blk->sp_sb.index_values[i],
905 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
906
907 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
908 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
909 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
910 i*sizeof(u32));
911
912 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
913 "pf_id(0x%x) vnic_id(0x%x) "
914 "vf_id(0x%x) vf_valid (0x%x)\n",
915 sp_sb_data.igu_sb_id,
916 sp_sb_data.igu_seg_id,
917 sp_sb_data.p_func.pf_id,
918 sp_sb_data.p_func.vnic_id,
919 sp_sb_data.p_func.vf_id,
920 sp_sb_data.p_func.vf_valid);
921
922
923 for_each_eth_queue(bp, i) {
558 struct bnx2x_fastpath *fp = &bp->fp[i]; 924 struct bnx2x_fastpath *fp = &bp->fp[i];
559 925 int loop;
926 struct hc_status_block_data_e2 sb_data_e2;
927 struct hc_status_block_data_e1x sb_data_e1x;
928 struct hc_status_block_sm *hc_sm_p =
929 CHIP_IS_E2(bp) ?
930 sb_data_e2.common.state_machine :
931 sb_data_e1x.common.state_machine;
932 struct hc_index_data *hc_index_p =
933 CHIP_IS_E2(bp) ?
934 sb_data_e2.index_data :
935 sb_data_e1x.index_data;
936 int data_size;
937 u32 *sb_data_p;
938
939 /* Rx */
560 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 940 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
561 " *rx_bd_cons_sb(0x%x) rx_comp_prod(0x%x)" 941 " rx_comp_prod(0x%x)"
562 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 942 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
563 i, fp->rx_bd_prod, fp->rx_bd_cons, 943 i, fp->rx_bd_prod, fp->rx_bd_cons,
564 le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod, 944 fp->rx_comp_prod,
565 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 945 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
566 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 946 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
567 " fp_u_idx(0x%x) *sb_u_idx(0x%x)\n", 947 " fp_hc_idx(0x%x)\n",
568 fp->rx_sge_prod, fp->last_max_sge, 948 fp->rx_sge_prod, fp->last_max_sge,
569 le16_to_cpu(fp->fp_u_idx), 949 le16_to_cpu(fp->fp_hc_idx));
570 fp->status_blk->u_status_block.status_block_index);
571 }
572
573 /* Tx */
574 for_each_queue(bp, i) {
575 struct bnx2x_fastpath *fp = &bp->fp[i];
576 950
951 /* Tx */
577 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 952 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
578 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)" 953 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
579 " *tx_cons_sb(0x%x)\n", 954 " *tx_cons_sb(0x%x)\n",
580 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod, 955 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
581 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb)); 956 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
582 BNX2X_ERR(" fp_c_idx(0x%x) *sb_c_idx(0x%x)" 957
583 " tx_db_prod(0x%x)\n", le16_to_cpu(fp->fp_c_idx), 958 loop = CHIP_IS_E2(bp) ?
584 fp->status_blk->c_status_block.status_block_index, 959 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
585 fp->tx_db.data.prod); 960
961 /* host sb data */
962
963#ifdef BCM_CNIC
964 if (IS_FCOE_FP(fp))
965 continue;
966#endif
967 BNX2X_ERR(" run indexes (");
968 for (j = 0; j < HC_SB_MAX_SM; j++)
969 pr_cont("0x%x%s",
970 fp->sb_running_index[j],
971 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
972
973 BNX2X_ERR(" indexes (");
974 for (j = 0; j < loop; j++)
975 pr_cont("0x%x%s",
976 fp->sb_index_values[j],
977 (j == loop - 1) ? ")" : " ");
978 /* fw sb data */
979 data_size = CHIP_IS_E2(bp) ?
980 sizeof(struct hc_status_block_data_e2) :
981 sizeof(struct hc_status_block_data_e1x);
982 data_size /= sizeof(u32);
983 sb_data_p = CHIP_IS_E2(bp) ?
984 (u32 *)&sb_data_e2 :
985 (u32 *)&sb_data_e1x;
986 /* copy sb data in here */
987 for (j = 0; j < data_size; j++)
988 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
989 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
990 j * sizeof(u32));
991
992 if (CHIP_IS_E2(bp)) {
993 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
994 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
995 sb_data_e2.common.p_func.pf_id,
996 sb_data_e2.common.p_func.vf_id,
997 sb_data_e2.common.p_func.vf_valid,
998 sb_data_e2.common.p_func.vnic_id,
999 sb_data_e2.common.same_igu_sb_1b);
1000 } else {
1001 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1002 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1003 sb_data_e1x.common.p_func.pf_id,
1004 sb_data_e1x.common.p_func.vf_id,
1005 sb_data_e1x.common.p_func.vf_valid,
1006 sb_data_e1x.common.p_func.vnic_id,
1007 sb_data_e1x.common.same_igu_sb_1b);
1008 }
1009
1010 /* SB_SMs data */
1011 for (j = 0; j < HC_SB_MAX_SM; j++) {
1012 pr_cont("SM[%d] __flags (0x%x) "
1013 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1014 "time_to_expire (0x%x) "
1015 "timer_value(0x%x)\n", j,
1016 hc_sm_p[j].__flags,
1017 hc_sm_p[j].igu_sb_id,
1018 hc_sm_p[j].igu_seg_id,
1019 hc_sm_p[j].time_to_expire,
1020 hc_sm_p[j].timer_value);
1021 }
1022
1023 /* Indecies data */
1024 for (j = 0; j < loop; j++) {
1025 pr_cont("INDEX[%d] flags (0x%x) "
1026 "timeout (0x%x)\n", j,
1027 hc_index_p[j].flags,
1028 hc_index_p[j].timeout);
1029 }
586 } 1030 }
587 1031
1032#ifdef BNX2X_STOP_ON_ERROR
588 /* Rings */ 1033 /* Rings */
589 /* Rx */ 1034 /* Rx */
590 for_each_queue(bp, i) { 1035 for_each_rx_queue(bp, i) {
591 struct bnx2x_fastpath *fp = &bp->fp[i]; 1036 struct bnx2x_fastpath *fp = &bp->fp[i];
592 1037
593 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 1038 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
@@ -621,7 +1066,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
621 } 1066 }
622 1067
623 /* Tx */ 1068 /* Tx */
624 for_each_queue(bp, i) { 1069 for_each_tx_queue(bp, i) {
625 struct bnx2x_fastpath *fp = &bp->fp[i]; 1070 struct bnx2x_fastpath *fp = &bp->fp[i];
626 1071
627 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10); 1072 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
@@ -642,13 +1087,13 @@ void bnx2x_panic_dump(struct bnx2x *bp)
642 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]); 1087 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
643 } 1088 }
644 } 1089 }
645 1090#endif
646 bnx2x_fw_dump(bp); 1091 bnx2x_fw_dump(bp);
647 bnx2x_mc_assert(bp); 1092 bnx2x_mc_assert(bp);
648 BNX2X_ERR("end crash dump -----------------\n"); 1093 BNX2X_ERR("end crash dump -----------------\n");
649} 1094}
650 1095
651void bnx2x_int_enable(struct bnx2x *bp) 1096static void bnx2x_hc_int_enable(struct bnx2x *bp)
652{ 1097{
653 int port = BP_PORT(bp); 1098 int port = BP_PORT(bp);
654 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1099 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
@@ -672,14 +1117,19 @@ void bnx2x_int_enable(struct bnx2x *bp)
672 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1117 HC_CONFIG_0_REG_INT_LINE_EN_0 |
673 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1118 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
674 1119
675 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1120 if (!CHIP_IS_E1(bp)) {
676 val, port, addr); 1121 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1122 val, port, addr);
677 1123
678 REG_WR(bp, addr, val); 1124 REG_WR(bp, addr, val);
679 1125
680 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1126 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1127 }
681 } 1128 }
682 1129
1130 if (CHIP_IS_E1(bp))
1131 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1132
683 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1133 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
684 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1134 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
685 1135
@@ -690,9 +1140,9 @@ void bnx2x_int_enable(struct bnx2x *bp)
690 mmiowb(); 1140 mmiowb();
691 barrier(); 1141 barrier();
692 1142
693 if (CHIP_IS_E1H(bp)) { 1143 if (!CHIP_IS_E1(bp)) {
694 /* init leading/trailing edge */ 1144 /* init leading/trailing edge */
695 if (IS_E1HMF(bp)) { 1145 if (IS_MF(bp)) {
696 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); 1146 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
697 if (bp->port.pmf) 1147 if (bp->port.pmf)
698 /* enable nig and gpio3 attention */ 1148 /* enable nig and gpio3 attention */
@@ -708,16 +1158,91 @@ void bnx2x_int_enable(struct bnx2x *bp)
708 mmiowb(); 1158 mmiowb();
709} 1159}
710 1160
711static void bnx2x_int_disable(struct bnx2x *bp) 1161static void bnx2x_igu_int_enable(struct bnx2x *bp)
1162{
1163 u32 val;
1164 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1165 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1166
1167 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1168
1169 if (msix) {
1170 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1171 IGU_PF_CONF_SINGLE_ISR_EN);
1172 val |= (IGU_PF_CONF_FUNC_EN |
1173 IGU_PF_CONF_MSI_MSIX_EN |
1174 IGU_PF_CONF_ATTN_BIT_EN);
1175 } else if (msi) {
1176 val &= ~IGU_PF_CONF_INT_LINE_EN;
1177 val |= (IGU_PF_CONF_FUNC_EN |
1178 IGU_PF_CONF_MSI_MSIX_EN |
1179 IGU_PF_CONF_ATTN_BIT_EN |
1180 IGU_PF_CONF_SINGLE_ISR_EN);
1181 } else {
1182 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1183 val |= (IGU_PF_CONF_FUNC_EN |
1184 IGU_PF_CONF_INT_LINE_EN |
1185 IGU_PF_CONF_ATTN_BIT_EN |
1186 IGU_PF_CONF_SINGLE_ISR_EN);
1187 }
1188
1189 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1190 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1191
1192 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1193
1194 barrier();
1195
1196 /* init leading/trailing edge */
1197 if (IS_MF(bp)) {
1198 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1199 if (bp->port.pmf)
1200 /* enable nig and gpio3 attention */
1201 val |= 0x1100;
1202 } else
1203 val = 0xffff;
1204
1205 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1206 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1207
1208 /* Make sure that interrupts are indeed enabled from here on */
1209 mmiowb();
1210}
1211
1212void bnx2x_int_enable(struct bnx2x *bp)
1213{
1214 if (bp->common.int_block == INT_BLOCK_HC)
1215 bnx2x_hc_int_enable(bp);
1216 else
1217 bnx2x_igu_int_enable(bp);
1218}
1219
1220static void bnx2x_hc_int_disable(struct bnx2x *bp)
712{ 1221{
713 int port = BP_PORT(bp); 1222 int port = BP_PORT(bp);
714 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1223 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
715 u32 val = REG_RD(bp, addr); 1224 u32 val = REG_RD(bp, addr);
716 1225
717 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1226 /*
718 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1227 * in E1 we must use only PCI configuration space to disable
719 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1228 * MSI/MSIX capablility
720 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1229 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1230 */
1231 if (CHIP_IS_E1(bp)) {
1232 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1233 * Use mask register to prevent from HC sending interrupts
1234 * after we exit the function
1235 */
1236 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1237
1238 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1239 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1240 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1241 } else
1242 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1243 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1244 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1245 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
721 1246
722 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1247 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
723 val, port, addr); 1248 val, port, addr);
@@ -730,6 +1255,32 @@ static void bnx2x_int_disable(struct bnx2x *bp)
730 BNX2X_ERR("BUG! proper val not read from IGU!\n"); 1255 BNX2X_ERR("BUG! proper val not read from IGU!\n");
731} 1256}
732 1257
1258static void bnx2x_igu_int_disable(struct bnx2x *bp)
1259{
1260 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1261
1262 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1263 IGU_PF_CONF_INT_LINE_EN |
1264 IGU_PF_CONF_ATTN_BIT_EN);
1265
1266 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1267
1268 /* flush all outstanding writes */
1269 mmiowb();
1270
1271 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1272 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1273 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1274}
1275
1276static void bnx2x_int_disable(struct bnx2x *bp)
1277{
1278 if (bp->common.int_block == INT_BLOCK_HC)
1279 bnx2x_hc_int_disable(bp);
1280 else
1281 bnx2x_igu_int_disable(bp);
1282}
1283
733void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1284void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
734{ 1285{
735 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1286 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
@@ -750,7 +1301,7 @@ void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
750#ifdef BCM_CNIC 1301#ifdef BCM_CNIC
751 offset++; 1302 offset++;
752#endif 1303#endif
753 for_each_queue(bp, i) 1304 for_each_eth_queue(bp, i)
754 synchronize_irq(bp->msix_table[i + offset].vector); 1305 synchronize_irq(bp->msix_table[i + offset].vector);
755 } else 1306 } else
756 synchronize_irq(bp->pdev->irq); 1307 synchronize_irq(bp->pdev->irq);
@@ -781,7 +1332,7 @@ static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
781 DP(NETIF_MSG_HW, 1332 DP(NETIF_MSG_HW,
782 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1333 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
783 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1334 resource, HW_LOCK_MAX_RESOURCE_VALUE);
784 return -EINVAL; 1335 return false;
785 } 1336 }
786 1337
787 if (func <= 5) 1338 if (func <= 5)
@@ -800,7 +1351,6 @@ static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
800 return false; 1351 return false;
801} 1352}
802 1353
803
804#ifdef BCM_CNIC 1354#ifdef BCM_CNIC
805static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid); 1355static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
806#endif 1356#endif
@@ -817,76 +1367,35 @@ void bnx2x_sp_event(struct bnx2x_fastpath *fp,
817 fp->index, cid, command, bp->state, 1367 fp->index, cid, command, bp->state,
818 rr_cqe->ramrod_cqe.ramrod_type); 1368 rr_cqe->ramrod_cqe.ramrod_type);
819 1369
820 bp->spq_left++; 1370 switch (command | fp->state) {
821 1371 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
822 if (fp->index) { 1372 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
823 switch (command | fp->state) { 1373 fp->state = BNX2X_FP_STATE_OPEN;
824 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
825 BNX2X_FP_STATE_OPENING):
826 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
827 cid);
828 fp->state = BNX2X_FP_STATE_OPEN;
829 break;
830
831 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
832 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
833 cid);
834 fp->state = BNX2X_FP_STATE_HALTED;
835 break;
836
837 default:
838 BNX2X_ERR("unexpected MC reply (%d) "
839 "fp[%d] state is %x\n",
840 command, fp->index, fp->state);
841 break;
842 }
843 mb(); /* force bnx2x_wait_ramrod() to see the change */
844 return;
845 }
846
847 switch (command | bp->state) {
848 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
849 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
850 bp->state = BNX2X_STATE_OPEN;
851 break; 1374 break;
852 1375
853 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT): 1376 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
854 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n"); 1377 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
855 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
856 fp->state = BNX2X_FP_STATE_HALTED; 1378 fp->state = BNX2X_FP_STATE_HALTED;
857 break; 1379 break;
858 1380
859 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT): 1381 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
860 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid); 1382 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
861 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED; 1383 fp->state = BNX2X_FP_STATE_TERMINATED;
862 break;
863
864#ifdef BCM_CNIC
865 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_OPEN):
866 DP(NETIF_MSG_IFDOWN, "got delete ramrod for CID %d\n", cid);
867 bnx2x_cnic_cfc_comp(bp, cid);
868 break;
869#endif
870
871 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
872 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
873 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
874 bp->set_mac_pending--;
875 smp_wmb();
876 break;
877
878 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
879 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
880 bp->set_mac_pending--;
881 smp_wmb();
882 break; 1384 break;
883 1385
884 default: 1386 default:
885 BNX2X_ERR("unexpected MC reply (%d) bp->state is %x\n", 1387 BNX2X_ERR("unexpected MC reply (%d) "
886 command, bp->state); 1388 "fp[%d] state is %x\n",
1389 command, fp->index, fp->state);
887 break; 1390 break;
888 } 1391 }
889 mb(); /* force bnx2x_wait_ramrod() to see the change */ 1392
1393 smp_mb__before_atomic_inc();
1394 atomic_inc(&bp->cq_spq_left);
1395 /* push the change in fp->state and towards the memory */
1396 smp_wmb();
1397
1398 return;
890} 1399}
891 1400
892irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1401irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
@@ -914,25 +1423,22 @@ irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
914 return IRQ_HANDLED; 1423 return IRQ_HANDLED;
915#endif 1424#endif
916 1425
917 for (i = 0; i < BNX2X_NUM_QUEUES(bp); i++) { 1426 for_each_eth_queue(bp, i) {
918 struct bnx2x_fastpath *fp = &bp->fp[i]; 1427 struct bnx2x_fastpath *fp = &bp->fp[i];
919 1428
920 mask = 0x2 << fp->sb_id; 1429 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
921 if (status & mask) { 1430 if (status & mask) {
922 /* Handle Rx and Tx according to SB id */ 1431 /* Handle Rx and Tx according to SB id */
923 prefetch(fp->rx_cons_sb); 1432 prefetch(fp->rx_cons_sb);
924 prefetch(&fp->status_blk->u_status_block.
925 status_block_index);
926 prefetch(fp->tx_cons_sb); 1433 prefetch(fp->tx_cons_sb);
927 prefetch(&fp->status_blk->c_status_block. 1434 prefetch(&fp->sb_running_index[SM_RX_ID]);
928 status_block_index);
929 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); 1435 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
930 status &= ~mask; 1436 status &= ~mask;
931 } 1437 }
932 } 1438 }
933 1439
934#ifdef BCM_CNIC 1440#ifdef BCM_CNIC
935 mask = 0x2 << CNIC_SB_ID(bp); 1441 mask = 0x2;
936 if (status & (mask | 0x1)) { 1442 if (status & (mask | 0x1)) {
937 struct cnic_ops *c_ops = NULL; 1443 struct cnic_ops *c_ops = NULL;
938 1444
@@ -1227,49 +1733,91 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1227 return 0; 1733 return 0;
1228} 1734}
1229 1735
1736int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1737{
1738 u32 sel_phy_idx = 0;
1739 if (bp->link_vars.link_up) {
1740 sel_phy_idx = EXT_PHY1;
1741 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1742 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1743 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1744 sel_phy_idx = EXT_PHY2;
1745 } else {
1746
1747 switch (bnx2x_phy_selection(&bp->link_params)) {
1748 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1749 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1750 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1751 sel_phy_idx = EXT_PHY1;
1752 break;
1753 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1754 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1755 sel_phy_idx = EXT_PHY2;
1756 break;
1757 }
1758 }
1759 /*
1760 * The selected actived PHY is always after swapping (in case PHY
1761 * swapping is enabled). So when swapping is enabled, we need to reverse
1762 * the configuration
1763 */
1764
1765 if (bp->link_params.multi_phy_config &
1766 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1767 if (sel_phy_idx == EXT_PHY1)
1768 sel_phy_idx = EXT_PHY2;
1769 else if (sel_phy_idx == EXT_PHY2)
1770 sel_phy_idx = EXT_PHY1;
1771 }
1772 return LINK_CONFIG_IDX(sel_phy_idx);
1773}
1774
1230void bnx2x_calc_fc_adv(struct bnx2x *bp) 1775void bnx2x_calc_fc_adv(struct bnx2x *bp)
1231{ 1776{
1777 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1232 switch (bp->link_vars.ieee_fc & 1778 switch (bp->link_vars.ieee_fc &
1233 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 1779 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1234 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 1780 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1235 bp->port.advertising &= ~(ADVERTISED_Asym_Pause | 1781 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1236 ADVERTISED_Pause); 1782 ADVERTISED_Pause);
1237 break; 1783 break;
1238 1784
1239 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 1785 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1240 bp->port.advertising |= (ADVERTISED_Asym_Pause | 1786 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
1241 ADVERTISED_Pause); 1787 ADVERTISED_Pause);
1242 break; 1788 break;
1243 1789
1244 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 1790 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1245 bp->port.advertising |= ADVERTISED_Asym_Pause; 1791 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
1246 break; 1792 break;
1247 1793
1248 default: 1794 default:
1249 bp->port.advertising &= ~(ADVERTISED_Asym_Pause | 1795 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1250 ADVERTISED_Pause); 1796 ADVERTISED_Pause);
1251 break; 1797 break;
1252 } 1798 }
1253} 1799}
1254 1800
1255
1256u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 1801u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1257{ 1802{
1258 if (!BP_NOMCP(bp)) { 1803 if (!BP_NOMCP(bp)) {
1259 u8 rc; 1804 u8 rc;
1260 1805 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1806 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1261 /* Initialize link parameters structure variables */ 1807 /* Initialize link parameters structure variables */
1262 /* It is recommended to turn off RX FC for jumbo frames 1808 /* It is recommended to turn off RX FC for jumbo frames
1263 for better performance */ 1809 for better performance */
1264 if (bp->dev->mtu > 5000) 1810 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
1265 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 1811 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1266 else 1812 else
1267 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 1813 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1268 1814
1269 bnx2x_acquire_phy_lock(bp); 1815 bnx2x_acquire_phy_lock(bp);
1270 1816
1271 if (load_mode == LOAD_DIAG) 1817 if (load_mode == LOAD_DIAG) {
1272 bp->link_params.loopback_mode = LOOPBACK_XGXS_10; 1818 bp->link_params.loopback_mode = LOOPBACK_XGXS;
1819 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1820 }
1273 1821
1274 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1822 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1275 1823
@@ -1281,7 +1829,7 @@ u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1281 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 1829 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1282 bnx2x_link_report(bp); 1830 bnx2x_link_report(bp);
1283 } 1831 }
1284 1832 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
1285 return rc; 1833 return rc;
1286 } 1834 }
1287 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 1835 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
@@ -1292,6 +1840,7 @@ void bnx2x_link_set(struct bnx2x *bp)
1292{ 1840{
1293 if (!BP_NOMCP(bp)) { 1841 if (!BP_NOMCP(bp)) {
1294 bnx2x_acquire_phy_lock(bp); 1842 bnx2x_acquire_phy_lock(bp);
1843 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1295 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1844 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1296 bnx2x_release_phy_lock(bp); 1845 bnx2x_release_phy_lock(bp);
1297 1846
@@ -1310,13 +1859,14 @@ static void bnx2x__link_reset(struct bnx2x *bp)
1310 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 1859 BNX2X_ERR("Bootcode is missing - can not reset link\n");
1311} 1860}
1312 1861
1313u8 bnx2x_link_test(struct bnx2x *bp) 1862u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
1314{ 1863{
1315 u8 rc = 0; 1864 u8 rc = 0;
1316 1865
1317 if (!BP_NOMCP(bp)) { 1866 if (!BP_NOMCP(bp)) {
1318 bnx2x_acquire_phy_lock(bp); 1867 bnx2x_acquire_phy_lock(bp);
1319 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars); 1868 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1869 is_serdes);
1320 bnx2x_release_phy_lock(bp); 1870 bnx2x_release_phy_lock(bp);
1321 } else 1871 } else
1322 BNX2X_ERR("Bootcode is missing - can not test link\n"); 1872 BNX2X_ERR("Bootcode is missing - can not test link\n");
@@ -1371,13 +1921,11 @@ static void bnx2x_init_port_minmax(struct bnx2x *bp)
1371static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) 1921static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1372{ 1922{
1373 int all_zero = 1; 1923 int all_zero = 1;
1374 int port = BP_PORT(bp);
1375 int vn; 1924 int vn;
1376 1925
1377 bp->vn_weight_sum = 0; 1926 bp->vn_weight_sum = 0;
1378 for (vn = VN_0; vn < E1HVN_MAX; vn++) { 1927 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1379 int func = 2*vn + port; 1928 u32 vn_cfg = bp->mf_config[vn];
1380 u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
1381 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 1929 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1382 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 1930 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1383 1931
@@ -1405,11 +1953,12 @@ static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1405 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 1953 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1406} 1954}
1407 1955
1408static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func) 1956static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
1409{ 1957{
1410 struct rate_shaping_vars_per_vn m_rs_vn; 1958 struct rate_shaping_vars_per_vn m_rs_vn;
1411 struct fairness_vars_per_vn m_fair_vn; 1959 struct fairness_vars_per_vn m_fair_vn;
1412 u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); 1960 u32 vn_cfg = bp->mf_config[vn];
1961 int func = 2*vn + BP_PORT(bp);
1413 u16 vn_min_rate, vn_max_rate; 1962 u16 vn_min_rate, vn_max_rate;
1414 int i; 1963 int i;
1415 1964
@@ -1419,14 +1968,24 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
1419 vn_max_rate = 0; 1968 vn_max_rate = 0;
1420 1969
1421 } else { 1970 } else {
1971 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
1972
1422 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 1973 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1423 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 1974 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1424 /* If min rate is zero - set it to 1 */ 1975 /* If fairness is enabled (not all min rates are zeroes) and
1425 if (!vn_min_rate) 1976 if current min rate is zero - set it to 1.
1977 This is a requirement of the algorithm. */
1978 if (bp->vn_weight_sum && (vn_min_rate == 0))
1426 vn_min_rate = DEF_MIN_RATE; 1979 vn_min_rate = DEF_MIN_RATE;
1427 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1980
1428 FUNC_MF_CFG_MAX_BW_SHIFT) * 100; 1981 if (IS_MF_SI(bp))
1982 /* maxCfg in percents of linkspeed */
1983 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
1984 else
1985 /* maxCfg is absolute in 100Mb units */
1986 vn_max_rate = maxCfg * 100;
1429 } 1987 }
1988
1430 DP(NETIF_MSG_IFUP, 1989 DP(NETIF_MSG_IFUP,
1431 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n", 1990 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
1432 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum); 1991 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
@@ -1450,7 +2009,8 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
1450 m_fair_vn.vn_credit_delta = 2009 m_fair_vn.vn_credit_delta =
1451 max_t(u32, (vn_min_rate * (T_FAIR_COEF / 2010 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
1452 (8 * bp->vn_weight_sum))), 2011 (8 * bp->vn_weight_sum))),
1453 (bp->cmng.fair_vars.fair_threshold * 2)); 2012 (bp->cmng.fair_vars.fair_threshold +
2013 MIN_ABOVE_THRESH));
1454 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n", 2014 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
1455 m_fair_vn.vn_credit_delta); 2015 m_fair_vn.vn_credit_delta);
1456 } 2016 }
@@ -1467,11 +2027,103 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
1467 ((u32 *)(&m_fair_vn))[i]); 2027 ((u32 *)(&m_fair_vn))[i]);
1468} 2028}
1469 2029
2030static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2031{
2032 if (CHIP_REV_IS_SLOW(bp))
2033 return CMNG_FNS_NONE;
2034 if (IS_MF(bp))
2035 return CMNG_FNS_MINMAX;
2036
2037 return CMNG_FNS_NONE;
2038}
2039
2040void bnx2x_read_mf_cfg(struct bnx2x *bp)
2041{
2042 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2043
2044 if (BP_NOMCP(bp))
2045 return; /* what should be the default bvalue in this case */
2046
2047 /* For 2 port configuration the absolute function number formula
2048 * is:
2049 * abs_func = 2 * vn + BP_PORT + BP_PATH
2050 *
2051 * and there are 4 functions per port
2052 *
2053 * For 4 port configuration it is
2054 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2055 *
2056 * and there are 2 functions per port
2057 */
2058 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2059 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2060
2061 if (func >= E1H_FUNC_MAX)
2062 break;
2063
2064 bp->mf_config[vn] =
2065 MF_CFG_RD(bp, func_mf_config[func].config);
2066 }
2067}
2068
2069static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2070{
2071
2072 if (cmng_type == CMNG_FNS_MINMAX) {
2073 int vn;
2074
2075 /* clear cmng_enables */
2076 bp->cmng.flags.cmng_enables = 0;
2077
2078 /* read mf conf from shmem */
2079 if (read_cfg)
2080 bnx2x_read_mf_cfg(bp);
2081
2082 /* Init rate shaping and fairness contexts */
2083 bnx2x_init_port_minmax(bp);
2084
2085 /* vn_weight_sum and enable fairness if not 0 */
2086 bnx2x_calc_vn_weight_sum(bp);
2087
2088 /* calculate and set min-max rate for each vn */
2089 if (bp->port.pmf)
2090 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2091 bnx2x_init_vn_minmax(bp, vn);
2092
2093 /* always enable rate shaping and fairness */
2094 bp->cmng.flags.cmng_enables |=
2095 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2096 if (!bp->vn_weight_sum)
2097 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2098 " fairness will be disabled\n");
2099 return;
2100 }
2101
2102 /* rate shaping and fairness are disabled */
2103 DP(NETIF_MSG_IFUP,
2104 "rate shaping and fairness are disabled\n");
2105}
2106
2107static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2108{
2109 int port = BP_PORT(bp);
2110 int func;
2111 int vn;
2112
2113 /* Set the attention towards other drivers on the same port */
2114 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2115 if (vn == BP_E1HVN(bp))
2116 continue;
2117
2118 func = ((vn << 1) | port);
2119 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2120 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2121 }
2122}
1470 2123
1471/* This function is called upon link interrupt */ 2124/* This function is called upon link interrupt */
1472static void bnx2x_link_attn(struct bnx2x *bp) 2125static void bnx2x_link_attn(struct bnx2x *bp)
1473{ 2126{
1474 u32 prev_link_status = bp->link_vars.link_status;
1475 /* Make sure that we are synced with the current statistics */ 2127 /* Make sure that we are synced with the current statistics */
1476 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2128 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1477 2129
@@ -1480,7 +2132,7 @@ static void bnx2x_link_attn(struct bnx2x *bp)
1480 if (bp->link_vars.link_up) { 2132 if (bp->link_vars.link_up) {
1481 2133
1482 /* dropless flow control */ 2134 /* dropless flow control */
1483 if (CHIP_IS_E1H(bp) && bp->dropless_fc) { 2135 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
1484 int port = BP_PORT(bp); 2136 int port = BP_PORT(bp);
1485 u32 pause_enabled = 0; 2137 u32 pause_enabled = 0;
1486 2138
@@ -1504,47 +2156,27 @@ static void bnx2x_link_attn(struct bnx2x *bp)
1504 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2156 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1505 } 2157 }
1506 2158
1507 /* indicate link status only if link status actually changed */ 2159 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
1508 if (prev_link_status != bp->link_vars.link_status) 2160 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
1509 bnx2x_link_report(bp);
1510 2161
1511 if (IS_E1HMF(bp)) { 2162 if (cmng_fns != CMNG_FNS_NONE) {
1512 int port = BP_PORT(bp); 2163 bnx2x_cmng_fns_init(bp, false, cmng_fns);
1513 int func; 2164 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
1514 int vn; 2165 } else
1515 2166 /* rate shaping and fairness are disabled */
1516 /* Set the attention towards other drivers on the same port */ 2167 DP(NETIF_MSG_IFUP,
1517 for (vn = VN_0; vn < E1HVN_MAX; vn++) { 2168 "single function mode without fairness\n");
1518 if (vn == BP_E1HVN(bp)) 2169 }
1519 continue;
1520
1521 func = ((vn << 1) | port);
1522 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1523 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1524 }
1525
1526 if (bp->link_vars.link_up) {
1527 int i;
1528 2170
1529 /* Init rate shaping and fairness contexts */ 2171 __bnx2x_link_report(bp);
1530 bnx2x_init_port_minmax(bp);
1531 2172
1532 for (vn = VN_0; vn < E1HVN_MAX; vn++) 2173 if (IS_MF(bp))
1533 bnx2x_init_vn_minmax(bp, 2*vn + port); 2174 bnx2x_link_sync_notify(bp);
1534
1535 /* Store it to internal memory */
1536 for (i = 0;
1537 i < sizeof(struct cmng_struct_per_port) / 4; i++)
1538 REG_WR(bp, BAR_XSTRORM_INTMEM +
1539 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
1540 ((u32 *)(&bp->cmng))[i]);
1541 }
1542 }
1543} 2175}
1544 2176
1545void bnx2x__link_status_update(struct bnx2x *bp) 2177void bnx2x__link_status_update(struct bnx2x *bp)
1546{ 2178{
1547 if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS)) 2179 if (bp->state != BNX2X_STATE_OPEN)
1548 return; 2180 return;
1549 2181
1550 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2182 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
@@ -1554,8 +2186,6 @@ void bnx2x__link_status_update(struct bnx2x *bp)
1554 else 2186 else
1555 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2187 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1556 2188
1557 bnx2x_calc_vn_weight_sum(bp);
1558
1559 /* indicate link status */ 2189 /* indicate link status */
1560 bnx2x_link_report(bp); 2190 bnx2x_link_report(bp);
1561} 2191}
@@ -1570,8 +2200,13 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
1570 2200
1571 /* enable nig attention */ 2201 /* enable nig attention */
1572 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4))); 2202 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
1573 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2203 if (bp->common.int_block == INT_BLOCK_HC) {
1574 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2204 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2205 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2206 } else if (CHIP_IS_E2(bp)) {
2207 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2208 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2209 }
1575 2210
1576 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 2211 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
1577} 2212}
@@ -1585,23 +2220,26 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
1585 */ 2220 */
1586 2221
1587/* send the MCP a request, block until there is a reply */ 2222/* send the MCP a request, block until there is a reply */
1588u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) 2223u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
1589{ 2224{
1590 int func = BP_FUNC(bp); 2225 int mb_idx = BP_FW_MB_IDX(bp);
1591 u32 seq = ++bp->fw_seq; 2226 u32 seq;
1592 u32 rc = 0; 2227 u32 rc = 0;
1593 u32 cnt = 1; 2228 u32 cnt = 1;
1594 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 2229 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
1595 2230
1596 mutex_lock(&bp->fw_mb_mutex); 2231 mutex_lock(&bp->fw_mb_mutex);
1597 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq)); 2232 seq = ++bp->fw_seq;
2233 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2234 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2235
1598 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq)); 2236 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
1599 2237
1600 do { 2238 do {
1601 /* let the FW do it's magic ... */ 2239 /* let the FW do it's magic ... */
1602 msleep(delay); 2240 msleep(delay);
1603 2241
1604 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header); 2242 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
1605 2243
1606 /* Give the FW up to 5 second (500*10ms) */ 2244 /* Give the FW up to 5 second (500*10ms) */
1607 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2245 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
@@ -1623,6 +2261,351 @@ u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
1623 return rc; 2261 return rc;
1624} 2262}
1625 2263
2264static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2265{
2266#ifdef BCM_CNIC
2267 if (IS_FCOE_FP(fp) && IS_MF(bp))
2268 return false;
2269#endif
2270 return true;
2271}
2272
2273/* must be called under rtnl_lock */
2274static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2275{
2276 u32 mask = (1 << cl_id);
2277
2278 /* initial seeting is BNX2X_ACCEPT_NONE */
2279 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2280 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2281 u8 unmatched_unicast = 0;
2282
2283 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2284 unmatched_unicast = 1;
2285
2286 if (filters & BNX2X_PROMISCUOUS_MODE) {
2287 /* promiscious - accept all, drop none */
2288 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2289 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
2290 if (IS_MF_SI(bp)) {
2291 /*
2292 * SI mode defines to accept in promiscuos mode
2293 * only unmatched packets
2294 */
2295 unmatched_unicast = 1;
2296 accp_all_ucast = 0;
2297 }
2298 }
2299 if (filters & BNX2X_ACCEPT_UNICAST) {
2300 /* accept matched ucast */
2301 drop_all_ucast = 0;
2302 }
2303 if (filters & BNX2X_ACCEPT_MULTICAST)
2304 /* accept matched mcast */
2305 drop_all_mcast = 0;
2306
2307 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2308 /* accept all mcast */
2309 drop_all_ucast = 0;
2310 accp_all_ucast = 1;
2311 }
2312 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2313 /* accept all mcast */
2314 drop_all_mcast = 0;
2315 accp_all_mcast = 1;
2316 }
2317 if (filters & BNX2X_ACCEPT_BROADCAST) {
2318 /* accept (all) bcast */
2319 drop_all_bcast = 0;
2320 accp_all_bcast = 1;
2321 }
2322
2323 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2324 bp->mac_filters.ucast_drop_all | mask :
2325 bp->mac_filters.ucast_drop_all & ~mask;
2326
2327 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2328 bp->mac_filters.mcast_drop_all | mask :
2329 bp->mac_filters.mcast_drop_all & ~mask;
2330
2331 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2332 bp->mac_filters.bcast_drop_all | mask :
2333 bp->mac_filters.bcast_drop_all & ~mask;
2334
2335 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2336 bp->mac_filters.ucast_accept_all | mask :
2337 bp->mac_filters.ucast_accept_all & ~mask;
2338
2339 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2340 bp->mac_filters.mcast_accept_all | mask :
2341 bp->mac_filters.mcast_accept_all & ~mask;
2342
2343 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2344 bp->mac_filters.bcast_accept_all | mask :
2345 bp->mac_filters.bcast_accept_all & ~mask;
2346
2347 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2348 bp->mac_filters.unmatched_unicast | mask :
2349 bp->mac_filters.unmatched_unicast & ~mask;
2350}
2351
2352static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2353{
2354 struct tstorm_eth_function_common_config tcfg = {0};
2355 u16 rss_flgs;
2356
2357 /* tpa */
2358 if (p->func_flgs & FUNC_FLG_TPA)
2359 tcfg.config_flags |=
2360 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2361
2362 /* set rss flags */
2363 rss_flgs = (p->rss->mode <<
2364 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2365
2366 if (p->rss->cap & RSS_IPV4_CAP)
2367 rss_flgs |= RSS_IPV4_CAP_MASK;
2368 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2369 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2370 if (p->rss->cap & RSS_IPV6_CAP)
2371 rss_flgs |= RSS_IPV6_CAP_MASK;
2372 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2373 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2374
2375 tcfg.config_flags |= rss_flgs;
2376 tcfg.rss_result_mask = p->rss->result_mask;
2377
2378 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2379
2380 /* Enable the function in the FW */
2381 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2382 storm_memset_func_en(bp, p->func_id, 1);
2383
2384 /* statistics */
2385 if (p->func_flgs & FUNC_FLG_STATS) {
2386 struct stats_indication_flags stats_flags = {0};
2387 stats_flags.collect_eth = 1;
2388
2389 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2390 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2391
2392 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2393 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2394
2395 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2396 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2397
2398 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2399 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2400 }
2401
2402 /* spq */
2403 if (p->func_flgs & FUNC_FLG_SPQ) {
2404 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2405 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2406 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2407 }
2408}
2409
2410static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2411 struct bnx2x_fastpath *fp)
2412{
2413 u16 flags = 0;
2414
2415 /* calculate queue flags */
2416 flags |= QUEUE_FLG_CACHE_ALIGN;
2417 flags |= QUEUE_FLG_HC;
2418 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
2419
2420 flags |= QUEUE_FLG_VLAN;
2421 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
2422
2423 if (!fp->disable_tpa)
2424 flags |= QUEUE_FLG_TPA;
2425
2426 flags = stat_counter_valid(bp, fp) ?
2427 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
2428
2429 return flags;
2430}
2431
2432static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2433 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2434 struct bnx2x_rxq_init_params *rxq_init)
2435{
2436 u16 max_sge = 0;
2437 u16 sge_sz = 0;
2438 u16 tpa_agg_size = 0;
2439
2440 /* calculate queue flags */
2441 u16 flags = bnx2x_get_cl_flags(bp, fp);
2442
2443 if (!fp->disable_tpa) {
2444 pause->sge_th_hi = 250;
2445 pause->sge_th_lo = 150;
2446 tpa_agg_size = min_t(u32,
2447 (min_t(u32, 8, MAX_SKB_FRAGS) *
2448 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2449 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2450 SGE_PAGE_SHIFT;
2451 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2452 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2453 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2454 0xffff);
2455 }
2456
2457 /* pause - not for e1 */
2458 if (!CHIP_IS_E1(bp)) {
2459 pause->bd_th_hi = 350;
2460 pause->bd_th_lo = 250;
2461 pause->rcq_th_hi = 350;
2462 pause->rcq_th_lo = 250;
2463 pause->sge_th_hi = 0;
2464 pause->sge_th_lo = 0;
2465 pause->pri_map = 1;
2466 }
2467
2468 /* rxq setup */
2469 rxq_init->flags = flags;
2470 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2471 rxq_init->dscr_map = fp->rx_desc_mapping;
2472 rxq_init->sge_map = fp->rx_sge_mapping;
2473 rxq_init->rcq_map = fp->rx_comp_mapping;
2474 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2475
2476 /* Always use mini-jumbo MTU for FCoE L2 ring */
2477 if (IS_FCOE_FP(fp))
2478 rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2479 else
2480 rxq_init->mtu = bp->dev->mtu;
2481
2482 rxq_init->buf_sz = fp->rx_buf_size;
2483 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2484 rxq_init->cl_id = fp->cl_id;
2485 rxq_init->spcl_id = fp->cl_id;
2486 rxq_init->stat_id = fp->cl_id;
2487 rxq_init->tpa_agg_sz = tpa_agg_size;
2488 rxq_init->sge_buf_sz = sge_sz;
2489 rxq_init->max_sges_pkt = max_sge;
2490 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2491 rxq_init->fw_sb_id = fp->fw_sb_id;
2492
2493 if (IS_FCOE_FP(fp))
2494 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2495 else
2496 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2497
2498 rxq_init->cid = HW_CID(bp, fp->cid);
2499
2500 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2501}
2502
2503static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2504 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2505{
2506 u16 flags = bnx2x_get_cl_flags(bp, fp);
2507
2508 txq_init->flags = flags;
2509 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2510 txq_init->dscr_map = fp->tx_desc_mapping;
2511 txq_init->stat_id = fp->cl_id;
2512 txq_init->cid = HW_CID(bp, fp->cid);
2513 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2514 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2515 txq_init->fw_sb_id = fp->fw_sb_id;
2516
2517 if (IS_FCOE_FP(fp)) {
2518 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2519 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2520 }
2521
2522 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2523}
2524
2525static void bnx2x_pf_init(struct bnx2x *bp)
2526{
2527 struct bnx2x_func_init_params func_init = {0};
2528 struct bnx2x_rss_params rss = {0};
2529 struct event_ring_data eq_data = { {0} };
2530 u16 flags;
2531
2532 /* pf specific setups */
2533 if (!CHIP_IS_E1(bp))
2534 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
2535
2536 if (CHIP_IS_E2(bp)) {
2537 /* reset IGU PF statistics: MSIX + ATTN */
2538 /* PF */
2539 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2540 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2541 (CHIP_MODE_IS_4_PORT(bp) ?
2542 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2543 /* ATTN */
2544 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2545 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2546 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2547 (CHIP_MODE_IS_4_PORT(bp) ?
2548 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2549 }
2550
2551 /* function setup flags */
2552 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2553
2554 if (CHIP_IS_E1x(bp))
2555 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2556 else
2557 flags |= FUNC_FLG_TPA;
2558
2559 /* function setup */
2560
2561 /**
2562 * Although RSS is meaningless when there is a single HW queue we
2563 * still need it enabled in order to have HW Rx hash generated.
2564 */
2565 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2566 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2567 rss.mode = bp->multi_mode;
2568 rss.result_mask = MULTI_MASK;
2569 func_init.rss = &rss;
2570
2571 func_init.func_flgs = flags;
2572 func_init.pf_id = BP_FUNC(bp);
2573 func_init.func_id = BP_FUNC(bp);
2574 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2575 func_init.spq_map = bp->spq_mapping;
2576 func_init.spq_prod = bp->spq_prod_idx;
2577
2578 bnx2x_func_init(bp, &func_init);
2579
2580 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2581
2582 /*
2583 Congestion management values depend on the link rate
2584 There is no active link so initial link rate is set to 10 Gbps.
2585 When the link comes up The congestion management values are
2586 re-calculated according to the actual link rate.
2587 */
2588 bp->link_vars.line_speed = SPEED_10000;
2589 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2590
2591 /* Only the PMF sets the HW */
2592 if (bp->port.pmf)
2593 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2594
2595 /* no rx until link is up */
2596 bp->rx_mode = BNX2X_RX_MODE_NONE;
2597 bnx2x_set_storm_rx_mode(bp);
2598
2599 /* init Event Queue */
2600 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2601 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2602 eq_data.producer = bp->eq_prod;
2603 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2604 eq_data.sb_id = DEF_SB_ID;
2605 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2606}
2607
2608
1626static void bnx2x_e1h_disable(struct bnx2x *bp) 2609static void bnx2x_e1h_disable(struct bnx2x *bp)
1627{ 2610{
1628 int port = BP_PORT(bp); 2611 int port = BP_PORT(bp);
@@ -1649,38 +2632,24 @@ static void bnx2x_e1h_enable(struct bnx2x *bp)
1649 */ 2632 */
1650} 2633}
1651 2634
1652static void bnx2x_update_min_max(struct bnx2x *bp) 2635/* called due to MCP event (on pmf):
2636 * reread new bandwidth configuration
2637 * configure FW
2638 * notify others function about the change
2639 */
2640static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
1653{ 2641{
1654 int port = BP_PORT(bp); 2642 if (bp->link_vars.link_up) {
1655 int vn, i; 2643 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
1656 2644 bnx2x_link_sync_notify(bp);
1657 /* Init rate shaping and fairness contexts */
1658 bnx2x_init_port_minmax(bp);
1659
1660 bnx2x_calc_vn_weight_sum(bp);
1661
1662 for (vn = VN_0; vn < E1HVN_MAX; vn++)
1663 bnx2x_init_vn_minmax(bp, 2*vn + port);
1664
1665 if (bp->port.pmf) {
1666 int func;
1667
1668 /* Set the attention towards other drivers on the same port */
1669 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1670 if (vn == BP_E1HVN(bp))
1671 continue;
1672
1673 func = ((vn << 1) | port);
1674 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1675 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1676 }
1677
1678 /* Store it to internal memory */
1679 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
1680 REG_WR(bp, BAR_XSTRORM_INTMEM +
1681 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
1682 ((u32 *)(&bp->cmng))[i]);
1683 } 2645 }
2646 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2647}
2648
2649static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2650{
2651 bnx2x_config_mf_bw(bp);
2652 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
1684} 2653}
1685 2654
1686static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event) 2655static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
@@ -1694,7 +2663,7 @@ static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
1694 * where the bp->flags can change so it is done without any 2663 * where the bp->flags can change so it is done without any
1695 * locks 2664 * locks
1696 */ 2665 */
1697 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) { 2666 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
1698 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 2667 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
1699 bp->flags |= MF_FUNC_DIS; 2668 bp->flags |= MF_FUNC_DIS;
1700 2669
@@ -1708,16 +2677,15 @@ static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
1708 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 2677 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
1709 } 2678 }
1710 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 2679 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
1711 2680 bnx2x_config_mf_bw(bp);
1712 bnx2x_update_min_max(bp);
1713 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 2681 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
1714 } 2682 }
1715 2683
1716 /* Report results to MCP */ 2684 /* Report results to MCP */
1717 if (dcc_event) 2685 if (dcc_event)
1718 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE); 2686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
1719 else 2687 else
1720 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK); 2688 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
1721} 2689}
1722 2690
1723/* must be called under the spq lock */ 2691/* must be called under the spq lock */
@@ -1744,16 +2712,17 @@ static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
1744 /* Make sure that BD data is updated before writing the producer */ 2712 /* Make sure that BD data is updated before writing the producer */
1745 wmb(); 2713 wmb();
1746 2714
1747 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 2715 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
1748 bp->spq_prod_idx); 2716 bp->spq_prod_idx);
1749 mmiowb(); 2717 mmiowb();
1750} 2718}
1751 2719
1752/* the slow path queue is odd since completions arrive on the fastpath ring */ 2720/* the slow path queue is odd since completions arrive on the fastpath ring */
1753int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2721int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1754 u32 data_hi, u32 data_lo, int common) 2722 u32 data_hi, u32 data_lo, int common)
1755{ 2723{
1756 struct eth_spe *spe; 2724 struct eth_spe *spe;
2725 u16 type;
1757 2726
1758#ifdef BNX2X_STOP_ON_ERROR 2727#ifdef BNX2X_STOP_ON_ERROR
1759 if (unlikely(bp->panic)) 2728 if (unlikely(bp->panic))
@@ -1762,11 +2731,18 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1762 2731
1763 spin_lock_bh(&bp->spq_lock); 2732 spin_lock_bh(&bp->spq_lock);
1764 2733
1765 if (!bp->spq_left) { 2734 if (common) {
1766 BNX2X_ERR("BUG! SPQ ring full!\n"); 2735 if (!atomic_read(&bp->eq_spq_left)) {
1767 spin_unlock_bh(&bp->spq_lock); 2736 BNX2X_ERR("BUG! EQ ring full!\n");
1768 bnx2x_panic(); 2737 spin_unlock_bh(&bp->spq_lock);
1769 return -EBUSY; 2738 bnx2x_panic();
2739 return -EBUSY;
2740 }
2741 } else if (!atomic_read(&bp->cq_spq_left)) {
2742 BNX2X_ERR("BUG! SPQ ring full!\n");
2743 spin_unlock_bh(&bp->spq_lock);
2744 bnx2x_panic();
2745 return -EBUSY;
1770 } 2746 }
1771 2747
1772 spe = bnx2x_sp_get_next(bp); 2748 spe = bnx2x_sp_get_next(bp);
@@ -1775,22 +2751,48 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1775 spe->hdr.conn_and_cmd_data = 2751 spe->hdr.conn_and_cmd_data =
1776 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 2752 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
1777 HW_CID(bp, cid)); 2753 HW_CID(bp, cid));
1778 spe->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE); 2754
1779 if (common) 2755 if (common)
1780 spe->hdr.type |= 2756 /* Common ramrods:
1781 cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT)); 2757 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2758 * TRAFFIC_STOP, TRAFFIC_START
2759 */
2760 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2761 & SPE_HDR_CONN_TYPE;
2762 else
2763 /* ETH ramrods: SETUP, HALT */
2764 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2765 & SPE_HDR_CONN_TYPE;
2766
2767 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2768 SPE_HDR_FUNCTION_ID);
1782 2769
1783 spe->data.mac_config_addr.hi = cpu_to_le32(data_hi); 2770 spe->hdr.type = cpu_to_le16(type);
1784 spe->data.mac_config_addr.lo = cpu_to_le32(data_lo); 2771
2772 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2773 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2774
2775 /* stats ramrod has it's own slot on the spq */
2776 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
2777 /* It's ok if the actual decrement is issued towards the memory
2778 * somewhere between the spin_lock and spin_unlock. Thus no
2779 * more explict memory barrier is needed.
2780 */
2781 if (common)
2782 atomic_dec(&bp->eq_spq_left);
2783 else
2784 atomic_dec(&bp->cq_spq_left);
2785 }
1785 2786
1786 bp->spq_left--;
1787 2787
1788 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 2788 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
1789 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n", 2789 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2790 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
1790 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 2791 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
1791 (u32)(U64_LO(bp->spq_mapping) + 2792 (u32)(U64_LO(bp->spq_mapping) +
1792 (void *)bp->spq_prod_bd - (void *)bp->spq), command, 2793 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
1793 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left); 2794 HW_CID(bp, cid), data_hi, data_lo, type,
2795 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
1794 2796
1795 bnx2x_sp_prod_update(bp); 2797 bnx2x_sp_prod_update(bp);
1796 spin_unlock_bh(&bp->spq_lock); 2798 spin_unlock_bh(&bp->spq_lock);
@@ -1827,32 +2829,27 @@ static void bnx2x_release_alr(struct bnx2x *bp)
1827 REG_WR(bp, GRCBASE_MCP + 0x9c, 0); 2829 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
1828} 2830}
1829 2831
2832#define BNX2X_DEF_SB_ATT_IDX 0x0001
2833#define BNX2X_DEF_SB_IDX 0x0002
2834
1830static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 2835static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
1831{ 2836{
1832 struct host_def_status_block *def_sb = bp->def_status_blk; 2837 struct host_sp_status_block *def_sb = bp->def_status_blk;
1833 u16 rc = 0; 2838 u16 rc = 0;
1834 2839
1835 barrier(); /* status block is written to by the chip */ 2840 barrier(); /* status block is written to by the chip */
1836 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 2841 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
1837 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 2842 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
1838 rc |= 1; 2843 rc |= BNX2X_DEF_SB_ATT_IDX;
1839 }
1840 if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
1841 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
1842 rc |= 2;
1843 }
1844 if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
1845 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
1846 rc |= 4;
1847 }
1848 if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
1849 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
1850 rc |= 8;
1851 } 2844 }
1852 if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) { 2845
1853 bp->def_t_idx = def_sb->t_def_status_block.status_block_index; 2846 if (bp->def_idx != def_sb->sp_sb.running_index) {
1854 rc |= 16; 2847 bp->def_idx = def_sb->sp_sb.running_index;
2848 rc |= BNX2X_DEF_SB_IDX;
1855 } 2849 }
2850
2851 /* Do not reorder: indecies reading should complete before handling */
2852 barrier();
1856 return rc; 2853 return rc;
1857} 2854}
1858 2855
@@ -1863,14 +2860,13 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
1863static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 2860static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
1864{ 2861{
1865 int port = BP_PORT(bp); 2862 int port = BP_PORT(bp);
1866 u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
1867 COMMAND_REG_ATTN_BITS_SET);
1868 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 2863 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
1869 MISC_REG_AEU_MASK_ATTN_FUNC_0; 2864 MISC_REG_AEU_MASK_ATTN_FUNC_0;
1870 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 2865 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
1871 NIG_REG_MASK_INTERRUPT_PORT0; 2866 NIG_REG_MASK_INTERRUPT_PORT0;
1872 u32 aeu_mask; 2867 u32 aeu_mask;
1873 u32 nig_mask = 0; 2868 u32 nig_mask = 0;
2869 u32 reg_addr;
1874 2870
1875 if (bp->attn_state & asserted) 2871 if (bp->attn_state & asserted)
1876 BNX2X_ERR("IGU ERROR\n"); 2872 BNX2X_ERR("IGU ERROR\n");
@@ -1945,9 +2941,15 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
1945 2941
1946 } /* if hardwired */ 2942 } /* if hardwired */
1947 2943
1948 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n", 2944 if (bp->common.int_block == INT_BLOCK_HC)
1949 asserted, hc_addr); 2945 reg_addr = (HC_REG_COMMAND_REG + port*32 +
1950 REG_WR(bp, hc_addr, asserted); 2946 COMMAND_REG_ATTN_BITS_SET);
2947 else
2948 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2949
2950 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2951 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2952 REG_WR(bp, reg_addr, asserted);
1951 2953
1952 /* now set back the mask */ 2954 /* now set back the mask */
1953 if (asserted & ATTN_NIG_FOR_FUNC) { 2955 if (asserted & ATTN_NIG_FOR_FUNC) {
@@ -1959,12 +2961,16 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
1959static inline void bnx2x_fan_failure(struct bnx2x *bp) 2961static inline void bnx2x_fan_failure(struct bnx2x *bp)
1960{ 2962{
1961 int port = BP_PORT(bp); 2963 int port = BP_PORT(bp);
1962 2964 u32 ext_phy_config;
1963 /* mark the failure */ 2965 /* mark the failure */
1964 bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 2966 ext_phy_config =
1965 bp->link_params.ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 2967 SHMEM_RD(bp,
2968 dev_info.port_hw_config[port].external_phy_config);
2969
2970 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2971 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
1966 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 2972 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
1967 bp->link_params.ext_phy_config); 2973 ext_phy_config);
1968 2974
1969 /* log the failure */ 2975 /* log the failure */
1970 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 2976 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
@@ -1976,7 +2982,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
1976{ 2982{
1977 int port = BP_PORT(bp); 2983 int port = BP_PORT(bp);
1978 int reg_offset; 2984 int reg_offset;
1979 u32 val, swap_val, swap_override; 2985 u32 val;
1980 2986
1981 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 2987 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
1982 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 2988 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
@@ -1990,30 +2996,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
1990 BNX2X_ERR("SPIO5 hw attention\n"); 2996 BNX2X_ERR("SPIO5 hw attention\n");
1991 2997
1992 /* Fan failure attention */ 2998 /* Fan failure attention */
1993 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) { 2999 bnx2x_hw_reset_phy(&bp->link_params);
1994 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
1995 /* Low power mode is controlled by GPIO 2 */
1996 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1997 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
1998 /* The PHY reset is controlled by GPIO 1 */
1999 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2000 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2001 break;
2002
2003 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
2004 /* The PHY reset is controlled by GPIO 1 */
2005 /* fake the port number to cancel the swap done in
2006 set_gpio() */
2007 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
2008 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
2009 port = (swap_val && swap_override) ^ 1;
2010 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2011 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2012 break;
2013
2014 default:
2015 break;
2016 }
2017 bnx2x_fan_failure(bp); 3000 bnx2x_fan_failure(bp);
2018 } 3001 }
2019 3002
@@ -2087,6 +3070,10 @@ static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2087 /* RQ_USDMDP_FIFO_OVERFLOW */ 3070 /* RQ_USDMDP_FIFO_OVERFLOW */
2088 if (val & 0x18000) 3071 if (val & 0x18000)
2089 BNX2X_ERR("FATAL error from PXP\n"); 3072 BNX2X_ERR("FATAL error from PXP\n");
3073 if (CHIP_IS_E2(bp)) {
3074 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3075 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3076 }
2090 } 3077 }
2091 3078
2092 if (attn & HW_INTERRUT_ASSERT_SET_2) { 3079 if (attn & HW_INTERRUT_ASSERT_SET_2) {
@@ -2117,16 +3104,31 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2117 int func = BP_FUNC(bp); 3104 int func = BP_FUNC(bp);
2118 3105
2119 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 3106 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2120 bp->mf_config = SHMEM_RD(bp, 3107 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
2121 mf_cfg.func_mf_config[func].config); 3108 func_mf_config[BP_ABS_FUNC(bp)].config);
2122 val = SHMEM_RD(bp, func_mb[func].drv_status); 3109 val = SHMEM_RD(bp,
3110 func_mb[BP_FW_MB_IDX(bp)].drv_status);
2123 if (val & DRV_STATUS_DCC_EVENT_MASK) 3111 if (val & DRV_STATUS_DCC_EVENT_MASK)
2124 bnx2x_dcc_event(bp, 3112 bnx2x_dcc_event(bp,
2125 (val & DRV_STATUS_DCC_EVENT_MASK)); 3113 (val & DRV_STATUS_DCC_EVENT_MASK));
2126 bnx2x__link_status_update(bp); 3114
3115 if (val & DRV_STATUS_SET_MF_BW)
3116 bnx2x_set_mf_bw(bp);
3117
2127 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3118 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
2128 bnx2x_pmf_update(bp); 3119 bnx2x_pmf_update(bp);
2129 3120
3121 /* Always call it here: bnx2x_link_report() will
3122 * prevent the link indication duplication.
3123 */
3124 bnx2x__link_status_update(bp);
3125
3126 if (bp->port.pmf &&
3127 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3128 bp->dcbx_enabled > 0)
3129 /* start dcbx state machine */
3130 bnx2x_dcbx_set_params(bp,
3131 BNX2X_DCBX_STATE_NEG_RECEIVED);
2130 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3132 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2131 3133
2132 BNX2X_ERR("MC assert!\n"); 3134 BNX2X_ERR("MC assert!\n");
@@ -2149,13 +3151,13 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2149 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 3151 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2150 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 3152 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2151 if (attn & BNX2X_GRC_TIMEOUT) { 3153 if (attn & BNX2X_GRC_TIMEOUT) {
2152 val = CHIP_IS_E1H(bp) ? 3154 val = CHIP_IS_E1(bp) ? 0 :
2153 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0; 3155 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
2154 BNX2X_ERR("GRC time-out 0x%08x\n", val); 3156 BNX2X_ERR("GRC time-out 0x%08x\n", val);
2155 } 3157 }
2156 if (attn & BNX2X_GRC_RSV) { 3158 if (attn & BNX2X_GRC_RSV) {
2157 val = CHIP_IS_E1H(bp) ? 3159 val = CHIP_IS_E1(bp) ? 0 :
2158 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0; 3160 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
2159 BNX2X_ERR("GRC reserved 0x%08x\n", val); 3161 BNX2X_ERR("GRC reserved 0x%08x\n", val);
2160 } 3162 }
2161 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 3163 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
@@ -2167,7 +3169,7 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2167#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1) 3169#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
2168#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK) 3170#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
2169#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS 3171#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
2170#define CHIP_PARITY_SUPPORTED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) 3172
2171/* 3173/*
2172 * should be run under rtnl lock 3174 * should be run under rtnl lock
2173 */ 3175 */
@@ -2460,6 +3462,74 @@ bool bnx2x_chk_parity_attn(struct bnx2x *bp)
2460 attn.sig[3]); 3462 attn.sig[3]);
2461} 3463}
2462 3464
3465
3466static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3467{
3468 u32 val;
3469 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3470
3471 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3472 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3473 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3474 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3475 "ADDRESS_ERROR\n");
3476 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3477 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3478 "INCORRECT_RCV_BEHAVIOR\n");
3479 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3480 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3481 "WAS_ERROR_ATTN\n");
3482 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3483 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3484 "VF_LENGTH_VIOLATION_ATTN\n");
3485 if (val &
3486 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3487 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3488 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3489 if (val &
3490 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3491 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3492 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3493 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3494 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3495 "TCPL_ERROR_ATTN\n");
3496 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3497 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3498 "TCPL_IN_TWO_RCBS_ATTN\n");
3499 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3500 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3501 "CSSNOOP_FIFO_OVERFLOW\n");
3502 }
3503 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3504 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3505 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3506 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3507 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3508 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3509 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3510 "_ATC_TCPL_TO_NOT_PEND\n");
3511 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3512 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3513 "ATC_GPA_MULTIPLE_HITS\n");
3514 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3515 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3516 "ATC_RCPL_TO_EMPTY_CNT\n");
3517 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3518 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3519 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3520 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3521 "ATC_IREQ_LESS_THAN_STU\n");
3522 }
3523
3524 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3525 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3526 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3527 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3528 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3529 }
3530
3531}
3532
2463static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 3533static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2464{ 3534{
2465 struct attn_route attn, *group_mask; 3535 struct attn_route attn, *group_mask;
@@ -2473,7 +3543,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2473 try to handle this event */ 3543 try to handle this event */
2474 bnx2x_acquire_alr(bp); 3544 bnx2x_acquire_alr(bp);
2475 3545
2476 if (bnx2x_chk_parity_attn(bp)) { 3546 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
2477 bp->recovery_state = BNX2X_RECOVERY_INIT; 3547 bp->recovery_state = BNX2X_RECOVERY_INIT;
2478 bnx2x_set_reset_in_progress(bp); 3548 bnx2x_set_reset_in_progress(bp);
2479 schedule_delayed_work(&bp->reset_task, 0); 3549 schedule_delayed_work(&bp->reset_task, 0);
@@ -2490,17 +3560,28 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2490 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 3560 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2491 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 3561 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2492 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 3562 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2493 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n", 3563 if (CHIP_IS_E2(bp))
2494 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]); 3564 attn.sig[4] =
3565 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3566 else
3567 attn.sig[4] = 0;
3568
3569 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3570 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
2495 3571
2496 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 3572 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2497 if (deasserted & (1 << index)) { 3573 if (deasserted & (1 << index)) {
2498 group_mask = &bp->attn_group[index]; 3574 group_mask = &bp->attn_group[index];
2499 3575
2500 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n", 3576 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
2501 index, group_mask->sig[0], group_mask->sig[1], 3577 "%08x %08x %08x\n",
2502 group_mask->sig[2], group_mask->sig[3]); 3578 index,
3579 group_mask->sig[0], group_mask->sig[1],
3580 group_mask->sig[2], group_mask->sig[3],
3581 group_mask->sig[4]);
2503 3582
3583 bnx2x_attn_int_deasserted4(bp,
3584 attn.sig[4] & group_mask->sig[4]);
2504 bnx2x_attn_int_deasserted3(bp, 3585 bnx2x_attn_int_deasserted3(bp,
2505 attn.sig[3] & group_mask->sig[3]); 3586 attn.sig[3] & group_mask->sig[3]);
2506 bnx2x_attn_int_deasserted1(bp, 3587 bnx2x_attn_int_deasserted1(bp,
@@ -2514,11 +3595,15 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2514 3595
2515 bnx2x_release_alr(bp); 3596 bnx2x_release_alr(bp);
2516 3597
2517 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR); 3598 if (bp->common.int_block == INT_BLOCK_HC)
3599 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3600 COMMAND_REG_ATTN_BITS_CLR);
3601 else
3602 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
2518 3603
2519 val = ~deasserted; 3604 val = ~deasserted;
2520 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n", 3605 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
2521 val, reg_addr); 3606 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2522 REG_WR(bp, reg_addr, val); 3607 REG_WR(bp, reg_addr, val);
2523 3608
2524 if (~bp->attn_state & deasserted) 3609 if (~bp->attn_state & deasserted)
@@ -2571,6 +3656,156 @@ static void bnx2x_attn_int(struct bnx2x *bp)
2571 bnx2x_attn_int_deasserted(bp, deasserted); 3656 bnx2x_attn_int_deasserted(bp, deasserted);
2572} 3657}
2573 3658
3659static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3660{
3661 /* No memory barriers */
3662 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3663 mmiowb(); /* keep prod updates ordered */
3664}
3665
3666#ifdef BCM_CNIC
3667static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3668 union event_ring_elem *elem)
3669{
3670 if (!bp->cnic_eth_dev.starting_cid ||
3671 (cid < bp->cnic_eth_dev.starting_cid &&
3672 cid != bp->cnic_eth_dev.iscsi_l2_cid))
3673 return 1;
3674
3675 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3676
3677 if (unlikely(elem->message.data.cfc_del_event.error)) {
3678 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3679 cid);
3680 bnx2x_panic_dump(bp);
3681 }
3682 bnx2x_cnic_cfc_comp(bp, cid);
3683 return 0;
3684}
3685#endif
3686
3687static void bnx2x_eq_int(struct bnx2x *bp)
3688{
3689 u16 hw_cons, sw_cons, sw_prod;
3690 union event_ring_elem *elem;
3691 u32 cid;
3692 u8 opcode;
3693 int spqe_cnt = 0;
3694
3695 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3696
3697 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3698 * when we get the the next-page we nned to adjust so the loop
3699 * condition below will be met. The next element is the size of a
3700 * regular element and hence incrementing by 1
3701 */
3702 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3703 hw_cons++;
3704
3705 /* This function may never run in parallel with itself for a
3706 * specific bp, thus there is no need in "paired" read memory
3707 * barrier here.
3708 */
3709 sw_cons = bp->eq_cons;
3710 sw_prod = bp->eq_prod;
3711
3712 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
3713 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
3714
3715 for (; sw_cons != hw_cons;
3716 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3717
3718
3719 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3720
3721 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3722 opcode = elem->message.opcode;
3723
3724
3725 /* handle eq element */
3726 switch (opcode) {
3727 case EVENT_RING_OPCODE_STAT_QUERY:
3728 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3729 /* nothing to do with stats comp */
3730 continue;
3731
3732 case EVENT_RING_OPCODE_CFC_DEL:
3733 /* handle according to cid range */
3734 /*
3735 * we may want to verify here that the bp state is
3736 * HALTING
3737 */
3738 DP(NETIF_MSG_IFDOWN,
3739 "got delete ramrod for MULTI[%d]\n", cid);
3740#ifdef BCM_CNIC
3741 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3742 goto next_spqe;
3743 if (cid == BNX2X_FCOE_ETH_CID)
3744 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3745 else
3746#endif
3747 bnx2x_fp(bp, cid, state) =
3748 BNX2X_FP_STATE_CLOSED;
3749
3750 goto next_spqe;
3751
3752 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3753 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3754 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3755 goto next_spqe;
3756 case EVENT_RING_OPCODE_START_TRAFFIC:
3757 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3758 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3759 goto next_spqe;
3760 }
3761
3762 switch (opcode | bp->state) {
3763 case (EVENT_RING_OPCODE_FUNCTION_START |
3764 BNX2X_STATE_OPENING_WAIT4_PORT):
3765 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3766 bp->state = BNX2X_STATE_FUNC_STARTED;
3767 break;
3768
3769 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3770 BNX2X_STATE_CLOSING_WAIT4_HALT):
3771 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3772 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3773 break;
3774
3775 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3776 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3777 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3778 if (elem->message.data.set_mac_event.echo)
3779 bp->set_mac_pending = 0;
3780 break;
3781
3782 case (EVENT_RING_OPCODE_SET_MAC |
3783 BNX2X_STATE_CLOSING_WAIT4_HALT):
3784 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3785 if (elem->message.data.set_mac_event.echo)
3786 bp->set_mac_pending = 0;
3787 break;
3788 default:
3789 /* unknown event log error and continue */
3790 BNX2X_ERR("Unknown EQ event %d\n",
3791 elem->message.opcode);
3792 }
3793next_spqe:
3794 spqe_cnt++;
3795 } /* for */
3796
3797 smp_mb__before_atomic_inc();
3798 atomic_add(spqe_cnt, &bp->eq_spq_left);
3799
3800 bp->eq_cons = sw_cons;
3801 bp->eq_prod = sw_prod;
3802 /* Make sure that above mem writes were issued towards the memory */
3803 smp_wmb();
3804
3805 /* update producer */
3806 bnx2x_update_eq_prod(bp, bp->eq_prod);
3807}
3808
2574static void bnx2x_sp_task(struct work_struct *work) 3809static void bnx2x_sp_task(struct work_struct *work)
2575{ 3810{
2576 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 3811 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
@@ -2589,31 +3824,35 @@ static void bnx2x_sp_task(struct work_struct *work)
2589 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 3824 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
2590 3825
2591 /* HW attentions */ 3826 /* HW attentions */
2592 if (status & 0x1) { 3827 if (status & BNX2X_DEF_SB_ATT_IDX) {
2593 bnx2x_attn_int(bp); 3828 bnx2x_attn_int(bp);
2594 status &= ~0x1; 3829 status &= ~BNX2X_DEF_SB_ATT_IDX;
2595 } 3830 }
2596 3831
2597 /* CStorm events: STAT_QUERY */ 3832 /* SP events: STAT_QUERY and others */
2598 if (status & 0x2) { 3833 if (status & BNX2X_DEF_SB_IDX) {
2599 DP(BNX2X_MSG_SP, "CStorm events: STAT_QUERY\n"); 3834#ifdef BCM_CNIC
2600 status &= ~0x2; 3835 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
3836
3837 if ((!NO_FCOE(bp)) &&
3838 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3839 napi_schedule(&bnx2x_fcoe(bp, napi));
3840#endif
3841 /* Handle EQ completions */
3842 bnx2x_eq_int(bp);
3843
3844 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3845 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3846
3847 status &= ~BNX2X_DEF_SB_IDX;
2601 } 3848 }
2602 3849
2603 if (unlikely(status)) 3850 if (unlikely(status))
2604 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 3851 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
2605 status); 3852 status);
2606 3853
2607 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx), 3854 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
2608 IGU_INT_NOP, 1); 3855 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
2609 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2610 IGU_INT_NOP, 1);
2611 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2612 IGU_INT_NOP, 1);
2613 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2614 IGU_INT_NOP, 1);
2615 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2616 IGU_INT_ENABLE, 1);
2617} 3856}
2618 3857
2619irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 3858irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
@@ -2627,7 +3866,8 @@ irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2627 return IRQ_HANDLED; 3866 return IRQ_HANDLED;
2628 } 3867 }
2629 3868
2630 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0); 3869 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3870 IGU_INT_DISABLE, 0);
2631 3871
2632#ifdef BNX2X_STOP_ON_ERROR 3872#ifdef BNX2X_STOP_ON_ERROR
2633 if (unlikely(bp->panic)) 3873 if (unlikely(bp->panic))
@@ -2664,14 +3904,13 @@ static void bnx2x_timer(unsigned long data)
2664 3904
2665 if (poll) { 3905 if (poll) {
2666 struct bnx2x_fastpath *fp = &bp->fp[0]; 3906 struct bnx2x_fastpath *fp = &bp->fp[0];
2667 int rc;
2668 3907
2669 bnx2x_tx_int(fp); 3908 bnx2x_tx_int(fp);
2670 rc = bnx2x_rx_int(fp, 1000); 3909 bnx2x_rx_int(fp, 1000);
2671 } 3910 }
2672 3911
2673 if (!BP_NOMCP(bp)) { 3912 if (!BP_NOMCP(bp)) {
2674 int func = BP_FUNC(bp); 3913 int mb_idx = BP_FW_MB_IDX(bp);
2675 u32 drv_pulse; 3914 u32 drv_pulse;
2676 u32 mcp_pulse; 3915 u32 mcp_pulse;
2677 3916
@@ -2679,9 +3918,9 @@ static void bnx2x_timer(unsigned long data)
2679 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 3918 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
2680 /* TBD - add SYSTEM_TIME */ 3919 /* TBD - add SYSTEM_TIME */
2681 drv_pulse = bp->fw_drv_pulse_wr_seq; 3920 drv_pulse = bp->fw_drv_pulse_wr_seq;
2682 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse); 3921 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
2683 3922
2684 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) & 3923 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
2685 MCP_PULSE_SEQ_MASK); 3924 MCP_PULSE_SEQ_MASK);
2686 /* The delta between driver pulse and mcp response 3925 /* The delta between driver pulse and mcp response
2687 * should be 1 (before mcp response) or 0 (after mcp response) 3926 * should be 1 (before mcp response) or 0 (after mcp response)
@@ -2709,327 +3948,313 @@ timer_restart:
2709 * nic init service functions 3948 * nic init service functions
2710 */ 3949 */
2711 3950
2712static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id) 3951static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
2713{ 3952{
2714 int port = BP_PORT(bp); 3953 u32 i;
3954 if (!(len%4) && !(addr%4))
3955 for (i = 0; i < len; i += 4)
3956 REG_WR(bp, addr + i, fill);
3957 else
3958 for (i = 0; i < len; i++)
3959 REG_WR8(bp, addr + i, fill);
2715 3960
2716 /* "CSTORM" */
2717 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
2718 CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0,
2719 CSTORM_SB_STATUS_BLOCK_U_SIZE / 4);
2720 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
2721 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0,
2722 CSTORM_SB_STATUS_BLOCK_C_SIZE / 4);
2723} 3961}
2724 3962
2725void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb, 3963/* helper: writes FP SP data to FW - data_size in dwords */
2726 dma_addr_t mapping, int sb_id) 3964static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3965 int fw_sb_id,
3966 u32 *sb_data_p,
3967 u32 data_size)
2727{ 3968{
2728 int port = BP_PORT(bp);
2729 int func = BP_FUNC(bp);
2730 int index; 3969 int index;
2731 u64 section; 3970 for (index = 0; index < data_size; index++)
3971 REG_WR(bp, BAR_CSTRORM_INTMEM +
3972 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3973 sizeof(u32)*index,
3974 *(sb_data_p + index));
3975}
3976
3977static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3978{
3979 u32 *sb_data_p;
3980 u32 data_size = 0;
3981 struct hc_status_block_data_e2 sb_data_e2;
3982 struct hc_status_block_data_e1x sb_data_e1x;
3983
3984 /* disable the function first */
3985 if (CHIP_IS_E2(bp)) {
3986 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3987 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3988 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3989 sb_data_e2.common.p_func.vf_valid = false;
3990 sb_data_p = (u32 *)&sb_data_e2;
3991 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3992 } else {
3993 memset(&sb_data_e1x, 0,
3994 sizeof(struct hc_status_block_data_e1x));
3995 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3996 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3997 sb_data_e1x.common.p_func.vf_valid = false;
3998 sb_data_p = (u32 *)&sb_data_e1x;
3999 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4000 }
4001 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
2732 4002
2733 /* USTORM */ 4003 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
2734 section = ((u64)mapping) + offsetof(struct host_status_block, 4004 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
2735 u_status_block); 4005 CSTORM_STATUS_BLOCK_SIZE);
2736 sb->u_status_block.status_block_id = sb_id; 4006 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
2737 4007 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
2738 REG_WR(bp, BAR_CSTRORM_INTMEM + 4008 CSTORM_SYNC_BLOCK_SIZE);
2739 CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section)); 4009}
2740 REG_WR(bp, BAR_CSTRORM_INTMEM +
2741 ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4),
2742 U64_HI(section));
2743 REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_USB_FUNC_OFF +
2744 CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func);
2745
2746 for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
2747 REG_WR16(bp, BAR_CSTRORM_INTMEM +
2748 CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 1);
2749 4010
2750 /* CSTORM */ 4011/* helper: writes SP SB data to FW */
2751 section = ((u64)mapping) + offsetof(struct host_status_block, 4012static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
2752 c_status_block); 4013 struct hc_sp_status_block_data *sp_sb_data)
2753 sb->c_status_block.status_block_id = sb_id; 4014{
4015 int func = BP_FUNC(bp);
4016 int i;
4017 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4018 REG_WR(bp, BAR_CSTRORM_INTMEM +
4019 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4020 i*sizeof(u32),
4021 *((u32 *)sp_sb_data + i));
4022}
4023
4024static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4025{
4026 int func = BP_FUNC(bp);
4027 struct hc_sp_status_block_data sp_sb_data;
4028 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4029
4030 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4031 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4032 sp_sb_data.p_func.vf_valid = false;
2754 4033
2755 REG_WR(bp, BAR_CSTRORM_INTMEM + 4034 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
2756 CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section));
2757 REG_WR(bp, BAR_CSTRORM_INTMEM +
2758 ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4),
2759 U64_HI(section));
2760 REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
2761 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func);
2762 4035
2763 for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++) 4036 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
2764 REG_WR16(bp, BAR_CSTRORM_INTMEM + 4037 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
2765 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 1); 4038 CSTORM_SP_STATUS_BLOCK_SIZE);
4039 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4040 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4041 CSTORM_SP_SYNC_BLOCK_SIZE);
2766 4042
2767 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
2768} 4043}
2769 4044
2770static void bnx2x_zero_def_sb(struct bnx2x *bp) 4045
4046static inline
4047void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4048 int igu_sb_id, int igu_seg_id)
2771{ 4049{
2772 int func = BP_FUNC(bp); 4050 hc_sm->igu_sb_id = igu_sb_id;
4051 hc_sm->igu_seg_id = igu_seg_id;
4052 hc_sm->timer_value = 0xFF;
4053 hc_sm->time_to_expire = 0xFFFFFFFF;
4054}
4055
4056static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4057 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4058{
4059 int igu_seg_id;
4060
4061 struct hc_status_block_data_e2 sb_data_e2;
4062 struct hc_status_block_data_e1x sb_data_e1x;
4063 struct hc_status_block_sm *hc_sm_p;
4064 int data_size;
4065 u32 *sb_data_p;
4066
4067 if (CHIP_INT_MODE_IS_BC(bp))
4068 igu_seg_id = HC_SEG_ACCESS_NORM;
4069 else
4070 igu_seg_id = IGU_SEG_ACCESS_NORM;
4071
4072 bnx2x_zero_fp_sb(bp, fw_sb_id);
4073
4074 if (CHIP_IS_E2(bp)) {
4075 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4076 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4077 sb_data_e2.common.p_func.vf_id = vfid;
4078 sb_data_e2.common.p_func.vf_valid = vf_valid;
4079 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4080 sb_data_e2.common.same_igu_sb_1b = true;
4081 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4082 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4083 hc_sm_p = sb_data_e2.common.state_machine;
4084 sb_data_p = (u32 *)&sb_data_e2;
4085 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4086 } else {
4087 memset(&sb_data_e1x, 0,
4088 sizeof(struct hc_status_block_data_e1x));
4089 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4090 sb_data_e1x.common.p_func.vf_id = 0xff;
4091 sb_data_e1x.common.p_func.vf_valid = false;
4092 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4093 sb_data_e1x.common.same_igu_sb_1b = true;
4094 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4095 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4096 hc_sm_p = sb_data_e1x.common.state_machine;
4097 sb_data_p = (u32 *)&sb_data_e1x;
4098 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4099 }
4100
4101 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4102 igu_sb_id, igu_seg_id);
4103 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4104 igu_sb_id, igu_seg_id);
2773 4105
2774 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY + 4106 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
2775 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, 4107
2776 sizeof(struct tstorm_def_status_block)/4); 4108 /* write indecies to HW */
2777 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY + 4109 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
2778 CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0,
2779 sizeof(struct cstorm_def_status_block_u)/4);
2780 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
2781 CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0,
2782 sizeof(struct cstorm_def_status_block_c)/4);
2783 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY +
2784 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
2785 sizeof(struct xstorm_def_status_block)/4);
2786} 4110}
2787 4111
2788static void bnx2x_init_def_sb(struct bnx2x *bp, 4112static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
2789 struct host_def_status_block *def_sb, 4113 u8 sb_index, u8 disable, u16 usec)
2790 dma_addr_t mapping, int sb_id)
2791{ 4114{
2792 int port = BP_PORT(bp); 4115 int port = BP_PORT(bp);
4116 u8 ticks = usec / BNX2X_BTR;
4117
4118 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4119
4120 disable = disable ? 1 : (usec ? 0 : 1);
4121 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4122}
4123
4124static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4125 u16 tx_usec, u16 rx_usec)
4126{
4127 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4128 false, rx_usec);
4129 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4130 false, tx_usec);
4131}
4132
4133static void bnx2x_init_def_sb(struct bnx2x *bp)
4134{
4135 struct host_sp_status_block *def_sb = bp->def_status_blk;
4136 dma_addr_t mapping = bp->def_status_blk_mapping;
4137 int igu_sp_sb_index;
4138 int igu_seg_id;
4139 int port = BP_PORT(bp);
2793 int func = BP_FUNC(bp); 4140 int func = BP_FUNC(bp);
2794 int index, val, reg_offset; 4141 int reg_offset;
2795 u64 section; 4142 u64 section;
4143 int index;
4144 struct hc_sp_status_block_data sp_sb_data;
4145 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4146
4147 if (CHIP_INT_MODE_IS_BC(bp)) {
4148 igu_sp_sb_index = DEF_SB_IGU_ID;
4149 igu_seg_id = HC_SEG_ACCESS_DEF;
4150 } else {
4151 igu_sp_sb_index = bp->igu_dsb_id;
4152 igu_seg_id = IGU_SEG_ACCESS_DEF;
4153 }
2796 4154
2797 /* ATTN */ 4155 /* ATTN */
2798 section = ((u64)mapping) + offsetof(struct host_def_status_block, 4156 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
2799 atten_status_block); 4157 atten_status_block);
2800 def_sb->atten_status_block.status_block_id = sb_id; 4158 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
2801 4159
2802 bp->attn_state = 0; 4160 bp->attn_state = 0;
2803 4161
2804 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4162 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2805 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 4163 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2806
2807 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 4164 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2808 bp->attn_group[index].sig[0] = REG_RD(bp, 4165 int sindex;
2809 reg_offset + 0x10*index); 4166 /* take care of sig[0]..sig[4] */
2810 bp->attn_group[index].sig[1] = REG_RD(bp, 4167 for (sindex = 0; sindex < 4; sindex++)
2811 reg_offset + 0x4 + 0x10*index); 4168 bp->attn_group[index].sig[sindex] =
2812 bp->attn_group[index].sig[2] = REG_RD(bp, 4169 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
2813 reg_offset + 0x8 + 0x10*index); 4170
2814 bp->attn_group[index].sig[3] = REG_RD(bp, 4171 if (CHIP_IS_E2(bp))
2815 reg_offset + 0xc + 0x10*index); 4172 /*
4173 * enable5 is separate from the rest of the registers,
4174 * and therefore the address skip is 4
4175 * and not 16 between the different groups
4176 */
4177 bp->attn_group[index].sig[4] = REG_RD(bp,
4178 reg_offset + 0x10 + 0x4*index);
4179 else
4180 bp->attn_group[index].sig[4] = 0;
2816 } 4181 }
2817 4182
2818 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 4183 if (bp->common.int_block == INT_BLOCK_HC) {
2819 HC_REG_ATTN_MSG0_ADDR_L); 4184 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4185 HC_REG_ATTN_MSG0_ADDR_L);
2820 4186
2821 REG_WR(bp, reg_offset, U64_LO(section)); 4187 REG_WR(bp, reg_offset, U64_LO(section));
2822 REG_WR(bp, reg_offset + 4, U64_HI(section)); 4188 REG_WR(bp, reg_offset + 4, U64_HI(section));
4189 } else if (CHIP_IS_E2(bp)) {
4190 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4191 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4192 }
2823 4193
2824 reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0); 4194 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4195 sp_sb);
2825 4196
2826 val = REG_RD(bp, reg_offset); 4197 bnx2x_zero_sp_sb(bp);
2827 val |= sb_id;
2828 REG_WR(bp, reg_offset, val);
2829 4198
2830 /* USTORM */ 4199 sp_sb_data.host_sb_addr.lo = U64_LO(section);
2831 section = ((u64)mapping) + offsetof(struct host_def_status_block, 4200 sp_sb_data.host_sb_addr.hi = U64_HI(section);
2832 u_def_status_block); 4201 sp_sb_data.igu_sb_id = igu_sp_sb_index;
2833 def_sb->u_def_status_block.status_block_id = sb_id; 4202 sp_sb_data.igu_seg_id = igu_seg_id;
2834 4203 sp_sb_data.p_func.pf_id = func;
2835 REG_WR(bp, BAR_CSTRORM_INTMEM + 4204 sp_sb_data.p_func.vnic_id = BP_VN(bp);
2836 CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section)); 4205 sp_sb_data.p_func.vf_id = 0xff;
2837 REG_WR(bp, BAR_CSTRORM_INTMEM +
2838 ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4),
2839 U64_HI(section));
2840 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_USB_FUNC_OFF +
2841 CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func);
2842
2843 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
2844 REG_WR16(bp, BAR_CSTRORM_INTMEM +
2845 CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1);
2846 4206
2847 /* CSTORM */ 4207 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
2848 section = ((u64)mapping) + offsetof(struct host_def_status_block,
2849 c_def_status_block);
2850 def_sb->c_def_status_block.status_block_id = sb_id;
2851
2852 REG_WR(bp, BAR_CSTRORM_INTMEM +
2853 CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section));
2854 REG_WR(bp, BAR_CSTRORM_INTMEM +
2855 ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4),
2856 U64_HI(section));
2857 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
2858 CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func);
2859
2860 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
2861 REG_WR16(bp, BAR_CSTRORM_INTMEM +
2862 CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1);
2863
2864 /* TSTORM */
2865 section = ((u64)mapping) + offsetof(struct host_def_status_block,
2866 t_def_status_block);
2867 def_sb->t_def_status_block.status_block_id = sb_id;
2868
2869 REG_WR(bp, BAR_TSTRORM_INTMEM +
2870 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
2871 REG_WR(bp, BAR_TSTRORM_INTMEM +
2872 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
2873 U64_HI(section));
2874 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
2875 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
2876
2877 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
2878 REG_WR16(bp, BAR_TSTRORM_INTMEM +
2879 TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
2880
2881 /* XSTORM */
2882 section = ((u64)mapping) + offsetof(struct host_def_status_block,
2883 x_def_status_block);
2884 def_sb->x_def_status_block.status_block_id = sb_id;
2885
2886 REG_WR(bp, BAR_XSTRORM_INTMEM +
2887 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
2888 REG_WR(bp, BAR_XSTRORM_INTMEM +
2889 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
2890 U64_HI(section));
2891 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
2892 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
2893
2894 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
2895 REG_WR16(bp, BAR_XSTRORM_INTMEM +
2896 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
2897 4208
2898 bp->stats_pending = 0; 4209 bp->stats_pending = 0;
2899 bp->set_mac_pending = 0; 4210 bp->set_mac_pending = 0;
2900 4211
2901 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); 4212 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
2902} 4213}
2903 4214
2904void bnx2x_update_coalesce(struct bnx2x *bp) 4215void bnx2x_update_coalesce(struct bnx2x *bp)
2905{ 4216{
2906 int port = BP_PORT(bp);
2907 int i; 4217 int i;
2908 4218
2909 for_each_queue(bp, i) { 4219 for_each_eth_queue(bp, i)
2910 int sb_id = bp->fp[i].sb_id; 4220 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
2911 4221 bp->tx_ticks, bp->rx_ticks);
2912 /* HC_INDEX_U_ETH_RX_CQ_CONS */
2913 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2914 CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id,
2915 U_SB_ETH_RX_CQ_INDEX),
2916 bp->rx_ticks/(4 * BNX2X_BTR));
2917 REG_WR16(bp, BAR_CSTRORM_INTMEM +
2918 CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id,
2919 U_SB_ETH_RX_CQ_INDEX),
2920 (bp->rx_ticks/(4 * BNX2X_BTR)) ? 0 : 1);
2921
2922 /* HC_INDEX_C_ETH_TX_CQ_CONS */
2923 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2924 CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
2925 C_SB_ETH_TX_CQ_INDEX),
2926 bp->tx_ticks/(4 * BNX2X_BTR));
2927 REG_WR16(bp, BAR_CSTRORM_INTMEM +
2928 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
2929 C_SB_ETH_TX_CQ_INDEX),
2930 (bp->tx_ticks/(4 * BNX2X_BTR)) ? 0 : 1);
2931 }
2932} 4222}
2933 4223
2934static void bnx2x_init_sp_ring(struct bnx2x *bp) 4224static void bnx2x_init_sp_ring(struct bnx2x *bp)
2935{ 4225{
2936 int func = BP_FUNC(bp);
2937
2938 spin_lock_init(&bp->spq_lock); 4226 spin_lock_init(&bp->spq_lock);
4227 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
2939 4228
2940 bp->spq_left = MAX_SPQ_PENDING;
2941 bp->spq_prod_idx = 0; 4229 bp->spq_prod_idx = 0;
2942 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 4230 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
2943 bp->spq_prod_bd = bp->spq; 4231 bp->spq_prod_bd = bp->spq;
2944 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 4232 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
2945
2946 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
2947 U64_LO(bp->spq_mapping));
2948 REG_WR(bp,
2949 XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
2950 U64_HI(bp->spq_mapping));
2951
2952 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
2953 bp->spq_prod_idx);
2954} 4233}
2955 4234
2956static void bnx2x_init_context(struct bnx2x *bp) 4235static void bnx2x_init_eq_ring(struct bnx2x *bp)
2957{ 4236{
2958 int i; 4237 int i;
4238 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4239 union event_ring_elem *elem =
4240 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
2959 4241
2960 /* Rx */ 4242 elem->next_page.addr.hi =
2961 for_each_queue(bp, i) { 4243 cpu_to_le32(U64_HI(bp->eq_mapping +
2962 struct eth_context *context = bnx2x_sp(bp, context[i].eth); 4244 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
2963 struct bnx2x_fastpath *fp = &bp->fp[i]; 4245 elem->next_page.addr.lo =
2964 u8 cl_id = fp->cl_id; 4246 cpu_to_le32(U64_LO(bp->eq_mapping +
2965 4247 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
2966 context->ustorm_st_context.common.sb_index_numbers =
2967 BNX2X_RX_SB_INDEX_NUM;
2968 context->ustorm_st_context.common.clientId = cl_id;
2969 context->ustorm_st_context.common.status_block_id = fp->sb_id;
2970 context->ustorm_st_context.common.flags =
2971 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
2972 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
2973 context->ustorm_st_context.common.statistics_counter_id =
2974 cl_id;
2975 context->ustorm_st_context.common.mc_alignment_log_size =
2976 BNX2X_RX_ALIGN_SHIFT;
2977 context->ustorm_st_context.common.bd_buff_size =
2978 bp->rx_buf_size;
2979 context->ustorm_st_context.common.bd_page_base_hi =
2980 U64_HI(fp->rx_desc_mapping);
2981 context->ustorm_st_context.common.bd_page_base_lo =
2982 U64_LO(fp->rx_desc_mapping);
2983 if (!fp->disable_tpa) {
2984 context->ustorm_st_context.common.flags |=
2985 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA;
2986 context->ustorm_st_context.common.sge_buff_size =
2987 (u16)min_t(u32, SGE_PAGE_SIZE*PAGES_PER_SGE,
2988 0xffff);
2989 context->ustorm_st_context.common.sge_page_base_hi =
2990 U64_HI(fp->rx_sge_mapping);
2991 context->ustorm_st_context.common.sge_page_base_lo =
2992 U64_LO(fp->rx_sge_mapping);
2993
2994 context->ustorm_st_context.common.max_sges_for_packet =
2995 SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
2996 context->ustorm_st_context.common.max_sges_for_packet =
2997 ((context->ustorm_st_context.common.
2998 max_sges_for_packet + PAGES_PER_SGE - 1) &
2999 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
3000 }
3001
3002 context->ustorm_ag_context.cdu_usage =
3003 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
3004 CDU_REGION_NUMBER_UCM_AG,
3005 ETH_CONNECTION_TYPE);
3006
3007 context->xstorm_ag_context.cdu_reserved =
3008 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
3009 CDU_REGION_NUMBER_XCM_AG,
3010 ETH_CONNECTION_TYPE);
3011 }
3012
3013 /* Tx */
3014 for_each_queue(bp, i) {
3015 struct bnx2x_fastpath *fp = &bp->fp[i];
3016 struct eth_context *context =
3017 bnx2x_sp(bp, context[i].eth);
3018
3019 context->cstorm_st_context.sb_index_number =
3020 C_SB_ETH_TX_CQ_INDEX;
3021 context->cstorm_st_context.status_block_id = fp->sb_id;
3022
3023 context->xstorm_st_context.tx_bd_page_base_hi =
3024 U64_HI(fp->tx_desc_mapping);
3025 context->xstorm_st_context.tx_bd_page_base_lo =
3026 U64_LO(fp->tx_desc_mapping);
3027 context->xstorm_st_context.statistics_data = (fp->cl_id |
3028 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
3029 } 4248 }
4249 bp->eq_cons = 0;
4250 bp->eq_prod = NUM_EQ_DESC;
4251 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4252 /* we want a warning message before it gets rought... */
4253 atomic_set(&bp->eq_spq_left,
4254 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
3030} 4255}
3031 4256
3032static void bnx2x_init_ind_table(struct bnx2x *bp) 4257void bnx2x_push_indir_table(struct bnx2x *bp)
3033{ 4258{
3034 int func = BP_FUNC(bp); 4259 int func = BP_FUNC(bp);
3035 int i; 4260 int i;
@@ -3037,55 +4262,29 @@ static void bnx2x_init_ind_table(struct bnx2x *bp)
3037 if (bp->multi_mode == ETH_RSS_MODE_DISABLED) 4262 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
3038 return; 4263 return;
3039 4264
3040 DP(NETIF_MSG_IFUP,
3041 "Initializing indirection table multi_mode %d\n", bp->multi_mode);
3042 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++) 4265 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
3043 REG_WR8(bp, BAR_TSTRORM_INTMEM + 4266 REG_WR8(bp, BAR_TSTRORM_INTMEM +
3044 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i, 4267 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
3045 bp->fp->cl_id + (i % bp->num_queues)); 4268 bp->fp->cl_id + bp->rx_indir_table[i]);
3046} 4269}
3047 4270
3048void bnx2x_set_client_config(struct bnx2x *bp) 4271static void bnx2x_init_ind_table(struct bnx2x *bp)
3049{ 4272{
3050 struct tstorm_eth_client_config tstorm_client = {0};
3051 int port = BP_PORT(bp);
3052 int i; 4273 int i;
3053 4274
3054 tstorm_client.mtu = bp->dev->mtu; 4275 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
3055 tstorm_client.config_flags = 4276 bp->rx_indir_table[i] = i % BNX2X_NUM_ETH_QUEUES(bp);
3056 (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
3057 TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
3058#ifdef BCM_VLAN
3059 if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
3060 tstorm_client.config_flags |=
3061 TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
3062 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
3063 }
3064#endif
3065
3066 for_each_queue(bp, i) {
3067 tstorm_client.statistics_counter_id = bp->fp[i].cl_id;
3068
3069 REG_WR(bp, BAR_TSTRORM_INTMEM +
3070 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
3071 ((u32 *)&tstorm_client)[0]);
3072 REG_WR(bp, BAR_TSTRORM_INTMEM +
3073 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
3074 ((u32 *)&tstorm_client)[1]);
3075 }
3076 4277
3077 DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n", 4278 bnx2x_push_indir_table(bp);
3078 ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
3079} 4279}
3080 4280
3081void bnx2x_set_storm_rx_mode(struct bnx2x *bp) 4281void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
3082{ 4282{
3083 struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
3084 int mode = bp->rx_mode; 4283 int mode = bp->rx_mode;
3085 int mask = bp->rx_mode_cl_mask;
3086 int func = BP_FUNC(bp);
3087 int port = BP_PORT(bp); 4284 int port = BP_PORT(bp);
3088 int i; 4285 u16 cl_id;
4286 u32 def_q_filters = 0;
4287
3089 /* All but management unicast packets should pass to the host as well */ 4288 /* All but management unicast packets should pass to the host as well */
3090 u32 llh_mask = 4289 u32 llh_mask =
3091 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST | 4290 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
@@ -3093,28 +4292,58 @@ void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
3093 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN | 4292 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
3094 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN; 4293 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
3095 4294
3096 DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask);
3097
3098 switch (mode) { 4295 switch (mode) {
3099 case BNX2X_RX_MODE_NONE: /* no Rx */ 4296 case BNX2X_RX_MODE_NONE: /* no Rx */
3100 tstorm_mac_filter.ucast_drop_all = mask; 4297 def_q_filters = BNX2X_ACCEPT_NONE;
3101 tstorm_mac_filter.mcast_drop_all = mask; 4298#ifdef BCM_CNIC
3102 tstorm_mac_filter.bcast_drop_all = mask; 4299 if (!NO_FCOE(bp)) {
4300 cl_id = bnx2x_fcoe(bp, cl_id);
4301 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4302 }
4303#endif
3103 break; 4304 break;
3104 4305
3105 case BNX2X_RX_MODE_NORMAL: 4306 case BNX2X_RX_MODE_NORMAL:
3106 tstorm_mac_filter.bcast_accept_all = mask; 4307 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4308 BNX2X_ACCEPT_MULTICAST;
4309#ifdef BCM_CNIC
4310 if (!NO_FCOE(bp)) {
4311 cl_id = bnx2x_fcoe(bp, cl_id);
4312 bnx2x_rxq_set_mac_filters(bp, cl_id,
4313 BNX2X_ACCEPT_UNICAST |
4314 BNX2X_ACCEPT_MULTICAST);
4315 }
4316#endif
3107 break; 4317 break;
3108 4318
3109 case BNX2X_RX_MODE_ALLMULTI: 4319 case BNX2X_RX_MODE_ALLMULTI:
3110 tstorm_mac_filter.mcast_accept_all = mask; 4320 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
3111 tstorm_mac_filter.bcast_accept_all = mask; 4321 BNX2X_ACCEPT_ALL_MULTICAST;
4322#ifdef BCM_CNIC
4323 /*
4324 * Prevent duplication of multicast packets by configuring FCoE
4325 * L2 Client to receive only matched unicast frames.
4326 */
4327 if (!NO_FCOE(bp)) {
4328 cl_id = bnx2x_fcoe(bp, cl_id);
4329 bnx2x_rxq_set_mac_filters(bp, cl_id,
4330 BNX2X_ACCEPT_UNICAST);
4331 }
4332#endif
3112 break; 4333 break;
3113 4334
3114 case BNX2X_RX_MODE_PROMISC: 4335 case BNX2X_RX_MODE_PROMISC:
3115 tstorm_mac_filter.ucast_accept_all = mask; 4336 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
3116 tstorm_mac_filter.mcast_accept_all = mask; 4337#ifdef BCM_CNIC
3117 tstorm_mac_filter.bcast_accept_all = mask; 4338 /*
4339 * Prevent packets duplication by configuring DROP_ALL for FCoE
4340 * L2 Client.
4341 */
4342 if (!NO_FCOE(bp)) {
4343 cl_id = bnx2x_fcoe(bp, cl_id);
4344 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4345 }
4346#endif
3118 /* pass management unicast packets as well */ 4347 /* pass management unicast packets as well */
3119 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST; 4348 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
3120 break; 4349 break;
@@ -3124,263 +4353,79 @@ void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
3124 break; 4353 break;
3125 } 4354 }
3126 4355
3127 REG_WR(bp, 4356 cl_id = BP_L_ID(bp);
3128 (port ? NIG_REG_LLH1_BRB1_DRV_MASK : NIG_REG_LLH0_BRB1_DRV_MASK), 4357 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
3129 llh_mask);
3130 4358
3131 for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) { 4359 REG_WR(bp,
3132 REG_WR(bp, BAR_TSTRORM_INTMEM + 4360 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
3133 TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4, 4361 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
3134 ((u32 *)&tstorm_mac_filter)[i]);
3135 4362
3136/* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i, 4363 DP(NETIF_MSG_IFUP, "rx mode %d\n"
3137 ((u32 *)&tstorm_mac_filter)[i]); */ 4364 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
3138 } 4365 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4366 "unmatched_ucast 0x%x\n", mode,
4367 bp->mac_filters.ucast_drop_all,
4368 bp->mac_filters.mcast_drop_all,
4369 bp->mac_filters.bcast_drop_all,
4370 bp->mac_filters.ucast_accept_all,
4371 bp->mac_filters.mcast_accept_all,
4372 bp->mac_filters.bcast_accept_all,
4373 bp->mac_filters.unmatched_unicast
4374 );
3139 4375
3140 if (mode != BNX2X_RX_MODE_NONE) 4376 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
3141 bnx2x_set_client_config(bp);
3142} 4377}
3143 4378
3144static void bnx2x_init_internal_common(struct bnx2x *bp) 4379static void bnx2x_init_internal_common(struct bnx2x *bp)
3145{ 4380{
3146 int i; 4381 int i;
3147 4382
3148 /* Zero this manually as its initialization is 4383 if (!CHIP_IS_E1(bp)) {
3149 currently missing in the initTool */
3150 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
3151 REG_WR(bp, BAR_USTRORM_INTMEM +
3152 USTORM_AGG_DATA_OFFSET + i * 4, 0);
3153}
3154
3155static void bnx2x_init_internal_port(struct bnx2x *bp)
3156{
3157 int port = BP_PORT(bp);
3158
3159 REG_WR(bp,
3160 BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BNX2X_BTR);
3161 REG_WR(bp,
3162 BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BNX2X_BTR);
3163 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
3164 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
3165}
3166
3167static void bnx2x_init_internal_func(struct bnx2x *bp)
3168{
3169 struct tstorm_eth_function_common_config tstorm_config = {0};
3170 struct stats_indication_flags stats_flags = {0};
3171 int port = BP_PORT(bp);
3172 int func = BP_FUNC(bp);
3173 int i, j;
3174 u32 offset;
3175 u16 max_agg_size;
3176
3177 tstorm_config.config_flags = RSS_FLAGS(bp);
3178
3179 if (is_multi(bp))
3180 tstorm_config.rss_result_mask = MULTI_MASK;
3181
3182 /* Enable TPA if needed */
3183 if (bp->flags & TPA_ENABLE_FLAG)
3184 tstorm_config.config_flags |=
3185 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
3186
3187 if (IS_E1HMF(bp))
3188 tstorm_config.config_flags |=
3189 TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
3190
3191 tstorm_config.leading_client_id = BP_L_ID(bp);
3192
3193 REG_WR(bp, BAR_TSTRORM_INTMEM +
3194 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
3195 (*(u32 *)&tstorm_config));
3196
3197 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
3198 bp->rx_mode_cl_mask = (1 << BP_L_ID(bp));
3199 bnx2x_set_storm_rx_mode(bp);
3200 4384
3201 for_each_queue(bp, i) { 4385 /* xstorm needs to know whether to add ovlan to packets or not,
3202 u8 cl_id = bp->fp[i].cl_id; 4386 * in switch-independent we'll write 0 to here... */
3203
3204 /* reset xstorm per client statistics */
3205 offset = BAR_XSTRORM_INTMEM +
3206 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
3207 for (j = 0;
3208 j < sizeof(struct xstorm_per_client_stats) / 4; j++)
3209 REG_WR(bp, offset + j*4, 0);
3210
3211 /* reset tstorm per client statistics */
3212 offset = BAR_TSTRORM_INTMEM +
3213 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
3214 for (j = 0;
3215 j < sizeof(struct tstorm_per_client_stats) / 4; j++)
3216 REG_WR(bp, offset + j*4, 0);
3217
3218 /* reset ustorm per client statistics */
3219 offset = BAR_USTRORM_INTMEM +
3220 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
3221 for (j = 0;
3222 j < sizeof(struct ustorm_per_client_stats) / 4; j++)
3223 REG_WR(bp, offset + j*4, 0);
3224 }
3225
3226 /* Init statistics related context */
3227 stats_flags.collect_eth = 1;
3228
3229 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
3230 ((u32 *)&stats_flags)[0]);
3231 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
3232 ((u32 *)&stats_flags)[1]);
3233
3234 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
3235 ((u32 *)&stats_flags)[0]);
3236 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
3237 ((u32 *)&stats_flags)[1]);
3238
3239 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
3240 ((u32 *)&stats_flags)[0]);
3241 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
3242 ((u32 *)&stats_flags)[1]);
3243
3244 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
3245 ((u32 *)&stats_flags)[0]);
3246 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
3247 ((u32 *)&stats_flags)[1]);
3248
3249 REG_WR(bp, BAR_XSTRORM_INTMEM +
3250 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
3251 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
3252 REG_WR(bp, BAR_XSTRORM_INTMEM +
3253 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
3254 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
3255
3256 REG_WR(bp, BAR_TSTRORM_INTMEM +
3257 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
3258 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
3259 REG_WR(bp, BAR_TSTRORM_INTMEM +
3260 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
3261 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
3262
3263 REG_WR(bp, BAR_USTRORM_INTMEM +
3264 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
3265 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
3266 REG_WR(bp, BAR_USTRORM_INTMEM +
3267 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
3268 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
3269
3270 if (CHIP_IS_E1H(bp)) {
3271 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET, 4387 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
3272 IS_E1HMF(bp)); 4388 bp->mf_mode);
3273 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET, 4389 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
3274 IS_E1HMF(bp)); 4390 bp->mf_mode);
3275 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET, 4391 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
3276 IS_E1HMF(bp)); 4392 bp->mf_mode);
3277 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET, 4393 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
3278 IS_E1HMF(bp)); 4394 bp->mf_mode);
3279
3280 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
3281 bp->e1hov);
3282 } 4395 }
3283 4396
3284 /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */ 4397 if (IS_MF_SI(bp))
3285 max_agg_size = min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * 4398 /*
3286 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); 4399 * In switch independent mode, the TSTORM needs to accept
3287 for_each_queue(bp, i) { 4400 * packets that failed classification, since approximate match
3288 struct bnx2x_fastpath *fp = &bp->fp[i]; 4401 * mac addresses aren't written to NIG LLH
3289 4402 */
3290 REG_WR(bp, BAR_USTRORM_INTMEM + 4403 REG_WR8(bp, BAR_TSTRORM_INTMEM +
3291 USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id), 4404 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
3292 U64_LO(fp->rx_comp_mapping));
3293 REG_WR(bp, BAR_USTRORM_INTMEM +
3294 USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
3295 U64_HI(fp->rx_comp_mapping));
3296 4405
3297 /* Next page */ 4406 /* Zero this manually as its initialization is
3298 REG_WR(bp, BAR_USTRORM_INTMEM + 4407 currently missing in the initTool */
3299 USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id), 4408 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
3300 U64_LO(fp->rx_comp_mapping + BCM_PAGE_SIZE));
3301 REG_WR(bp, BAR_USTRORM_INTMEM + 4409 REG_WR(bp, BAR_USTRORM_INTMEM +
3302 USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id) + 4, 4410 USTORM_AGG_DATA_OFFSET + i * 4, 0);
3303 U64_HI(fp->rx_comp_mapping + BCM_PAGE_SIZE)); 4411 if (CHIP_IS_E2(bp)) {
3304 4412 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
3305 REG_WR16(bp, BAR_USTRORM_INTMEM + 4413 CHIP_INT_MODE_IS_BC(bp) ?
3306 USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id), 4414 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
3307 max_agg_size);
3308 }
3309
3310 /* dropless flow control */
3311 if (CHIP_IS_E1H(bp)) {
3312 struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
3313
3314 rx_pause.bd_thr_low = 250;
3315 rx_pause.cqe_thr_low = 250;
3316 rx_pause.cos = 1;
3317 rx_pause.sge_thr_low = 0;
3318 rx_pause.bd_thr_high = 350;
3319 rx_pause.cqe_thr_high = 350;
3320 rx_pause.sge_thr_high = 0;
3321
3322 for_each_queue(bp, i) {
3323 struct bnx2x_fastpath *fp = &bp->fp[i];
3324
3325 if (!fp->disable_tpa) {
3326 rx_pause.sge_thr_low = 150;
3327 rx_pause.sge_thr_high = 250;
3328 }
3329
3330
3331 offset = BAR_USTRORM_INTMEM +
3332 USTORM_ETH_RING_PAUSE_DATA_OFFSET(port,
3333 fp->cl_id);
3334 for (j = 0;
3335 j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4;
3336 j++)
3337 REG_WR(bp, offset + j*4,
3338 ((u32 *)&rx_pause)[j]);
3339 }
3340 }
3341
3342 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3343
3344 /* Init rate shaping and fairness contexts */
3345 if (IS_E1HMF(bp)) {
3346 int vn;
3347
3348 /* During init there is no active link
3349 Until link is up, set link rate to 10Gbps */
3350 bp->link_vars.line_speed = SPEED_10000;
3351 bnx2x_init_port_minmax(bp);
3352
3353 if (!BP_NOMCP(bp))
3354 bp->mf_config =
3355 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
3356 bnx2x_calc_vn_weight_sum(bp);
3357
3358 for (vn = VN_0; vn < E1HVN_MAX; vn++)
3359 bnx2x_init_vn_minmax(bp, 2*vn + port);
3360
3361 /* Enable rate shaping and fairness */
3362 bp->cmng.flags.cmng_enables |=
3363 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
3364
3365 } else {
3366 /* rate shaping and fairness are disabled */
3367 DP(NETIF_MSG_IFUP,
3368 "single function mode minmax will be disabled\n");
3369 } 4415 }
4416}
3370 4417
3371 4418static void bnx2x_init_internal_port(struct bnx2x *bp)
3372 /* Store cmng structures to internal memory */ 4419{
3373 if (bp->port.pmf) 4420 /* port */
3374 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++) 4421 bnx2x_dcb_init_intmem_pfc(bp);
3375 REG_WR(bp, BAR_XSTRORM_INTMEM +
3376 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
3377 ((u32 *)(&bp->cmng))[i]);
3378} 4422}
3379 4423
3380static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 4424static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
3381{ 4425{
3382 switch (load_code) { 4426 switch (load_code) {
3383 case FW_MSG_CODE_DRV_LOAD_COMMON: 4427 case FW_MSG_CODE_DRV_LOAD_COMMON:
4428 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
3384 bnx2x_init_internal_common(bp); 4429 bnx2x_init_internal_common(bp);
3385 /* no break */ 4430 /* no break */
3386 4431
@@ -3389,7 +4434,8 @@ static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
3389 /* no break */ 4434 /* no break */
3390 4435
3391 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 4436 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3392 bnx2x_init_internal_func(bp); 4437 /* internal memory per function is
4438 initialized inside bnx2x_pf_init */
3393 break; 4439 break;
3394 4440
3395 default: 4441 default:
@@ -3398,43 +4444,65 @@ static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
3398 } 4444 }
3399} 4445}
3400 4446
4447static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4448{
4449 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4450
4451 fp->state = BNX2X_FP_STATE_CLOSED;
4452
4453 fp->cid = fp_idx;
4454 fp->cl_id = BP_L_ID(bp) + fp_idx;
4455 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4456 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4457 /* qZone id equals to FW (per path) client id */
4458 fp->cl_qzone_id = fp->cl_id +
4459 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4460 ETH_MAX_RX_CLIENTS_E1H);
4461 /* init shortcut */
4462 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4463 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
4464 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4465 /* Setup SB indicies */
4466 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4467 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4468
4469 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4470 "cl_id %d fw_sb %d igu_sb %d\n",
4471 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4472 fp->igu_sb_id);
4473 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4474 fp->fw_sb_id, fp->igu_sb_id);
4475
4476 bnx2x_update_fpsb_idx(fp);
4477}
4478
3401void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) 4479void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
3402{ 4480{
3403 int i; 4481 int i;
3404 4482
3405 for_each_queue(bp, i) { 4483 for_each_eth_queue(bp, i)
3406 struct bnx2x_fastpath *fp = &bp->fp[i]; 4484 bnx2x_init_fp_sb(bp, i);
3407
3408 fp->bp = bp;
3409 fp->state = BNX2X_FP_STATE_CLOSED;
3410 fp->index = i;
3411 fp->cl_id = BP_L_ID(bp) + i;
3412#ifdef BCM_CNIC 4485#ifdef BCM_CNIC
3413 fp->sb_id = fp->cl_id + 1; 4486 if (!NO_FCOE(bp))
3414#else 4487 bnx2x_init_fcoe_fp(bp);
3415 fp->sb_id = fp->cl_id; 4488
4489 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4490 BNX2X_VF_ID_INVALID, false,
4491 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4492
3416#endif 4493#endif
3417 DP(NETIF_MSG_IFUP,
3418 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d sb %d\n",
3419 i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
3420 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
3421 fp->sb_id);
3422 bnx2x_update_fpsb_idx(fp);
3423 }
3424 4494
3425 /* ensure status block indices were read */ 4495 /* ensure status block indices were read */
3426 rmb(); 4496 rmb();
3427 4497
3428 4498 bnx2x_init_def_sb(bp);
3429 bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
3430 DEF_SB_ID);
3431 bnx2x_update_dsb_idx(bp); 4499 bnx2x_update_dsb_idx(bp);
3432 bnx2x_update_coalesce(bp);
3433 bnx2x_init_rx_rings(bp); 4500 bnx2x_init_rx_rings(bp);
3434 bnx2x_init_tx_ring(bp); 4501 bnx2x_init_tx_rings(bp);
3435 bnx2x_init_sp_ring(bp); 4502 bnx2x_init_sp_ring(bp);
3436 bnx2x_init_context(bp); 4503 bnx2x_init_eq_ring(bp);
3437 bnx2x_init_internal(bp, load_code); 4504 bnx2x_init_internal(bp, load_code);
4505 bnx2x_pf_init(bp);
3438 bnx2x_init_ind_table(bp); 4506 bnx2x_init_ind_table(bp);
3439 bnx2x_stats_init(bp); 4507 bnx2x_stats_init(bp);
3440 4508
@@ -3470,8 +4538,7 @@ static int bnx2x_gunzip_init(struct bnx2x *bp)
3470 if (bp->strm == NULL) 4538 if (bp->strm == NULL)
3471 goto gunzip_nomem2; 4539 goto gunzip_nomem2;
3472 4540
3473 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), 4541 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
3474 GFP_KERNEL);
3475 if (bp->strm->workspace == NULL) 4542 if (bp->strm->workspace == NULL)
3476 goto gunzip_nomem3; 4543 goto gunzip_nomem3;
3477 4544
@@ -3494,10 +4561,11 @@ gunzip_nomem1:
3494 4561
3495static void bnx2x_gunzip_end(struct bnx2x *bp) 4562static void bnx2x_gunzip_end(struct bnx2x *bp)
3496{ 4563{
3497 kfree(bp->strm->workspace); 4564 if (bp->strm) {
3498 4565 vfree(bp->strm->workspace);
3499 kfree(bp->strm); 4566 kfree(bp->strm);
3500 bp->strm = NULL; 4567 bp->strm = NULL;
4568 }
3501 4569
3502 if (bp->gunzip_buf) { 4570 if (bp->gunzip_buf) {
3503 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 4571 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
@@ -3593,8 +4661,6 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
3593 else 4661 else
3594 factor = 1; 4662 factor = 1;
3595 4663
3596 DP(NETIF_MSG_HW, "start part1\n");
3597
3598 /* Disable inputs of parser neighbor blocks */ 4664 /* Disable inputs of parser neighbor blocks */
3599 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 4665 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
3600 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 4666 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
@@ -3728,12 +4794,22 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
3728 return 0; /* OK */ 4794 return 0; /* OK */
3729} 4795}
3730 4796
3731static void enable_blocks_attention(struct bnx2x *bp) 4797static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
3732{ 4798{
3733 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 4799 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
3734 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 4800 if (CHIP_IS_E2(bp))
4801 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4802 else
4803 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
3735 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 4804 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
3736 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 4805 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
4806 /*
4807 * mask read length error interrupts in brb for parser
4808 * (parsing unit and 'checksum and crc' unit)
4809 * these errors are legal (PU reads fixed length and CAC can cause
4810 * read length error on truncated packets)
4811 */
4812 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
3737 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 4813 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
3738 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 4814 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
3739 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 4815 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
@@ -3752,8 +4828,16 @@ static void enable_blocks_attention(struct bnx2x *bp)
3752 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 4828 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
3753/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 4829/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
3754/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 4830/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
4831
3755 if (CHIP_REV_IS_FPGA(bp)) 4832 if (CHIP_REV_IS_FPGA(bp))
3756 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000); 4833 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
4834 else if (CHIP_IS_E2(bp))
4835 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4836 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4837 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4838 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4839 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4840 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
3757 else 4841 else
3758 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000); 4842 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
3759 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 4843 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
@@ -3764,54 +4848,9 @@ static void enable_blocks_attention(struct bnx2x *bp)
3764 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 4848 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
3765 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 4849 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
3766/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 4850/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
3767 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */ 4851 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
3768} 4852}
3769 4853
3770static const struct {
3771 u32 addr;
3772 u32 mask;
3773} bnx2x_parity_mask[] = {
3774 {PXP_REG_PXP_PRTY_MASK, 0xffffffff},
3775 {PXP2_REG_PXP2_PRTY_MASK_0, 0xffffffff},
3776 {PXP2_REG_PXP2_PRTY_MASK_1, 0xffffffff},
3777 {HC_REG_HC_PRTY_MASK, 0xffffffff},
3778 {MISC_REG_MISC_PRTY_MASK, 0xffffffff},
3779 {QM_REG_QM_PRTY_MASK, 0x0},
3780 {DORQ_REG_DORQ_PRTY_MASK, 0x0},
3781 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},
3782 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},
3783 {SRC_REG_SRC_PRTY_MASK, 0x4}, /* bit 2 */
3784 {CDU_REG_CDU_PRTY_MASK, 0x0},
3785 {CFC_REG_CFC_PRTY_MASK, 0x0},
3786 {DBG_REG_DBG_PRTY_MASK, 0x0},
3787 {DMAE_REG_DMAE_PRTY_MASK, 0x0},
3788 {BRB1_REG_BRB1_PRTY_MASK, 0x0},
3789 {PRS_REG_PRS_PRTY_MASK, (1<<6)},/* bit 6 */
3790 {TSDM_REG_TSDM_PRTY_MASK, 0x18},/* bit 3,4 */
3791 {CSDM_REG_CSDM_PRTY_MASK, 0x8}, /* bit 3 */
3792 {USDM_REG_USDM_PRTY_MASK, 0x38},/* bit 3,4,5 */
3793 {XSDM_REG_XSDM_PRTY_MASK, 0x8}, /* bit 3 */
3794 {TSEM_REG_TSEM_PRTY_MASK_0, 0x0},
3795 {TSEM_REG_TSEM_PRTY_MASK_1, 0x0},
3796 {USEM_REG_USEM_PRTY_MASK_0, 0x0},
3797 {USEM_REG_USEM_PRTY_MASK_1, 0x0},
3798 {CSEM_REG_CSEM_PRTY_MASK_0, 0x0},
3799 {CSEM_REG_CSEM_PRTY_MASK_1, 0x0},
3800 {XSEM_REG_XSEM_PRTY_MASK_0, 0x0},
3801 {XSEM_REG_XSEM_PRTY_MASK_1, 0x0}
3802};
3803
3804static void enable_blocks_parity(struct bnx2x *bp)
3805{
3806 int i, mask_arr_len =
3807 sizeof(bnx2x_parity_mask)/(sizeof(bnx2x_parity_mask[0]));
3808
3809 for (i = 0; i < mask_arr_len; i++)
3810 REG_WR(bp, bnx2x_parity_mask[i].addr,
3811 bnx2x_parity_mask[i].mask);
3812}
3813
3814
3815static void bnx2x_reset_common(struct bnx2x *bp) 4854static void bnx2x_reset_common(struct bnx2x *bp)
3816{ 4855{
3817 /* reset_common */ 4856 /* reset_common */
@@ -3862,17 +4901,12 @@ static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
3862 */ 4901 */
3863 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 4902 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
3864 for (port = PORT_0; port < PORT_MAX; port++) { 4903 for (port = PORT_0; port < PORT_MAX; port++) {
3865 u32 phy_type =
3866 SHMEM_RD(bp, dev_info.port_hw_config[port].
3867 external_phy_config) &
3868 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3869 is_required |= 4904 is_required |=
3870 ((phy_type == 4905 bnx2x_fan_failure_det_req(
3871 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) || 4906 bp,
3872 (phy_type == 4907 bp->common.shmem_base,
3873 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 4908 bp->common.shmem2_base,
3874 (phy_type == 4909 port);
3875 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
3876 } 4910 }
3877 4911
3878 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 4912 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
@@ -3896,26 +4930,97 @@ static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
3896 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 4930 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
3897} 4931}
3898 4932
3899static int bnx2x_init_common(struct bnx2x *bp) 4933static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4934{
4935 u32 offset = 0;
4936
4937 if (CHIP_IS_E1(bp))
4938 return;
4939 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4940 return;
4941
4942 switch (BP_ABS_FUNC(bp)) {
4943 case 0:
4944 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4945 break;
4946 case 1:
4947 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4948 break;
4949 case 2:
4950 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4951 break;
4952 case 3:
4953 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4954 break;
4955 case 4:
4956 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4957 break;
4958 case 5:
4959 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4960 break;
4961 case 6:
4962 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4963 break;
4964 case 7:
4965 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4966 break;
4967 default:
4968 return;
4969 }
4970
4971 REG_WR(bp, offset, pretend_func_num);
4972 REG_RD(bp, offset);
4973 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4974}
4975
4976static void bnx2x_pf_disable(struct bnx2x *bp)
4977{
4978 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4979 val &= ~IGU_PF_CONF_FUNC_EN;
4980
4981 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4982 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4983 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4984}
4985
4986static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
3900{ 4987{
3901 u32 val, i; 4988 u32 val, i;
3902#ifdef BCM_CNIC
3903 u32 wb_write[2];
3904#endif
3905 4989
3906 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_FUNC(bp)); 4990 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
3907 4991
3908 bnx2x_reset_common(bp); 4992 bnx2x_reset_common(bp);
3909 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 4993 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
3910 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc); 4994 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
3911 4995
3912 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE); 4996 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
3913 if (CHIP_IS_E1H(bp)) 4997 if (!CHIP_IS_E1(bp))
3914 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp)); 4998 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
3915 4999
3916 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100); 5000 if (CHIP_IS_E2(bp)) {
3917 msleep(30); 5001 u8 fid;
3918 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0); 5002
5003 /**
5004 * 4-port mode or 2-port mode we need to turn of master-enable
5005 * for everyone, after that, turn it back on for self.
5006 * so, we disregard multi-function or not, and always disable
5007 * for all functions on the given path, this means 0,2,4,6 for
5008 * path 0 and 1,3,5,7 for path 1
5009 */
5010 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
5011 if (fid == BP_ABS_FUNC(bp)) {
5012 REG_WR(bp,
5013 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5014 1);
5015 continue;
5016 }
5017
5018 bnx2x_pretend_func(bp, fid);
5019 /* clear pf enable */
5020 bnx2x_pf_disable(bp);
5021 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5022 }
5023 }
3919 5024
3920 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE); 5025 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
3921 if (CHIP_IS_E1(bp)) { 5026 if (CHIP_IS_E1(bp)) {
@@ -3943,12 +5048,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
3943 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 5048 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
3944#endif 5049#endif
3945 5050
3946 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2); 5051 bnx2x_ilt_init_page_size(bp, INITOP_SET);
3947#ifdef BCM_CNIC
3948 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
3949 REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
3950 REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
3951#endif
3952 5052
3953 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 5053 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
3954 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 5054 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
@@ -3967,9 +5067,65 @@ static int bnx2x_init_common(struct bnx2x *bp)
3967 return -EBUSY; 5067 return -EBUSY;
3968 } 5068 }
3969 5069
5070 /* Timers bug workaround E2 only. We need to set the entire ILT to
5071 * have entries with value "0" and valid bit on.
5072 * This needs to be done by the first PF that is loaded in a path
5073 * (i.e. common phase)
5074 */
5075 if (CHIP_IS_E2(bp)) {
5076 struct ilt_client_info ilt_cli;
5077 struct bnx2x_ilt ilt;
5078 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5079 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5080
5081 /* initialize dummy TM client */
5082 ilt_cli.start = 0;
5083 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5084 ilt_cli.client_num = ILT_CLIENT_TM;
5085
5086 /* Step 1: set zeroes to all ilt page entries with valid bit on
5087 * Step 2: set the timers first/last ilt entry to point
5088 * to the entire range to prevent ILT range error for 3rd/4th
5089 * vnic (this code assumes existence of the vnic)
5090 *
5091 * both steps performed by call to bnx2x_ilt_client_init_op()
5092 * with dummy TM client
5093 *
5094 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5095 * and his brother are split registers
5096 */
5097 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5098 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5099 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5100
5101 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5102 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5103 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5104 }
5105
5106
3970 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 5107 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
3971 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 5108 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
3972 5109
5110 if (CHIP_IS_E2(bp)) {
5111 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5112 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5113 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5114
5115 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5116
5117 /* let the HW do it's magic ... */
5118 do {
5119 msleep(200);
5120 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5121 } while (factor-- && (val != 1));
5122
5123 if (val != 1) {
5124 BNX2X_ERR("ATC_INIT failed\n");
5125 return -EBUSY;
5126 }
5127 }
5128
3973 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE); 5129 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
3974 5130
3975 /* clean the DMAE memory */ 5131 /* clean the DMAE memory */
@@ -3988,20 +5144,12 @@ static int bnx2x_init_common(struct bnx2x *bp)
3988 5144
3989 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE); 5145 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
3990 5146
3991#ifdef BCM_CNIC 5147 if (CHIP_MODE_IS_4_PORT(bp))
3992 wb_write[0] = 0; 5148 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
3993 wb_write[1] = 0; 5149
3994 for (i = 0; i < 64; i++) { 5150 /* QM queues pointers table */
3995 REG_WR(bp, QM_REG_BASEADDR + i*4, 1024 * 4 * (i%16)); 5151 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
3996 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL + i*8, wb_write, 2);
3997 5152
3998 if (CHIP_IS_E1H(bp)) {
3999 REG_WR(bp, QM_REG_BASEADDR_EXT_A + i*4, 1024*4*(i%16));
4000 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL_EXT_A + i*8,
4001 wb_write, 2);
4002 }
4003 }
4004#endif
4005 /* soft reset pulse */ 5153 /* soft reset pulse */
4006 REG_WR(bp, QM_REG_SOFT_RESET, 1); 5154 REG_WR(bp, QM_REG_SOFT_RESET, 1);
4007 REG_WR(bp, QM_REG_SOFT_RESET, 0); 5155 REG_WR(bp, QM_REG_SOFT_RESET, 0);
@@ -4011,21 +5159,35 @@ static int bnx2x_init_common(struct bnx2x *bp)
4011#endif 5159#endif
4012 5160
4013 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE); 5161 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
4014 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT); 5162 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5163
4015 if (!CHIP_REV_IS_SLOW(bp)) { 5164 if (!CHIP_REV_IS_SLOW(bp)) {
4016 /* enable hw interrupt from doorbell Q */ 5165 /* enable hw interrupt from doorbell Q */
4017 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 5166 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4018 } 5167 }
4019 5168
4020 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE); 5169 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5170 if (CHIP_MODE_IS_4_PORT(bp)) {
5171 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5172 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5173 }
5174
4021 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE); 5175 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4022 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 5176 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
4023#ifndef BCM_CNIC 5177#ifndef BCM_CNIC
4024 /* set NIC mode */ 5178 /* set NIC mode */
4025 REG_WR(bp, PRS_REG_NIC_MODE, 1); 5179 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4026#endif 5180#endif
4027 if (CHIP_IS_E1H(bp)) 5181 if (!CHIP_IS_E1(bp))
4028 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp)); 5182 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
5183
5184 if (CHIP_IS_E2(bp)) {
5185 /* Bit-map indicating which L2 hdrs may appear after the
5186 basic Ethernet header */
5187 int has_ovlan = IS_MF_SD(bp);
5188 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5189 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5190 }
4029 5191
4030 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE); 5192 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
4031 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE); 5193 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
@@ -4042,6 +5204,9 @@ static int bnx2x_init_common(struct bnx2x *bp)
4042 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE); 5204 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
4043 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE); 5205 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
4044 5206
5207 if (CHIP_MODE_IS_4_PORT(bp))
5208 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5209
4045 /* sync semi rtc */ 5210 /* sync semi rtc */
4046 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 5211 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4047 0x80000000); 5212 0x80000000);
@@ -4052,9 +5217,16 @@ static int bnx2x_init_common(struct bnx2x *bp)
4052 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE); 5217 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
4053 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE); 5218 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
4054 5219
5220 if (CHIP_IS_E2(bp)) {
5221 int has_ovlan = IS_MF_SD(bp);
5222 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5223 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5224 }
5225
4055 REG_WR(bp, SRC_REG_SOFT_RST, 1); 5226 REG_WR(bp, SRC_REG_SOFT_RST, 1);
4056 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) 5227 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
4057 REG_WR(bp, i, random32()); 5228 REG_WR(bp, i, random32());
5229
4058 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE); 5230 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
4059#ifdef BCM_CNIC 5231#ifdef BCM_CNIC
4060 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 5232 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
@@ -4089,6 +5261,11 @@ static int bnx2x_init_common(struct bnx2x *bp)
4089 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 5261 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
4090 5262
4091 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE); 5263 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5264
5265 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5266 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5267
5268 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
4092 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE); 5269 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
4093 5270
4094 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE); 5271 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
@@ -4096,15 +5273,34 @@ static int bnx2x_init_common(struct bnx2x *bp)
4096 REG_WR(bp, 0x2814, 0xffffffff); 5273 REG_WR(bp, 0x2814, 0xffffffff);
4097 REG_WR(bp, 0x3820, 0xffffffff); 5274 REG_WR(bp, 0x3820, 0xffffffff);
4098 5275
5276 if (CHIP_IS_E2(bp)) {
5277 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5278 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5279 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5280 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5281 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5282 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5283 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5284 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5285 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5286 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5287 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5288 }
5289
4099 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE); 5290 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
4100 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE); 5291 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
4101 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE); 5292 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
4102 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE); 5293 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
4103 5294
4104 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE); 5295 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
4105 if (CHIP_IS_E1H(bp)) { 5296 if (!CHIP_IS_E1(bp)) {
4106 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp)); 5297 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
4107 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp)); 5298 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5299 }
5300 if (CHIP_IS_E2(bp)) {
5301 /* Bit-map indicating which L2 hdrs may appear after the
5302 basic Ethernet header */
5303 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
4108 } 5304 }
4109 5305
4110 if (CHIP_REV_IS_SLOW(bp)) 5306 if (CHIP_REV_IS_SLOW(bp))
@@ -4128,27 +5324,17 @@ static int bnx2x_init_common(struct bnx2x *bp)
4128 } 5324 }
4129 REG_WR(bp, CFC_REG_DEBUG0, 0); 5325 REG_WR(bp, CFC_REG_DEBUG0, 0);
4130 5326
4131 /* read NIG statistic 5327 if (CHIP_IS_E1(bp)) {
4132 to see if this is our first up since powerup */ 5328 /* read NIG statistic
4133 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 5329 to see if this is our first up since powerup */
4134 val = *bnx2x_sp(bp, wb_data[0]); 5330 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4135 5331 val = *bnx2x_sp(bp, wb_data[0]);
4136 /* do internal memory self test */
4137 if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
4138 BNX2X_ERR("internal mem self test failed\n");
4139 return -EBUSY;
4140 }
4141
4142 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
4143 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4144 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4145 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4146 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4147 bp->port.need_hw_lock = 1;
4148 break;
4149 5332
4150 default: 5333 /* do internal memory self test */
4151 break; 5334 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5335 BNX2X_ERR("internal mem self test failed\n");
5336 return -EBUSY;
5337 }
4152 } 5338 }
4153 5339
4154 bnx2x_setup_fan_failure_detection(bp); 5340 bnx2x_setup_fan_failure_detection(bp);
@@ -4156,21 +5342,35 @@ static int bnx2x_init_common(struct bnx2x *bp)
4156 /* clear PXP2 attentions */ 5342 /* clear PXP2 attentions */
4157 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 5343 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
4158 5344
4159 enable_blocks_attention(bp); 5345 bnx2x_enable_blocks_attention(bp);
4160 if (CHIP_PARITY_SUPPORTED(bp)) 5346 if (CHIP_PARITY_ENABLED(bp))
4161 enable_blocks_parity(bp); 5347 bnx2x_enable_blocks_parity(bp);
4162 5348
4163 if (!BP_NOMCP(bp)) { 5349 if (!BP_NOMCP(bp)) {
4164 bnx2x_acquire_phy_lock(bp); 5350 /* In E2 2-PORT mode, same ext phy is used for the two paths */
4165 bnx2x_common_init_phy(bp, bp->common.shmem_base); 5351 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
4166 bnx2x_release_phy_lock(bp); 5352 CHIP_IS_E1x(bp)) {
5353 u32 shmem_base[2], shmem2_base[2];
5354 shmem_base[0] = bp->common.shmem_base;
5355 shmem2_base[0] = bp->common.shmem2_base;
5356 if (CHIP_IS_E2(bp)) {
5357 shmem_base[1] =
5358 SHMEM2_RD(bp, other_shmem_base_addr);
5359 shmem2_base[1] =
5360 SHMEM2_RD(bp, other_shmem2_base_addr);
5361 }
5362 bnx2x_acquire_phy_lock(bp);
5363 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5364 bp->common.chip_id);
5365 bnx2x_release_phy_lock(bp);
5366 }
4167 } else 5367 } else
4168 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 5368 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
4169 5369
4170 return 0; 5370 return 0;
4171} 5371}
4172 5372
4173static int bnx2x_init_port(struct bnx2x *bp) 5373static int bnx2x_init_hw_port(struct bnx2x *bp)
4174{ 5374{
4175 int port = BP_PORT(bp); 5375 int port = BP_PORT(bp);
4176 int init_stage = port ? PORT1_STAGE : PORT0_STAGE; 5376 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
@@ -4184,14 +5384,23 @@ static int bnx2x_init_port(struct bnx2x *bp)
4184 bnx2x_init_block(bp, PXP_BLOCK, init_stage); 5384 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
4185 bnx2x_init_block(bp, PXP2_BLOCK, init_stage); 5385 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
4186 5386
5387 /* Timers bug workaround: disables the pf_master bit in pglue at
5388 * common phase, we need to enable it here before any dmae access are
5389 * attempted. Therefore we manually added the enable-master to the
5390 * port phase (it also happens in the function phase)
5391 */
5392 if (CHIP_IS_E2(bp))
5393 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5394
4187 bnx2x_init_block(bp, TCM_BLOCK, init_stage); 5395 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
4188 bnx2x_init_block(bp, UCM_BLOCK, init_stage); 5396 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
4189 bnx2x_init_block(bp, CCM_BLOCK, init_stage); 5397 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
4190 bnx2x_init_block(bp, XCM_BLOCK, init_stage); 5398 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
4191 5399
4192#ifdef BCM_CNIC 5400 /* QM cid (connection) count */
4193 REG_WR(bp, QM_REG_CONNNUM_0 + port*4, 1024/16 - 1); 5401 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
4194 5402
5403#ifdef BCM_CNIC
4195 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage); 5404 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
4196 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 5405 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
4197 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 5406 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
@@ -4199,29 +5408,41 @@ static int bnx2x_init_port(struct bnx2x *bp)
4199 5408
4200 bnx2x_init_block(bp, DQ_BLOCK, init_stage); 5409 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
4201 5410
4202 bnx2x_init_block(bp, BRB1_BLOCK, init_stage); 5411 if (CHIP_MODE_IS_4_PORT(bp))
4203 if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) { 5412 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
4204 /* no pause for emulation and FPGA */ 5413
4205 low = 0; 5414 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
4206 high = 513; 5415 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
4207 } else { 5416 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
4208 if (IS_E1HMF(bp)) 5417 /* no pause for emulation and FPGA */
4209 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 5418 low = 0;
4210 else if (bp->dev->mtu > 4096) { 5419 high = 513;
4211 if (bp->flags & ONE_PORT_FLAG) 5420 } else {
4212 low = 160; 5421 if (IS_MF(bp))
4213 else { 5422 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
4214 val = bp->dev->mtu; 5423 else if (bp->dev->mtu > 4096) {
4215 /* (24*1024 + val*4)/256 */ 5424 if (bp->flags & ONE_PORT_FLAG)
4216 low = 96 + (val/64) + ((val % 64) ? 1 : 0); 5425 low = 160;
4217 } 5426 else {
4218 } else 5427 val = bp->dev->mtu;
4219 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 5428 /* (24*1024 + val*4)/256 */
4220 high = low + 56; /* 14*1024/256 */ 5429 low = 96 + (val/64) +
5430 ((val % 64) ? 1 : 0);
5431 }
5432 } else
5433 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5434 high = low + 56; /* 14*1024/256 */
5435 }
5436 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5437 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
4221 } 5438 }
4222 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
4223 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
4224 5439
5440 if (CHIP_MODE_IS_4_PORT(bp)) {
5441 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5442 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5443 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5444 BRB1_REG_MAC_GUARANTIED_0), 40);
5445 }
4225 5446
4226 bnx2x_init_block(bp, PRS_BLOCK, init_stage); 5447 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
4227 5448
@@ -4234,24 +5455,28 @@ static int bnx2x_init_port(struct bnx2x *bp)
4234 bnx2x_init_block(bp, USEM_BLOCK, init_stage); 5455 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
4235 bnx2x_init_block(bp, CSEM_BLOCK, init_stage); 5456 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
4236 bnx2x_init_block(bp, XSEM_BLOCK, init_stage); 5457 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5458 if (CHIP_MODE_IS_4_PORT(bp))
5459 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
4237 5460
4238 bnx2x_init_block(bp, UPB_BLOCK, init_stage); 5461 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
4239 bnx2x_init_block(bp, XPB_BLOCK, init_stage); 5462 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
4240 5463
4241 bnx2x_init_block(bp, PBF_BLOCK, init_stage); 5464 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
4242 5465
4243 /* configure PBF to work without PAUSE mtu 9000 */ 5466 if (!CHIP_IS_E2(bp)) {
4244 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 5467 /* configure PBF to work without PAUSE mtu 9000 */
5468 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
4245 5469
4246 /* update threshold */ 5470 /* update threshold */
4247 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 5471 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
4248 /* update init credit */ 5472 /* update init credit */
4249 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 5473 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
4250 5474
4251 /* probe changes */ 5475 /* probe changes */
4252 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 5476 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
4253 msleep(5); 5477 udelay(50);
4254 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 5478 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5479 }
4255 5480
4256#ifdef BCM_CNIC 5481#ifdef BCM_CNIC
4257 bnx2x_init_block(bp, SRCH_BLOCK, init_stage); 5482 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
@@ -4265,13 +5490,17 @@ static int bnx2x_init_port(struct bnx2x *bp)
4265 } 5490 }
4266 bnx2x_init_block(bp, HC_BLOCK, init_stage); 5491 bnx2x_init_block(bp, HC_BLOCK, init_stage);
4267 5492
5493 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5494
4268 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage); 5495 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
4269 /* init aeu_mask_attn_func_0/1: 5496 /* init aeu_mask_attn_func_0/1:
4270 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 5497 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
4271 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 5498 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
4272 * bits 4-7 are used for "per vn group attention" */ 5499 * bits 4-7 are used for "per vn group attention" */
4273 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 5500 val = IS_MF(bp) ? 0xF7 : 0x7;
4274 (IS_E1HMF(bp) ? 0xF7 : 0x7)); 5501 /* Enable DCBX attention for all but E1 */
5502 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5503 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
4275 5504
4276 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage); 5505 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
4277 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage); 5506 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
@@ -4283,11 +5512,25 @@ static int bnx2x_init_port(struct bnx2x *bp)
4283 5512
4284 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 5513 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
4285 5514
4286 if (CHIP_IS_E1H(bp)) { 5515 if (!CHIP_IS_E1(bp)) {
4287 /* 0x2 disable e1hov, 0x1 enable */ 5516 /* 0x2 disable mf_ov, 0x1 enable */
4288 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 5517 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
4289 (IS_E1HMF(bp) ? 0x1 : 0x2)); 5518 (IS_MF_SD(bp) ? 0x1 : 0x2));
4290 5519
5520 if (CHIP_IS_E2(bp)) {
5521 val = 0;
5522 switch (bp->mf_mode) {
5523 case MULTI_FUNCTION_SD:
5524 val = 1;
5525 break;
5526 case MULTI_FUNCTION_SI:
5527 val = 2;
5528 break;
5529 }
5530
5531 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5532 NIG_REG_LLH0_CLS_TYPE), val);
5533 }
4291 { 5534 {
4292 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 5535 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
4293 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 5536 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
@@ -4297,223 +5540,356 @@ static int bnx2x_init_port(struct bnx2x *bp)
4297 5540
4298 bnx2x_init_block(bp, MCP_BLOCK, init_stage); 5541 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
4299 bnx2x_init_block(bp, DMAE_BLOCK, init_stage); 5542 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
4300 5543 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
4301 switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) { 5544 bp->common.shmem2_base, port)) {
4302 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4303 {
4304 u32 swap_val, swap_override, aeu_gpio_mask, offset;
4305
4306 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
4307 MISC_REGISTERS_GPIO_INPUT_HI_Z, port);
4308
4309 /* The GPIO should be swapped if the swap register is
4310 set and active */
4311 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4312 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4313
4314 /* Select function upon port-swap configuration */
4315 if (port == 0) {
4316 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4317 aeu_gpio_mask = (swap_val && swap_override) ?
4318 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
4319 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
4320 } else {
4321 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
4322 aeu_gpio_mask = (swap_val && swap_override) ?
4323 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
4324 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
4325 }
4326 val = REG_RD(bp, offset);
4327 /* add GPIO3 to group */
4328 val |= aeu_gpio_mask;
4329 REG_WR(bp, offset, val);
4330 }
4331 bp->port.need_hw_lock = 1;
4332 break;
4333
4334 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4335 bp->port.need_hw_lock = 1;
4336 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4337 /* add SPIO 5 to group 0 */
4338 {
4339 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 5545 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4340 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 5546 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4341 val = REG_RD(bp, reg_addr); 5547 val = REG_RD(bp, reg_addr);
4342 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 5548 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4343 REG_WR(bp, reg_addr, val); 5549 REG_WR(bp, reg_addr, val);
4344 }
4345 break;
4346 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4347 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4348 bp->port.need_hw_lock = 1;
4349 break;
4350 default:
4351 break;
4352 } 5550 }
4353
4354 bnx2x__link_reset(bp); 5551 bnx2x__link_reset(bp);
4355 5552
4356 return 0; 5553 return 0;
4357} 5554}
4358 5555
4359#define ILT_PER_FUNC (768/2)
4360#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
4361/* the phys address is shifted right 12 bits and has an added
4362 1=valid bit added to the 53rd bit
4363 then since this is a wide register(TM)
4364 we split it into two 32 bit writes
4365 */
4366#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
4367#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
4368#define PXP_ONE_ILT(x) (((x) << 10) | x)
4369#define PXP_ILT_RANGE(f, l) (((l) << 10) | f)
4370
4371#ifdef BCM_CNIC
4372#define CNIC_ILT_LINES 127
4373#define CNIC_CTX_PER_ILT 16
4374#else
4375#define CNIC_ILT_LINES 0
4376#endif
4377
4378static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 5556static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
4379{ 5557{
4380 int reg; 5558 int reg;
4381 5559
4382 if (CHIP_IS_E1H(bp)) 5560 if (CHIP_IS_E1(bp))
4383 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
4384 else /* E1 */
4385 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 5561 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5562 else
5563 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
4386 5564
4387 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr)); 5565 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
4388} 5566}
4389 5567
4390static int bnx2x_init_func(struct bnx2x *bp) 5568static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5569{
5570 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5571}
5572
5573static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5574{
5575 u32 i, base = FUNC_ILT_BASE(func);
5576 for (i = base; i < base + ILT_PER_FUNC; i++)
5577 bnx2x_ilt_wr(bp, i, 0);
5578}
5579
5580static int bnx2x_init_hw_func(struct bnx2x *bp)
4391{ 5581{
4392 int port = BP_PORT(bp); 5582 int port = BP_PORT(bp);
4393 int func = BP_FUNC(bp); 5583 int func = BP_FUNC(bp);
5584 struct bnx2x_ilt *ilt = BP_ILT(bp);
5585 u16 cdu_ilt_start;
4394 u32 addr, val; 5586 u32 addr, val;
4395 int i; 5587 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5588 int i, main_mem_width;
4396 5589
4397 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 5590 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
4398 5591
4399 /* set MSI reconfigure capability */ 5592 /* set MSI reconfigure capability */
4400 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 5593 if (bp->common.int_block == INT_BLOCK_HC) {
4401 val = REG_RD(bp, addr); 5594 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
4402 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 5595 val = REG_RD(bp, addr);
4403 REG_WR(bp, addr, val); 5596 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5597 REG_WR(bp, addr, val);
5598 }
4404 5599
4405 i = FUNC_ILT_BASE(func); 5600 ilt = BP_ILT(bp);
5601 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
4406 5602
4407 bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context)); 5603 for (i = 0; i < L2_ILT_LINES(bp); i++) {
4408 if (CHIP_IS_E1H(bp)) { 5604 ilt->lines[cdu_ilt_start + i].page =
4409 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i); 5605 bp->context.vcxt + (ILT_PAGE_CIDS * i);
4410 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES); 5606 ilt->lines[cdu_ilt_start + i].page_mapping =
4411 } else /* E1 */ 5607 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
4412 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4, 5608 /* cdu ilt pages are allocated manually so there's no need to
4413 PXP_ILT_RANGE(i, i + CNIC_ILT_LINES)); 5609 set the size */
5610 }
5611 bnx2x_ilt_init_op(bp, INITOP_SET);
4414 5612
4415#ifdef BCM_CNIC 5613#ifdef BCM_CNIC
4416 i += 1 + CNIC_ILT_LINES; 5614 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
4417 bnx2x_ilt_wr(bp, i, bp->timers_mapping);
4418 if (CHIP_IS_E1(bp))
4419 REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
4420 else {
4421 REG_WR(bp, PXP2_REG_RQ_TM_FIRST_ILT, i);
4422 REG_WR(bp, PXP2_REG_RQ_TM_LAST_ILT, i);
4423 }
4424 5615
4425 i++; 5616 /* T1 hash bits value determines the T1 number of entries */
4426 bnx2x_ilt_wr(bp, i, bp->qm_mapping); 5617 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
4427 if (CHIP_IS_E1(bp)) 5618#endif
4428 REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i)); 5619
4429 else { 5620#ifndef BCM_CNIC
4430 REG_WR(bp, PXP2_REG_RQ_QM_FIRST_ILT, i); 5621 /* set NIC mode */
4431 REG_WR(bp, PXP2_REG_RQ_QM_LAST_ILT, i); 5622 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5623#endif /* BCM_CNIC */
5624
5625 if (CHIP_IS_E2(bp)) {
5626 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5627
5628 /* Turn on a single ISR mode in IGU if driver is going to use
5629 * INT#x or MSI
5630 */
5631 if (!(bp->flags & USING_MSIX_FLAG))
5632 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5633 /*
5634 * Timers workaround bug: function init part.
5635 * Need to wait 20msec after initializing ILT,
5636 * needed to make sure there are no requests in
5637 * one of the PXP internal queues with "old" ILT addresses
5638 */
5639 msleep(20);
5640 /*
5641 * Master enable - Due to WB DMAE writes performed before this
5642 * register is re-initialized as part of the regular function
5643 * init
5644 */
5645 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5646 /* Enable the function in IGU */
5647 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
4432 } 5648 }
4433 5649
4434 i++; 5650 bp->dmae_ready = 1;
4435 bnx2x_ilt_wr(bp, i, bp->t1_mapping); 5651
4436 if (CHIP_IS_E1(bp)) 5652 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
4437 REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i)); 5653
4438 else { 5654 if (CHIP_IS_E2(bp))
4439 REG_WR(bp, PXP2_REG_RQ_SRC_FIRST_ILT, i); 5655 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
4440 REG_WR(bp, PXP2_REG_RQ_SRC_LAST_ILT, i); 5656
5657 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5658 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5659 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5660 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5661 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5662 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5663 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5664 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5665 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5666
5667 if (CHIP_IS_E2(bp)) {
5668 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5669 BP_PATH(bp));
5670 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5671 BP_PATH(bp));
4441 } 5672 }
4442 5673
4443 /* tell the searcher where the T2 table is */ 5674 if (CHIP_MODE_IS_4_PORT(bp))
4444 REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, 16*1024/64); 5675 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
4445 5676
4446 bnx2x_wb_wr(bp, SRC_REG_FIRSTFREE0 + port*16, 5677 if (CHIP_IS_E2(bp))
4447 U64_LO(bp->t2_mapping), U64_HI(bp->t2_mapping)); 5678 REG_WR(bp, QM_REG_PF_EN, 1);
4448 5679
4449 bnx2x_wb_wr(bp, SRC_REG_LASTFREE0 + port*16, 5680 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
4450 U64_LO((u64)bp->t2_mapping + 16*1024 - 64),
4451 U64_HI((u64)bp->t2_mapping + 16*1024 - 64));
4452 5681
4453 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, 10); 5682 if (CHIP_MODE_IS_4_PORT(bp))
4454#endif 5683 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5684
5685 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5686 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5687 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5688 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5689 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5690 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5691 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5692 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5693 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5694 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5695 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
5696 if (CHIP_IS_E2(bp))
5697 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
4455 5698
4456 if (CHIP_IS_E1H(bp)) { 5699 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
4457 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
4458 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
4459 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
4460 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
4461 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
4462 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
4463 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
4464 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
4465 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
4466 5700
5701 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
5702
5703 if (CHIP_IS_E2(bp))
5704 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5705
5706 if (IS_MF(bp)) {
4467 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 5707 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
4468 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov); 5708 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
4469 } 5709 }
4470 5710
5711 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5712
4471 /* HC init per function */ 5713 /* HC init per function */
4472 if (CHIP_IS_E1H(bp)) { 5714 if (bp->common.int_block == INT_BLOCK_HC) {
5715 if (CHIP_IS_E1H(bp)) {
5716 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5717
5718 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5719 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5720 }
5721 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5722
5723 } else {
5724 int num_segs, sb_idx, prod_offset;
5725
4473 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 5726 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4474 5727
4475 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 5728 if (CHIP_IS_E2(bp)) {
4476 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 5729 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5730 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5731 }
5732
5733 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5734
5735 if (CHIP_IS_E2(bp)) {
5736 int dsb_idx = 0;
5737 /**
5738 * Producer memory:
5739 * E2 mode: address 0-135 match to the mapping memory;
5740 * 136 - PF0 default prod; 137 - PF1 default prod;
5741 * 138 - PF2 default prod; 139 - PF3 default prod;
5742 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5743 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5744 * 144-147 reserved.
5745 *
5746 * E1.5 mode - In backward compatible mode;
5747 * for non default SB; each even line in the memory
5748 * holds the U producer and each odd line hold
5749 * the C producer. The first 128 producers are for
5750 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5751 * producers are for the DSB for each PF.
5752 * Each PF has five segments: (the order inside each
5753 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5754 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5755 * 144-147 attn prods;
5756 */
5757 /* non-default-status-blocks */
5758 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5759 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5760 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5761 prod_offset = (bp->igu_base_sb + sb_idx) *
5762 num_segs;
5763
5764 for (i = 0; i < num_segs; i++) {
5765 addr = IGU_REG_PROD_CONS_MEMORY +
5766 (prod_offset + i) * 4;
5767 REG_WR(bp, addr, 0);
5768 }
5769 /* send consumer update with value 0 */
5770 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5771 USTORM_ID, 0, IGU_INT_NOP, 1);
5772 bnx2x_igu_clear_sb(bp,
5773 bp->igu_base_sb + sb_idx);
5774 }
5775
5776 /* default-status-blocks */
5777 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5778 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5779
5780 if (CHIP_MODE_IS_4_PORT(bp))
5781 dsb_idx = BP_FUNC(bp);
5782 else
5783 dsb_idx = BP_E1HVN(bp);
5784
5785 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5786 IGU_BC_BASE_DSB_PROD + dsb_idx :
5787 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5788
5789 for (i = 0; i < (num_segs * E1HVN_MAX);
5790 i += E1HVN_MAX) {
5791 addr = IGU_REG_PROD_CONS_MEMORY +
5792 (prod_offset + i)*4;
5793 REG_WR(bp, addr, 0);
5794 }
5795 /* send consumer update with 0 */
5796 if (CHIP_INT_MODE_IS_BC(bp)) {
5797 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5798 USTORM_ID, 0, IGU_INT_NOP, 1);
5799 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5800 CSTORM_ID, 0, IGU_INT_NOP, 1);
5801 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5802 XSTORM_ID, 0, IGU_INT_NOP, 1);
5803 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5804 TSTORM_ID, 0, IGU_INT_NOP, 1);
5805 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5806 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5807 } else {
5808 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5809 USTORM_ID, 0, IGU_INT_NOP, 1);
5810 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5811 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5812 }
5813 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5814
5815 /* !!! these should become driver const once
5816 rf-tool supports split-68 const */
5817 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5818 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5819 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5820 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5821 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5822 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5823 }
4477 } 5824 }
4478 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
4479 5825
4480 /* Reset PCIE errors for debug */ 5826 /* Reset PCIE errors for debug */
4481 REG_WR(bp, 0x2114, 0xffffffff); 5827 REG_WR(bp, 0x2114, 0xffffffff);
4482 REG_WR(bp, 0x2120, 0xffffffff); 5828 REG_WR(bp, 0x2120, 0xffffffff);
4483 5829
5830 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5831 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5832 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5833 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5834 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5835 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5836
5837 if (CHIP_IS_E1x(bp)) {
5838 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5839 main_mem_base = HC_REG_MAIN_MEMORY +
5840 BP_PORT(bp) * (main_mem_size * 4);
5841 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5842 main_mem_width = 8;
5843
5844 val = REG_RD(bp, main_mem_prty_clr);
5845 if (val)
5846 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5847 "block during "
5848 "function init (0x%x)!\n", val);
5849
5850 /* Clear "false" parity errors in MSI-X table */
5851 for (i = main_mem_base;
5852 i < main_mem_base + main_mem_size * 4;
5853 i += main_mem_width) {
5854 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5855 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5856 i, main_mem_width / 4);
5857 }
5858 /* Clear HC parity attention */
5859 REG_RD(bp, main_mem_prty_clr);
5860 }
5861
5862 bnx2x_phy_probe(&bp->link_params);
5863
4484 return 0; 5864 return 0;
4485} 5865}
4486 5866
4487int bnx2x_init_hw(struct bnx2x *bp, u32 load_code) 5867int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
4488{ 5868{
4489 int i, rc = 0; 5869 int rc = 0;
4490 5870
4491 DP(BNX2X_MSG_MCP, "function %d load_code %x\n", 5871 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
4492 BP_FUNC(bp), load_code); 5872 BP_ABS_FUNC(bp), load_code);
4493 5873
4494 bp->dmae_ready = 0; 5874 bp->dmae_ready = 0;
4495 mutex_init(&bp->dmae_mutex); 5875 spin_lock_init(&bp->dmae_lock);
4496 rc = bnx2x_gunzip_init(bp);
4497 if (rc)
4498 return rc;
4499 5876
4500 switch (load_code) { 5877 switch (load_code) {
4501 case FW_MSG_CODE_DRV_LOAD_COMMON: 5878 case FW_MSG_CODE_DRV_LOAD_COMMON:
4502 rc = bnx2x_init_common(bp); 5879 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5880 rc = bnx2x_init_hw_common(bp, load_code);
4503 if (rc) 5881 if (rc)
4504 goto init_hw_err; 5882 goto init_hw_err;
4505 /* no break */ 5883 /* no break */
4506 5884
4507 case FW_MSG_CODE_DRV_LOAD_PORT: 5885 case FW_MSG_CODE_DRV_LOAD_PORT:
4508 bp->dmae_ready = 1; 5886 rc = bnx2x_init_hw_port(bp);
4509 rc = bnx2x_init_port(bp);
4510 if (rc) 5887 if (rc)
4511 goto init_hw_err; 5888 goto init_hw_err;
4512 /* no break */ 5889 /* no break */
4513 5890
4514 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 5891 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4515 bp->dmae_ready = 1; 5892 rc = bnx2x_init_hw_func(bp);
4516 rc = bnx2x_init_func(bp);
4517 if (rc) 5893 if (rc)
4518 goto init_hw_err; 5894 goto init_hw_err;
4519 break; 5895 break;
@@ -4524,22 +5900,14 @@ int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
4524 } 5900 }
4525 5901
4526 if (!BP_NOMCP(bp)) { 5902 if (!BP_NOMCP(bp)) {
4527 int func = BP_FUNC(bp); 5903 int mb_idx = BP_FW_MB_IDX(bp);
4528 5904
4529 bp->fw_drv_pulse_wr_seq = 5905 bp->fw_drv_pulse_wr_seq =
4530 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) & 5906 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
4531 DRV_PULSE_SEQ_MASK); 5907 DRV_PULSE_SEQ_MASK);
4532 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq); 5908 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
4533 } 5909 }
4534 5910
4535 /* this needs to be done before gunzip end */
4536 bnx2x_zero_def_sb(bp);
4537 for_each_queue(bp, i)
4538 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
4539#ifdef BCM_CNIC
4540 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
4541#endif
4542
4543init_hw_err: 5911init_hw_err:
4544 bnx2x_gunzip_end(bp); 5912 bnx2x_gunzip_end(bp);
4545 5913
@@ -4548,288 +5916,153 @@ init_hw_err:
4548 5916
4549void bnx2x_free_mem(struct bnx2x *bp) 5917void bnx2x_free_mem(struct bnx2x *bp)
4550{ 5918{
4551 5919 bnx2x_gunzip_end(bp);
4552#define BNX2X_PCI_FREE(x, y, size) \
4553 do { \
4554 if (x) { \
4555 dma_free_coherent(&bp->pdev->dev, size, x, y); \
4556 x = NULL; \
4557 y = 0; \
4558 } \
4559 } while (0)
4560
4561#define BNX2X_FREE(x) \
4562 do { \
4563 if (x) { \
4564 vfree(x); \
4565 x = NULL; \
4566 } \
4567 } while (0)
4568
4569 int i;
4570 5920
4571 /* fastpath */ 5921 /* fastpath */
4572 /* Common */ 5922 bnx2x_free_fp_mem(bp);
4573 for_each_queue(bp, i) {
4574
4575 /* status blocks */
4576 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
4577 bnx2x_fp(bp, i, status_blk_mapping),
4578 sizeof(struct host_status_block));
4579 }
4580 /* Rx */
4581 for_each_queue(bp, i) {
4582
4583 /* fastpath rx rings: rx_buf rx_desc rx_comp */
4584 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
4585 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
4586 bnx2x_fp(bp, i, rx_desc_mapping),
4587 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4588
4589 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
4590 bnx2x_fp(bp, i, rx_comp_mapping),
4591 sizeof(struct eth_fast_path_rx_cqe) *
4592 NUM_RCQ_BD);
4593
4594 /* SGE ring */
4595 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
4596 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
4597 bnx2x_fp(bp, i, rx_sge_mapping),
4598 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4599 }
4600 /* Tx */
4601 for_each_queue(bp, i) {
4602
4603 /* fastpath tx rings: tx_buf tx_desc */
4604 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
4605 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
4606 bnx2x_fp(bp, i, tx_desc_mapping),
4607 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4608 }
4609 /* end of fastpath */ 5923 /* end of fastpath */
4610 5924
4611 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 5925 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
4612 sizeof(struct host_def_status_block)); 5926 sizeof(struct host_sp_status_block));
4613 5927
4614 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 5928 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
4615 sizeof(struct bnx2x_slowpath)); 5929 sizeof(struct bnx2x_slowpath));
4616 5930
5931 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5932 bp->context.size);
5933
5934 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5935
5936 BNX2X_FREE(bp->ilt->lines);
5937
4617#ifdef BCM_CNIC 5938#ifdef BCM_CNIC
4618 BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024); 5939 if (CHIP_IS_E2(bp))
4619 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024); 5940 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
4620 BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024); 5941 sizeof(struct host_hc_status_block_e2));
4621 BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024); 5942 else
4622 BNX2X_PCI_FREE(bp->cnic_sb, bp->cnic_sb_mapping, 5943 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
4623 sizeof(struct host_status_block)); 5944 sizeof(struct host_hc_status_block_e1x));
5945
5946 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
4624#endif 5947#endif
5948
4625 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 5949 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
4626 5950
4627#undef BNX2X_PCI_FREE 5951 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
4628#undef BNX2X_KFREE 5952 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5953
5954 BNX2X_FREE(bp->rx_indir_table);
4629} 5955}
4630 5956
5957
4631int bnx2x_alloc_mem(struct bnx2x *bp) 5958int bnx2x_alloc_mem(struct bnx2x *bp)
4632{ 5959{
5960 if (bnx2x_gunzip_init(bp))
5961 return -ENOMEM;
4633 5962
4634#define BNX2X_PCI_ALLOC(x, y, size) \ 5963#ifdef BCM_CNIC
4635 do { \ 5964 if (CHIP_IS_E2(bp))
4636 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 5965 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
4637 if (x == NULL) \ 5966 sizeof(struct host_hc_status_block_e2));
4638 goto alloc_mem_err; \ 5967 else
4639 memset(x, 0, size); \ 5968 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
4640 } while (0) 5969 sizeof(struct host_hc_status_block_e1x));
4641
4642#define BNX2X_ALLOC(x, size) \
4643 do { \
4644 x = vmalloc(size); \
4645 if (x == NULL) \
4646 goto alloc_mem_err; \
4647 memset(x, 0, size); \
4648 } while (0)
4649
4650 int i;
4651
4652 /* fastpath */
4653 /* Common */
4654 for_each_queue(bp, i) {
4655 bnx2x_fp(bp, i, bp) = bp;
4656 5970
4657 /* status blocks */ 5971 /* allocate searcher T2 table */
4658 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk), 5972 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
4659 &bnx2x_fp(bp, i, status_blk_mapping), 5973#endif
4660 sizeof(struct host_status_block));
4661 }
4662 /* Rx */
4663 for_each_queue(bp, i) {
4664
4665 /* fastpath rx rings: rx_buf rx_desc rx_comp */
4666 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
4667 sizeof(struct sw_rx_bd) * NUM_RX_BD);
4668 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
4669 &bnx2x_fp(bp, i, rx_desc_mapping),
4670 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4671
4672 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
4673 &bnx2x_fp(bp, i, rx_comp_mapping),
4674 sizeof(struct eth_fast_path_rx_cqe) *
4675 NUM_RCQ_BD);
4676
4677 /* SGE ring */
4678 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
4679 sizeof(struct sw_rx_page) * NUM_RX_SGE);
4680 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
4681 &bnx2x_fp(bp, i, rx_sge_mapping),
4682 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4683 }
4684 /* Tx */
4685 for_each_queue(bp, i) {
4686 5974
4687 /* fastpath tx rings: tx_buf tx_desc */
4688 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
4689 sizeof(struct sw_tx_bd) * NUM_TX_BD);
4690 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
4691 &bnx2x_fp(bp, i, tx_desc_mapping),
4692 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4693 }
4694 /* end of fastpath */
4695 5975
4696 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping, 5976 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
4697 sizeof(struct host_def_status_block)); 5977 sizeof(struct host_sp_status_block));
4698 5978
4699 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping, 5979 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
4700 sizeof(struct bnx2x_slowpath)); 5980 sizeof(struct bnx2x_slowpath));
4701 5981
4702#ifdef BCM_CNIC 5982 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
4703 BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
4704
4705 /* allocate searcher T2 table
4706 we allocate 1/4 of alloc num for T2
4707 (which is not entered into the ILT) */
4708 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
4709
4710 /* Initialize T2 (for 1024 connections) */
4711 for (i = 0; i < 16*1024; i += 64)
4712 *(u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
4713 5983
4714 /* Timer block array (8*MAX_CONN) phys uncached for now 1024 conns */ 5984 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
4715 BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024); 5985 bp->context.size);
4716 5986
4717 /* QM queues (128*MAX_CONN) */ 5987 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
4718 BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
4719 5988
4720 BNX2X_PCI_ALLOC(bp->cnic_sb, &bp->cnic_sb_mapping, 5989 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
4721 sizeof(struct host_status_block)); 5990 goto alloc_mem_err;
4722#endif
4723 5991
4724 /* Slow path ring */ 5992 /* Slow path ring */
4725 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE); 5993 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
4726 5994
5995 /* EQ */
5996 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
5997 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5998
5999 BNX2X_ALLOC(bp->rx_indir_table, sizeof(bp->rx_indir_table[0]) *
6000 TSTORM_INDIRECTION_TABLE_SIZE);
6001
6002 /* fastpath */
6003 /* need to be done at the end, since it's self adjusting to amount
6004 * of memory available for RSS queues
6005 */
6006 if (bnx2x_alloc_fp_mem(bp))
6007 goto alloc_mem_err;
4727 return 0; 6008 return 0;
4728 6009
4729alloc_mem_err: 6010alloc_mem_err:
4730 bnx2x_free_mem(bp); 6011 bnx2x_free_mem(bp);
4731 return -ENOMEM; 6012 return -ENOMEM;
4732
4733#undef BNX2X_PCI_ALLOC
4734#undef BNX2X_ALLOC
4735} 6013}
4736 6014
4737
4738/* 6015/*
4739 * Init service functions 6016 * Init service functions
4740 */ 6017 */
6018static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6019 int *state_p, int flags);
4741 6020
4742/** 6021int bnx2x_func_start(struct bnx2x *bp)
4743 * Sets a MAC in a CAM for a few L2 Clients for E1 chip
4744 *
4745 * @param bp driver descriptor
4746 * @param set set or clear an entry (1 or 0)
4747 * @param mac pointer to a buffer containing a MAC
4748 * @param cl_bit_vec bit vector of clients to register a MAC for
4749 * @param cam_offset offset in a CAM to use
4750 * @param with_bcast set broadcast MAC as well
4751 */
4752static void bnx2x_set_mac_addr_e1_gen(struct bnx2x *bp, int set, u8 *mac,
4753 u32 cl_bit_vec, u8 cam_offset,
4754 u8 with_bcast)
4755{ 6022{
4756 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config); 6023 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
4757 int port = BP_PORT(bp);
4758
4759 /* CAM allocation
4760 * unicasts 0-31:port0 32-63:port1
4761 * multicast 64-127:port0 128-191:port1
4762 */
4763 config->hdr.length = 1 + (with_bcast ? 1 : 0);
4764 config->hdr.offset = cam_offset;
4765 config->hdr.client_id = 0xff;
4766 config->hdr.reserved1 = 0;
4767 6024
4768 /* primary MAC */ 6025 /* Wait for completion */
4769 config->config_table[0].cam_entry.msb_mac_addr = 6026 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
4770 swab16(*(u16 *)&mac[0]); 6027 WAIT_RAMROD_COMMON);
4771 config->config_table[0].cam_entry.middle_mac_addr = 6028}
4772 swab16(*(u16 *)&mac[2]);
4773 config->config_table[0].cam_entry.lsb_mac_addr =
4774 swab16(*(u16 *)&mac[4]);
4775 config->config_table[0].cam_entry.flags = cpu_to_le16(port);
4776 if (set)
4777 config->config_table[0].target_table_entry.flags = 0;
4778 else
4779 CAM_INVALIDATE(config->config_table[0]);
4780 config->config_table[0].target_table_entry.clients_bit_vector =
4781 cpu_to_le32(cl_bit_vec);
4782 config->config_table[0].target_table_entry.vlan_id = 0;
4783 6029
4784 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n", 6030static int bnx2x_func_stop(struct bnx2x *bp)
4785 (set ? "setting" : "clearing"), 6031{
4786 config->config_table[0].cam_entry.msb_mac_addr, 6032 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
4787 config->config_table[0].cam_entry.middle_mac_addr,
4788 config->config_table[0].cam_entry.lsb_mac_addr);
4789
4790 /* broadcast */
4791 if (with_bcast) {
4792 config->config_table[1].cam_entry.msb_mac_addr =
4793 cpu_to_le16(0xffff);
4794 config->config_table[1].cam_entry.middle_mac_addr =
4795 cpu_to_le16(0xffff);
4796 config->config_table[1].cam_entry.lsb_mac_addr =
4797 cpu_to_le16(0xffff);
4798 config->config_table[1].cam_entry.flags = cpu_to_le16(port);
4799 if (set)
4800 config->config_table[1].target_table_entry.flags =
4801 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
4802 else
4803 CAM_INVALIDATE(config->config_table[1]);
4804 config->config_table[1].target_table_entry.clients_bit_vector =
4805 cpu_to_le32(cl_bit_vec);
4806 config->config_table[1].target_table_entry.vlan_id = 0;
4807 }
4808 6033
4809 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, 6034 /* Wait for completion */
4810 U64_HI(bnx2x_sp_mapping(bp, mac_config)), 6035 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
4811 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); 6036 0, &(bp->state), WAIT_RAMROD_COMMON);
4812} 6037}
4813 6038
4814/** 6039/**
4815 * Sets a MAC in a CAM for a few L2 Clients for E1H chip 6040 * bnx2x_set_mac_addr_gen - set a MAC in a CAM for a few L2 Clients for E1x chips
4816 * 6041 *
4817 * @param bp driver descriptor 6042 * @bp: driver handle
4818 * @param set set or clear an entry (1 or 0) 6043 * @set: set or clear an entry (1 or 0)
4819 * @param mac pointer to a buffer containing a MAC 6044 * @mac: pointer to a buffer containing a MAC
4820 * @param cl_bit_vec bit vector of clients to register a MAC for 6045 * @cl_bit_vec: bit vector of clients to register a MAC for
4821 * @param cam_offset offset in a CAM to use 6046 * @cam_offset: offset in a CAM to use
6047 * @is_bcast: is the set MAC a broadcast address (for E1 only)
4822 */ 6048 */
4823static void bnx2x_set_mac_addr_e1h_gen(struct bnx2x *bp, int set, u8 *mac, 6049static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
4824 u32 cl_bit_vec, u8 cam_offset) 6050 u32 cl_bit_vec, u8 cam_offset,
6051 u8 is_bcast)
4825{ 6052{
4826 struct mac_configuration_cmd_e1h *config = 6053 struct mac_configuration_cmd *config =
4827 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config); 6054 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6055 int ramrod_flags = WAIT_RAMROD_COMMON;
6056
6057 bp->set_mac_pending = 1;
4828 6058
4829 config->hdr.length = 1; 6059 config->hdr.length = 1;
4830 config->hdr.offset = cam_offset; 6060 config->hdr.offset = cam_offset;
4831 config->hdr.client_id = 0xff; 6061 config->hdr.client_id = 0xff;
4832 config->hdr.reserved1 = 0; 6062 /* Mark the single MAC configuration ramrod as opposed to a
6063 * UC/MC list configuration).
6064 */
6065 config->hdr.echo = 1;
4833 6066
4834 /* primary MAC */ 6067 /* primary MAC */
4835 config->config_table[0].msb_mac_addr = 6068 config->config_table[0].msb_mac_addr =
@@ -4841,29 +6074,43 @@ static void bnx2x_set_mac_addr_e1h_gen(struct bnx2x *bp, int set, u8 *mac,
4841 config->config_table[0].clients_bit_vector = 6074 config->config_table[0].clients_bit_vector =
4842 cpu_to_le32(cl_bit_vec); 6075 cpu_to_le32(cl_bit_vec);
4843 config->config_table[0].vlan_id = 0; 6076 config->config_table[0].vlan_id = 0;
4844 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov); 6077 config->config_table[0].pf_id = BP_FUNC(bp);
4845 if (set) 6078 if (set)
4846 config->config_table[0].flags = BP_PORT(bp); 6079 SET_FLAG(config->config_table[0].flags,
6080 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6081 T_ETH_MAC_COMMAND_SET);
4847 else 6082 else
4848 config->config_table[0].flags = 6083 SET_FLAG(config->config_table[0].flags,
4849 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE; 6084 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6085 T_ETH_MAC_COMMAND_INVALIDATE);
4850 6086
4851 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID mask %d\n", 6087 if (is_bcast)
6088 SET_FLAG(config->config_table[0].flags,
6089 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6090
6091 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
4852 (set ? "setting" : "clearing"), 6092 (set ? "setting" : "clearing"),
4853 config->config_table[0].msb_mac_addr, 6093 config->config_table[0].msb_mac_addr,
4854 config->config_table[0].middle_mac_addr, 6094 config->config_table[0].middle_mac_addr,
4855 config->config_table[0].lsb_mac_addr, bp->e1hov, cl_bit_vec); 6095 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
4856 6096
4857 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, 6097 mb();
6098
6099 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
4858 U64_HI(bnx2x_sp_mapping(bp, mac_config)), 6100 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
4859 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); 6101 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6102
6103 /* Wait for a completion */
6104 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
4860} 6105}
4861 6106
4862static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx, 6107static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
4863 int *state_p, int poll) 6108 int *state_p, int flags)
4864{ 6109{
4865 /* can take a while if any port is running */ 6110 /* can take a while if any port is running */
4866 int cnt = 5000; 6111 int cnt = 5000;
6112 u8 poll = flags & WAIT_RAMROD_POLL;
6113 u8 common = flags & WAIT_RAMROD_COMMON;
4867 6114
4868 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n", 6115 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
4869 poll ? "polling" : "waiting", state, idx); 6116 poll ? "polling" : "waiting", state, idx);
@@ -4871,13 +6118,17 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
4871 might_sleep(); 6118 might_sleep();
4872 while (cnt--) { 6119 while (cnt--) {
4873 if (poll) { 6120 if (poll) {
4874 bnx2x_rx_int(bp->fp, 10); 6121 if (common)
4875 /* if index is different from 0 6122 bnx2x_eq_int(bp);
4876 * the reply for some commands will 6123 else {
4877 * be on the non default queue 6124 bnx2x_rx_int(bp->fp, 10);
4878 */ 6125 /* if index is different from 0
4879 if (idx) 6126 * the reply for some commands will
4880 bnx2x_rx_int(&bp->fp[idx], 10); 6127 * be on the non default queue
6128 */
6129 if (idx)
6130 bnx2x_rx_int(&bp->fp[idx], 10);
6131 }
4881 } 6132 }
4882 6133
4883 mb(); /* state is changed by bnx2x_sp_event() */ 6134 mb(); /* state is changed by bnx2x_sp_event() */
@@ -4904,212 +6155,781 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
4904 return -EBUSY; 6155 return -EBUSY;
4905} 6156}
4906 6157
4907void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set) 6158static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
4908{ 6159{
4909 bp->set_mac_pending++; 6160 if (CHIP_IS_E1H(bp))
4910 smp_wmb(); 6161 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6162 else if (CHIP_MODE_IS_4_PORT(bp))
6163 return E2_FUNC_MAX * rel_offset + BP_FUNC(bp);
6164 else
6165 return E2_FUNC_MAX * rel_offset + BP_VN(bp);
6166}
4911 6167
4912 bnx2x_set_mac_addr_e1h_gen(bp, set, bp->dev->dev_addr, 6168/**
4913 (1 << bp->fp->cl_id), BP_FUNC(bp)); 6169 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6170 * relevant. In addition, current implementation is tuned for a
6171 * single ETH MAC.
6172 */
6173enum {
6174 LLH_CAM_ISCSI_ETH_LINE = 0,
6175 LLH_CAM_ETH_LINE,
6176 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6177};
6178
6179static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6180 int set,
6181 unsigned char *dev_addr,
6182 int index)
6183{
6184 u32 wb_data[2];
6185 u32 mem_offset, ena_offset, mem_index;
6186 /**
6187 * indexes mapping:
6188 * 0..7 - goes to MEM
6189 * 8..15 - goes to MEM2
6190 */
6191
6192 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6193 return;
6194
6195 /* calculate memory start offset according to the mapping
6196 * and index in the memory */
6197 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6198 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6199 NIG_REG_LLH0_FUNC_MEM;
6200 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6201 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6202 mem_index = index;
6203 } else {
6204 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6205 NIG_REG_P0_LLH_FUNC_MEM2;
6206 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6207 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6208 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6209 }
6210
6211 if (set) {
6212 /* LLH_FUNC_MEM is a u64 WB register */
6213 mem_offset += 8*mem_index;
6214
6215 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6216 (dev_addr[4] << 8) | dev_addr[5]);
6217 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6218
6219 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6220 }
6221
6222 /* enable/disable the entry */
6223 REG_WR(bp, ena_offset + 4*mem_index, set);
4914 6224
4915 /* Wait for a completion */
4916 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
4917} 6225}
4918 6226
4919void bnx2x_set_eth_mac_addr_e1(struct bnx2x *bp, int set) 6227void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
4920{ 6228{
4921 bp->set_mac_pending++; 6229 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
4922 smp_wmb(); 6230 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
6231
6232 /* networking MAC */
6233 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6234 (1 << bp->fp->cl_id), cam_offset , 0);
4923 6235
4924 bnx2x_set_mac_addr_e1_gen(bp, set, bp->dev->dev_addr, 6236 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
4925 (1 << bp->fp->cl_id), (BP_PORT(bp) ? 32 : 0), 6237
4926 1); 6238 if (CHIP_IS_E1(bp)) {
6239 /* broadcast MAC */
6240 static const u8 bcast[ETH_ALEN] = {
6241 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6242 };
6243 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6244 }
6245}
6246
6247static inline u8 bnx2x_e1_cam_mc_offset(struct bnx2x *bp)
6248{
6249 return CHIP_REV_IS_SLOW(bp) ?
6250 (BNX2X_MAX_EMUL_MULTI * (1 + BP_PORT(bp))) :
6251 (BNX2X_MAX_MULTICAST * (1 + BP_PORT(bp)));
6252}
6253
6254/* set mc list, do not wait as wait implies sleep and
6255 * set_rx_mode can be invoked from non-sleepable context.
6256 *
6257 * Instead we use the same ramrod data buffer each time we need
6258 * to configure a list of addresses, and use the fact that the
6259 * list of MACs is changed in an incremental way and that the
6260 * function is called under the netif_addr_lock. A temporary
6261 * inconsistent CAM configuration (possible in case of a very fast
6262 * sequence of add/del/add on the host side) will shortly be
6263 * restored by the handler of the last ramrod.
6264 */
6265static int bnx2x_set_e1_mc_list(struct bnx2x *bp)
6266{
6267 int i = 0, old;
6268 struct net_device *dev = bp->dev;
6269 u8 offset = bnx2x_e1_cam_mc_offset(bp);
6270 struct netdev_hw_addr *ha;
6271 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6272 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6273
6274 if (netdev_mc_count(dev) > BNX2X_MAX_MULTICAST)
6275 return -EINVAL;
6276
6277 netdev_for_each_mc_addr(ha, dev) {
6278 /* copy mac */
6279 config_cmd->config_table[i].msb_mac_addr =
6280 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6281 config_cmd->config_table[i].middle_mac_addr =
6282 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6283 config_cmd->config_table[i].lsb_mac_addr =
6284 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
6285
6286 config_cmd->config_table[i].vlan_id = 0;
6287 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6288 config_cmd->config_table[i].clients_bit_vector =
6289 cpu_to_le32(1 << BP_L_ID(bp));
6290
6291 SET_FLAG(config_cmd->config_table[i].flags,
6292 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6293 T_ETH_MAC_COMMAND_SET);
6294
6295 DP(NETIF_MSG_IFUP,
6296 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6297 config_cmd->config_table[i].msb_mac_addr,
6298 config_cmd->config_table[i].middle_mac_addr,
6299 config_cmd->config_table[i].lsb_mac_addr);
6300 i++;
6301 }
6302 old = config_cmd->hdr.length;
6303 if (old > i) {
6304 for (; i < old; i++) {
6305 if (CAM_IS_INVALID(config_cmd->
6306 config_table[i])) {
6307 /* already invalidated */
6308 break;
6309 }
6310 /* invalidate */
6311 SET_FLAG(config_cmd->config_table[i].flags,
6312 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6313 T_ETH_MAC_COMMAND_INVALIDATE);
6314 }
6315 }
6316
6317 wmb();
6318
6319 config_cmd->hdr.length = i;
6320 config_cmd->hdr.offset = offset;
6321 config_cmd->hdr.client_id = 0xff;
6322 /* Mark that this ramrod doesn't use bp->set_mac_pending for
6323 * synchronization.
6324 */
6325 config_cmd->hdr.echo = 0;
6326
6327 mb();
6328
6329 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6330 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6331}
6332
6333void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp)
6334{
6335 int i;
6336 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6337 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6338 int ramrod_flags = WAIT_RAMROD_COMMON;
6339 u8 offset = bnx2x_e1_cam_mc_offset(bp);
6340
6341 for (i = 0; i < BNX2X_MAX_MULTICAST; i++)
6342 SET_FLAG(config_cmd->config_table[i].flags,
6343 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6344 T_ETH_MAC_COMMAND_INVALIDATE);
6345
6346 wmb();
6347
6348 config_cmd->hdr.length = BNX2X_MAX_MULTICAST;
6349 config_cmd->hdr.offset = offset;
6350 config_cmd->hdr.client_id = 0xff;
6351 /* We'll wait for a completion this time... */
6352 config_cmd->hdr.echo = 1;
6353
6354 bp->set_mac_pending = 1;
6355
6356 mb();
6357
6358 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6359 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
4927 6360
4928 /* Wait for a completion */ 6361 /* Wait for a completion */
4929 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1); 6362 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6363 ramrod_flags);
6364
6365}
6366
6367/* Accept one or more multicasts */
6368static int bnx2x_set_e1h_mc_list(struct bnx2x *bp)
6369{
6370 struct net_device *dev = bp->dev;
6371 struct netdev_hw_addr *ha;
6372 u32 mc_filter[MC_HASH_SIZE];
6373 u32 crc, bit, regidx;
6374 int i;
6375
6376 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
6377
6378 netdev_for_each_mc_addr(ha, dev) {
6379 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
6380 bnx2x_mc_addr(ha));
6381
6382 crc = crc32c_le(0, bnx2x_mc_addr(ha),
6383 ETH_ALEN);
6384 bit = (crc >> 24) & 0xff;
6385 regidx = bit >> 5;
6386 bit &= 0x1f;
6387 mc_filter[regidx] |= (1 << bit);
6388 }
6389
6390 for (i = 0; i < MC_HASH_SIZE; i++)
6391 REG_WR(bp, MC_HASH_OFFSET(bp, i),
6392 mc_filter[i]);
6393
6394 return 0;
6395}
6396
6397void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp)
6398{
6399 int i;
6400
6401 for (i = 0; i < MC_HASH_SIZE; i++)
6402 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
4930} 6403}
4931 6404
4932#ifdef BCM_CNIC 6405#ifdef BCM_CNIC
4933/** 6406/**
4934 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH 6407 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
4935 * MAC(s). This function will wait until the ramdord completion
4936 * returns.
4937 * 6408 *
4938 * @param bp driver handle 6409 * @bp: driver handle
4939 * @param set set or clear the CAM entry 6410 * @set: set or clear the CAM entry
4940 * 6411 *
4941 * @return 0 if cussess, -ENODEV if ramrod doesn't return. 6412 * This function will wait until the ramdord completion returns.
6413 * Return 0 if success, -ENODEV if ramrod doesn't return.
4942 */ 6414 */
4943int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set) 6415static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
4944{ 6416{
4945 u32 cl_bit_vec = (1 << BCM_ISCSI_ETH_CL_ID); 6417 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
4946 6418 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
4947 bp->set_mac_pending++; 6419 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
4948 smp_wmb(); 6420 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
6421 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
6422 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
4949 6423
4950 /* Send a SET_MAC ramrod */ 6424 /* Send a SET_MAC ramrod */
4951 if (CHIP_IS_E1(bp)) 6425 bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,
4952 bnx2x_set_mac_addr_e1_gen(bp, set, bp->iscsi_mac, 6426 cam_offset, 0);
4953 cl_bit_vec, (BP_PORT(bp) ? 32 : 0) + 2,
4954 1);
4955 else
4956 /* CAM allocation for E1H
4957 * unicasts: by func number
4958 * multicast: 20+FUNC*20, 20 each
4959 */
4960 bnx2x_set_mac_addr_e1h_gen(bp, set, bp->iscsi_mac,
4961 cl_bit_vec, E1H_FUNC_MAX + BP_FUNC(bp));
4962 6427
4963 /* Wait for a completion when setting */ 6428 bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
4964 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
4965 6429
4966 return 0; 6430 return 0;
4967} 6431}
4968#endif
4969 6432
4970int bnx2x_setup_leading(struct bnx2x *bp) 6433/**
4971{ 6434 * bnx2x_set_fip_eth_mac_addr - set FCoE L2 MAC(s)
4972 int rc; 6435 *
6436 * @bp: driver handle
6437 * @set: set or clear the CAM entry
6438 *
6439 * This function will wait until the ramrod completion returns.
6440 * Returns 0 if success, -ENODEV if ramrod doesn't return.
6441 */
6442int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6443{
6444 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6445 /**
6446 * CAM allocation for E1H
6447 * eth unicasts: by func number
6448 * iscsi: by func number
6449 * fip unicast: by func number
6450 * fip multicast: by func number
6451 */
6452 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6453 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
4973 6454
4974 /* reset IGU state */ 6455 return 0;
4975 bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); 6456}
4976 6457
4977 /* SETUP ramrod */ 6458int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
4978 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0); 6459{
6460 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
4979 6461
4980 /* Wait for completion */ 6462 /**
4981 rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0); 6463 * CAM allocation for E1H
6464 * eth unicasts: by func number
6465 * iscsi: by func number
6466 * fip unicast: by func number
6467 * fip multicast: by func number
6468 */
6469 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6470 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
4982 6471
4983 return rc; 6472 return 0;
4984} 6473}
6474#endif
4985 6475
4986int bnx2x_setup_multi(struct bnx2x *bp, int index) 6476static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
4987{ 6477 struct bnx2x_client_init_params *params,
4988 struct bnx2x_fastpath *fp = &bp->fp[index]; 6478 u8 activate,
6479 struct client_init_ramrod_data *data)
6480{
6481 /* Clear the buffer */
6482 memset(data, 0, sizeof(*data));
6483
6484 /* general */
6485 data->general.client_id = params->rxq_params.cl_id;
6486 data->general.statistics_counter_id = params->rxq_params.stat_id;
6487 data->general.statistics_en_flg =
6488 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
6489 data->general.is_fcoe_flg =
6490 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
6491 data->general.activate_flg = activate;
6492 data->general.sp_client_id = params->rxq_params.spcl_id;
6493
6494 /* Rx data */
6495 data->rx.tpa_en_flg =
6496 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6497 data->rx.vmqueue_mode_en_flg = 0;
6498 data->rx.cache_line_alignment_log_size =
6499 params->rxq_params.cache_line_log;
6500 data->rx.enable_dynamic_hc =
6501 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6502 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6503 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6504 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6505
6506 /* We don't set drop flags */
6507 data->rx.drop_ip_cs_err_flg = 0;
6508 data->rx.drop_tcp_cs_err_flg = 0;
6509 data->rx.drop_ttl0_flg = 0;
6510 data->rx.drop_udp_cs_err_flg = 0;
6511
6512 data->rx.inner_vlan_removal_enable_flg =
6513 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6514 data->rx.outer_vlan_removal_enable_flg =
6515 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6516 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6517 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6518 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6519 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6520 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6521 data->rx.bd_page_base.lo =
6522 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6523 data->rx.bd_page_base.hi =
6524 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6525 data->rx.sge_page_base.lo =
6526 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6527 data->rx.sge_page_base.hi =
6528 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6529 data->rx.cqe_page_base.lo =
6530 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6531 data->rx.cqe_page_base.hi =
6532 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6533 data->rx.is_leading_rss =
6534 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6535 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6536
6537 /* Tx data */
6538 data->tx.enforce_security_flg = 0; /* VF specific */
6539 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6540 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6541 data->tx.mtu = 0; /* VF specific */
6542 data->tx.tx_bd_page_base.lo =
6543 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6544 data->tx.tx_bd_page_base.hi =
6545 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6546
6547 /* flow control data */
6548 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6549 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6550 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6551 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6552 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6553 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6554 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6555
6556 data->fc.safc_group_num = params->txq_params.cos;
6557 data->fc.safc_group_en_flg =
6558 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
6559 data->fc.traffic_type =
6560 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6561 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
6562}
6563
6564static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6565{
6566 /* ustorm cxt validation */
6567 cxt->ustorm_ag_context.cdu_usage =
6568 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6569 ETH_CONNECTION_TYPE);
6570 /* xcontext validation */
6571 cxt->xstorm_ag_context.cdu_reserved =
6572 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6573 ETH_CONNECTION_TYPE);
6574}
6575
6576static int bnx2x_setup_fw_client(struct bnx2x *bp,
6577 struct bnx2x_client_init_params *params,
6578 u8 activate,
6579 struct client_init_ramrod_data *data,
6580 dma_addr_t data_mapping)
6581{
6582 u16 hc_usec;
6583 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6584 int ramrod_flags = 0, rc;
6585
6586 /* HC and context validation values */
6587 hc_usec = params->txq_params.hc_rate ?
6588 1000000 / params->txq_params.hc_rate : 0;
6589 bnx2x_update_coalesce_sb_index(bp,
6590 params->txq_params.fw_sb_id,
6591 params->txq_params.sb_cq_index,
6592 !(params->txq_params.flags & QUEUE_FLG_HC),
6593 hc_usec);
6594
6595 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6596
6597 hc_usec = params->rxq_params.hc_rate ?
6598 1000000 / params->rxq_params.hc_rate : 0;
6599 bnx2x_update_coalesce_sb_index(bp,
6600 params->rxq_params.fw_sb_id,
6601 params->rxq_params.sb_cq_index,
6602 !(params->rxq_params.flags & QUEUE_FLG_HC),
6603 hc_usec);
6604
6605 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6606 params->rxq_params.cid);
6607
6608 /* zero stats */
6609 if (params->txq_params.flags & QUEUE_FLG_STATS)
6610 storm_memset_xstats_zero(bp, BP_PORT(bp),
6611 params->txq_params.stat_id);
6612
6613 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6614 storm_memset_ustats_zero(bp, BP_PORT(bp),
6615 params->rxq_params.stat_id);
6616 storm_memset_tstats_zero(bp, BP_PORT(bp),
6617 params->rxq_params.stat_id);
6618 }
6619
6620 /* Fill the ramrod data */
6621 bnx2x_fill_cl_init_data(bp, params, activate, data);
6622
6623 /* SETUP ramrod.
6624 *
6625 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6626 * barrier except from mmiowb() is needed to impose a
6627 * proper ordering of memory operations.
6628 */
6629 mmiowb();
4989 6630
4990 /* reset IGU state */
4991 bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4992 6631
4993 /* SETUP ramrod */ 6632 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
4994 fp->state = BNX2X_FP_STATE_OPENING; 6633 U64_HI(data_mapping), U64_LO(data_mapping), 0);
4995 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0,
4996 fp->cl_id, 0);
4997 6634
4998 /* Wait for completion */ 6635 /* Wait for completion */
4999 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index, 6636 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
5000 &(fp->state), 0); 6637 params->ramrod_params.index,
6638 params->ramrod_params.pstate,
6639 ramrod_flags);
6640 return rc;
5001} 6641}
5002 6642
5003 6643/**
5004void bnx2x_set_num_queues_msix(struct bnx2x *bp) 6644 * bnx2x_set_int_mode - configure interrupt mode
6645 *
6646 * @bp: driver handle
6647 *
6648 * In case of MSI-X it will also try to enable MSI-X.
6649 */
6650static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
5005{ 6651{
6652 int rc = 0;
5006 6653
5007 switch (bp->multi_mode) { 6654 switch (bp->int_mode) {
5008 case ETH_RSS_MODE_DISABLED: 6655 case INT_MODE_MSI:
5009 bp->num_queues = 1; 6656 bnx2x_enable_msi(bp);
6657 /* falling through... */
6658 case INT_MODE_INTx:
6659 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6660 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
5010 break; 6661 break;
6662 default:
6663 /* Set number of queues according to bp->multi_mode value */
6664 bnx2x_set_num_queues(bp);
5011 6665
5012 case ETH_RSS_MODE_REGULAR: 6666 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
5013 if (num_queues) 6667 bp->num_queues);
5014 bp->num_queues = min_t(u32, num_queues,
5015 BNX2X_MAX_QUEUES(bp));
5016 else
5017 bp->num_queues = min_t(u32, num_online_cpus(),
5018 BNX2X_MAX_QUEUES(bp));
5019 break;
5020 6668
6669 /* if we can't use MSI-X we only need one fp,
6670 * so try to enable MSI-X with the requested number of fp's
6671 * and fallback to MSI or legacy INTx with one fp
6672 */
6673 rc = bnx2x_enable_msix(bp);
6674 if (rc) {
6675 /* failed to enable MSI-X */
6676 if (bp->multi_mode)
6677 DP(NETIF_MSG_IFUP,
6678 "Multi requested but failed to "
6679 "enable MSI-X (%d), "
6680 "set number of queues to %d\n",
6681 bp->num_queues,
6682 1 + NONE_ETH_CONTEXT_USE);
6683 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6684
6685 if (!(bp->flags & DISABLE_MSI_FLAG))
6686 bnx2x_enable_msi(bp);
6687 }
5021 6688
5022 default:
5023 bp->num_queues = 1;
5024 break; 6689 break;
5025 } 6690 }
6691
6692 return rc;
6693}
6694
6695/* must be called prioir to any HW initializations */
6696static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6697{
6698 return L2_ILT_LINES(bp);
5026} 6699}
5027 6700
6701void bnx2x_ilt_set_info(struct bnx2x *bp)
6702{
6703 struct ilt_client_info *ilt_client;
6704 struct bnx2x_ilt *ilt = BP_ILT(bp);
6705 u16 line = 0;
6706
6707 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6708 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6709
6710 /* CDU */
6711 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6712 ilt_client->client_num = ILT_CLIENT_CDU;
6713 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6714 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6715 ilt_client->start = line;
6716 line += L2_ILT_LINES(bp);
6717#ifdef BCM_CNIC
6718 line += CNIC_ILT_LINES;
6719#endif
6720 ilt_client->end = line - 1;
6721
6722 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6723 "flags 0x%x, hw psz %d\n",
6724 ilt_client->start,
6725 ilt_client->end,
6726 ilt_client->page_size,
6727 ilt_client->flags,
6728 ilog2(ilt_client->page_size >> 12));
6729
6730 /* QM */
6731 if (QM_INIT(bp->qm_cid_count)) {
6732 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6733 ilt_client->client_num = ILT_CLIENT_QM;
6734 ilt_client->page_size = QM_ILT_PAGE_SZ;
6735 ilt_client->flags = 0;
6736 ilt_client->start = line;
6737
6738 /* 4 bytes for each cid */
6739 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6740 QM_ILT_PAGE_SZ);
6741
6742 ilt_client->end = line - 1;
6743
6744 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6745 "flags 0x%x, hw psz %d\n",
6746 ilt_client->start,
6747 ilt_client->end,
6748 ilt_client->page_size,
6749 ilt_client->flags,
6750 ilog2(ilt_client->page_size >> 12));
6751
6752 }
6753 /* SRC */
6754 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6755#ifdef BCM_CNIC
6756 ilt_client->client_num = ILT_CLIENT_SRC;
6757 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6758 ilt_client->flags = 0;
6759 ilt_client->start = line;
6760 line += SRC_ILT_LINES;
6761 ilt_client->end = line - 1;
6762
6763 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6764 "flags 0x%x, hw psz %d\n",
6765 ilt_client->start,
6766 ilt_client->end,
6767 ilt_client->page_size,
6768 ilt_client->flags,
6769 ilog2(ilt_client->page_size >> 12));
6770
6771#else
6772 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6773#endif
6774
6775 /* TM */
6776 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6777#ifdef BCM_CNIC
6778 ilt_client->client_num = ILT_CLIENT_TM;
6779 ilt_client->page_size = TM_ILT_PAGE_SZ;
6780 ilt_client->flags = 0;
6781 ilt_client->start = line;
6782 line += TM_ILT_LINES;
6783 ilt_client->end = line - 1;
6784
6785 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6786 "flags 0x%x, hw psz %d\n",
6787 ilt_client->start,
6788 ilt_client->end,
6789 ilt_client->page_size,
6790 ilt_client->flags,
6791 ilog2(ilt_client->page_size >> 12));
5028 6792
6793#else
6794 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6795#endif
6796}
5029 6797
5030static int bnx2x_stop_multi(struct bnx2x *bp, int index) 6798int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6799 int is_leading)
5031{ 6800{
5032 struct bnx2x_fastpath *fp = &bp->fp[index]; 6801 struct bnx2x_client_init_params params = { {0} };
5033 int rc; 6802 int rc;
5034 6803
5035 /* halt the connection */ 6804 /* reset IGU state skip FCoE L2 queue */
5036 fp->state = BNX2X_FP_STATE_HALTING; 6805 if (!IS_FCOE_FP(fp))
5037 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, fp->cl_id, 0); 6806 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6807 IGU_INT_ENABLE, 0);
5038 6808
5039 /* Wait for completion */ 6809 params.ramrod_params.pstate = &fp->state;
5040 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index, 6810 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
5041 &(fp->state), 1); 6811 params.ramrod_params.index = fp->index;
5042 if (rc) /* timeout */ 6812 params.ramrod_params.cid = fp->cid;
5043 return rc;
5044 6813
5045 /* delete cfc entry */ 6814#ifdef BCM_CNIC
5046 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1); 6815 if (IS_FCOE_FP(fp))
6816 params.ramrod_params.flags |= CLIENT_IS_FCOE;
5047 6817
5048 /* Wait for completion */ 6818#endif
5049 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index, 6819
5050 &(fp->state), 1); 6820 if (is_leading)
6821 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
6822
6823 bnx2x_pf_rx_cl_prep(bp, fp, &params.pause, &params.rxq_params);
6824
6825 bnx2x_pf_tx_cl_prep(bp, fp, &params.txq_params);
6826
6827 rc = bnx2x_setup_fw_client(bp, &params, 1,
6828 bnx2x_sp(bp, client_init_data),
6829 bnx2x_sp_mapping(bp, client_init_data));
5051 return rc; 6830 return rc;
5052} 6831}
5053 6832
5054static int bnx2x_stop_leading(struct bnx2x *bp) 6833static int bnx2x_stop_fw_client(struct bnx2x *bp,
6834 struct bnx2x_client_ramrod_params *p)
5055{ 6835{
5056 __le16 dsb_sp_prod_idx;
5057 /* if the other port is handling traffic,
5058 this can take a lot of time */
5059 int cnt = 500;
5060 int rc; 6836 int rc;
5061 6837
5062 might_sleep(); 6838 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
5063 6839
5064 /* Send HALT ramrod */ 6840 /* halt the connection */
5065 bp->fp[0].state = BNX2X_FP_STATE_HALTING; 6841 *p->pstate = BNX2X_FP_STATE_HALTING;
5066 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, bp->fp->cl_id, 0); 6842 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6843 p->cl_id, 0);
5067 6844
5068 /* Wait for completion */ 6845 /* Wait for completion */
5069 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0, 6846 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
5070 &(bp->fp[0].state), 1); 6847 p->pstate, poll_flag);
5071 if (rc) /* timeout */ 6848 if (rc) /* timeout */
5072 return rc; 6849 return rc;
5073 6850
5074 dsb_sp_prod_idx = *bp->dsb_sp_prod; 6851 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6852 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6853 p->cl_id, 0);
6854 /* Wait for completion */
6855 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6856 p->pstate, poll_flag);
6857 if (rc) /* timeout */
6858 return rc;
5075 6859
5076 /* Send PORT_DELETE ramrod */
5077 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
5078 6860
5079 /* Wait for completion to arrive on default status block 6861 /* delete cfc entry */
5080 we are going to reset the chip anyway 6862 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
5081 so there is not much to do if this times out
5082 */
5083 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
5084 if (!cnt) {
5085 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
5086 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
5087 *bp->dsb_sp_prod, dsb_sp_prod_idx);
5088#ifdef BNX2X_STOP_ON_ERROR
5089 bnx2x_panic();
5090#endif
5091 rc = -EBUSY;
5092 break;
5093 }
5094 cnt--;
5095 msleep(1);
5096 rmb(); /* Refresh the dsb_sp_prod */
5097 }
5098 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
5099 bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
5100 6863
6864 /* Wait for completion */
6865 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6866 p->pstate, WAIT_RAMROD_COMMON);
5101 return rc; 6867 return rc;
5102} 6868}
5103 6869
6870static int bnx2x_stop_client(struct bnx2x *bp, int index)
6871{
6872 struct bnx2x_client_ramrod_params client_stop = {0};
6873 struct bnx2x_fastpath *fp = &bp->fp[index];
6874
6875 client_stop.index = index;
6876 client_stop.cid = fp->cid;
6877 client_stop.cl_id = fp->cl_id;
6878 client_stop.pstate = &(fp->state);
6879 client_stop.poll = 0;
6880
6881 return bnx2x_stop_fw_client(bp, &client_stop);
6882}
6883
6884
5104static void bnx2x_reset_func(struct bnx2x *bp) 6885static void bnx2x_reset_func(struct bnx2x *bp)
5105{ 6886{
5106 int port = BP_PORT(bp); 6887 int port = BP_PORT(bp);
5107 int func = BP_FUNC(bp); 6888 int func = BP_FUNC(bp);
5108 int base, i; 6889 int i;
6890 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
6891 (CHIP_IS_E2(bp) ?
6892 offsetof(struct hc_status_block_data_e2, common) :
6893 offsetof(struct hc_status_block_data_e1x, common));
6894 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6895 int pfid_offset = offsetof(struct pci_entity, pf_id);
6896
6897 /* Disable the function in the FW */
6898 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6899 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6900 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6901 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6902
6903 /* FP SBs */
6904 for_each_eth_queue(bp, i) {
6905 struct bnx2x_fastpath *fp = &bp->fp[i];
6906 REG_WR8(bp,
6907 BAR_CSTRORM_INTMEM +
6908 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6909 + pfunc_offset_fp + pfid_offset,
6910 HC_FUNCTION_DISABLED);
6911 }
6912
6913 /* SP SB */
6914 REG_WR8(bp,
6915 BAR_CSTRORM_INTMEM +
6916 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6917 pfunc_offset_sp + pfid_offset,
6918 HC_FUNCTION_DISABLED);
6919
6920
6921 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6922 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6923 0);
5109 6924
5110 /* Configure IGU */ 6925 /* Configure IGU */
5111 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 6926 if (bp->common.int_block == INT_BLOCK_HC) {
5112 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 6927 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6928 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6929 } else {
6930 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6931 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6932 }
5113 6933
5114#ifdef BCM_CNIC 6934#ifdef BCM_CNIC
5115 /* Disable Timer scan */ 6935 /* Disable Timer scan */
@@ -5125,9 +6945,27 @@ static void bnx2x_reset_func(struct bnx2x *bp)
5125 } 6945 }
5126#endif 6946#endif
5127 /* Clear ILT */ 6947 /* Clear ILT */
5128 base = FUNC_ILT_BASE(func); 6948 bnx2x_clear_func_ilt(bp, func);
5129 for (i = base; i < base + ILT_PER_FUNC; i++) 6949
5130 bnx2x_ilt_wr(bp, i, 0); 6950 /* Timers workaround bug for E2: if this is vnic-3,
6951 * we need to set the entire ilt range for this timers.
6952 */
6953 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6954 struct ilt_client_info ilt_cli;
6955 /* use dummy TM client */
6956 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6957 ilt_cli.start = 0;
6958 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6959 ilt_cli.client_num = ILT_CLIENT_TM;
6960
6961 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
6962 }
6963
6964 /* this assumes that reset_port() called before reset_func()*/
6965 if (CHIP_IS_E2(bp))
6966 bnx2x_pf_disable(bp);
6967
6968 bp->dmae_ready = 0;
5131} 6969}
5132 6970
5133static void bnx2x_reset_port(struct bnx2x *bp) 6971static void bnx2x_reset_port(struct bnx2x *bp)
@@ -5159,7 +6997,7 @@ static void bnx2x_reset_port(struct bnx2x *bp)
5159static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code) 6997static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
5160{ 6998{
5161 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n", 6999 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
5162 BP_FUNC(bp), reset_code); 7000 BP_ABS_FUNC(bp), reset_code);
5163 7001
5164 switch (reset_code) { 7002 switch (reset_code) {
5165 case FW_MSG_CODE_DRV_UNLOAD_COMMON: 7003 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
@@ -5183,6 +7021,20 @@ static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
5183 } 7021 }
5184} 7022}
5185 7023
7024#ifdef BCM_CNIC
7025static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7026{
7027 if (bp->flags & FCOE_MACS_SET) {
7028 if (!IS_MF_SD(bp))
7029 bnx2x_set_fip_eth_mac_addr(bp, 0);
7030
7031 bnx2x_set_all_enode_macs(bp, 0);
7032
7033 bp->flags &= ~FCOE_MACS_SET;
7034 }
7035}
7036#endif
7037
5186void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode) 7038void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
5187{ 7039{
5188 int port = BP_PORT(bp); 7040 int port = BP_PORT(bp);
@@ -5190,13 +7042,12 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
5190 int i, cnt, rc; 7042 int i, cnt, rc;
5191 7043
5192 /* Wait until tx fastpath tasks complete */ 7044 /* Wait until tx fastpath tasks complete */
5193 for_each_queue(bp, i) { 7045 for_each_tx_queue(bp, i) {
5194 struct bnx2x_fastpath *fp = &bp->fp[i]; 7046 struct bnx2x_fastpath *fp = &bp->fp[i];
5195 7047
5196 cnt = 1000; 7048 cnt = 1000;
5197 while (bnx2x_has_tx_work_unload(fp)) { 7049 while (bnx2x_has_tx_work_unload(fp)) {
5198 7050
5199 bnx2x_tx_int(fp);
5200 if (!cnt) { 7051 if (!cnt) {
5201 BNX2X_ERR("timeout waiting for queue[%d]\n", 7052 BNX2X_ERR("timeout waiting for queue[%d]\n",
5202 i); 7053 i);
@@ -5214,48 +7065,19 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
5214 /* Give HW time to discard old tx messages */ 7065 /* Give HW time to discard old tx messages */
5215 msleep(1); 7066 msleep(1);
5216 7067
5217 if (CHIP_IS_E1(bp)) { 7068 bnx2x_set_eth_mac(bp, 0);
5218 struct mac_configuration_cmd *config =
5219 bnx2x_sp(bp, mcast_config);
5220
5221 bnx2x_set_eth_mac_addr_e1(bp, 0);
5222
5223 for (i = 0; i < config->hdr.length; i++)
5224 CAM_INVALIDATE(config->config_table[i]);
5225
5226 config->hdr.length = i;
5227 if (CHIP_REV_IS_SLOW(bp))
5228 config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
5229 else
5230 config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
5231 config->hdr.client_id = bp->fp->cl_id;
5232 config->hdr.reserved1 = 0;
5233 7069
5234 bp->set_mac_pending++; 7070 bnx2x_invalidate_uc_list(bp);
5235 smp_wmb();
5236 7071
5237 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, 7072 if (CHIP_IS_E1(bp))
5238 U64_HI(bnx2x_sp_mapping(bp, mcast_config)), 7073 bnx2x_invalidate_e1_mc_list(bp);
5239 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0); 7074 else {
5240 7075 bnx2x_invalidate_e1h_mc_list(bp);
5241 } else { /* E1H */
5242 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7076 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
5243
5244 bnx2x_set_eth_mac_addr_e1h(bp, 0);
5245
5246 for (i = 0; i < MC_HASH_SIZE; i++)
5247 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
5248
5249 REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
5250 } 7077 }
7078
5251#ifdef BCM_CNIC 7079#ifdef BCM_CNIC
5252 /* Clear iSCSI L2 MAC */ 7080 bnx2x_del_fcoe_eth_macs(bp);
5253 mutex_lock(&bp->cnic_mutex);
5254 if (bp->cnic_flags & BNX2X_CNIC_FLAG_MAC_SET) {
5255 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
5256 bp->cnic_flags &= ~BNX2X_CNIC_FLAG_MAC_SET;
5257 }
5258 mutex_unlock(&bp->cnic_mutex);
5259#endif 7081#endif
5260 7082
5261 if (unload_mode == UNLOAD_NORMAL) 7083 if (unload_mode == UNLOAD_NORMAL)
@@ -5286,33 +7108,44 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
5286 7108
5287 /* Close multi and leading connections 7109 /* Close multi and leading connections
5288 Completions for ramrods are collected in a synchronous way */ 7110 Completions for ramrods are collected in a synchronous way */
5289 for_each_nondefault_queue(bp, i) 7111 for_each_queue(bp, i)
5290 if (bnx2x_stop_multi(bp, i)) 7112
7113 if (bnx2x_stop_client(bp, i))
7114#ifdef BNX2X_STOP_ON_ERROR
7115 return;
7116#else
5291 goto unload_error; 7117 goto unload_error;
7118#endif
5292 7119
5293 rc = bnx2x_stop_leading(bp); 7120 rc = bnx2x_func_stop(bp);
5294 if (rc) { 7121 if (rc) {
5295 BNX2X_ERR("Stop leading failed!\n"); 7122 BNX2X_ERR("Function stop failed!\n");
5296#ifdef BNX2X_STOP_ON_ERROR 7123#ifdef BNX2X_STOP_ON_ERROR
5297 return -EBUSY; 7124 return;
5298#else 7125#else
5299 goto unload_error; 7126 goto unload_error;
5300#endif 7127#endif
5301 } 7128 }
5302 7129#ifndef BNX2X_STOP_ON_ERROR
5303unload_error: 7130unload_error:
7131#endif
5304 if (!BP_NOMCP(bp)) 7132 if (!BP_NOMCP(bp))
5305 reset_code = bnx2x_fw_command(bp, reset_code); 7133 reset_code = bnx2x_fw_command(bp, reset_code, 0);
5306 else { 7134 else {
5307 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts %d, %d, %d\n", 7135 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
5308 load_count[0], load_count[1], load_count[2]); 7136 "%d, %d, %d\n", BP_PATH(bp),
5309 load_count[0]--; 7137 load_count[BP_PATH(bp)][0],
5310 load_count[1 + port]--; 7138 load_count[BP_PATH(bp)][1],
5311 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts %d, %d, %d\n", 7139 load_count[BP_PATH(bp)][2]);
5312 load_count[0], load_count[1], load_count[2]); 7140 load_count[BP_PATH(bp)][0]--;
5313 if (load_count[0] == 0) 7141 load_count[BP_PATH(bp)][1 + port]--;
7142 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7143 "%d, %d, %d\n", BP_PATH(bp),
7144 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7145 load_count[BP_PATH(bp)][2]);
7146 if (load_count[BP_PATH(bp)][0] == 0)
5314 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7147 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
5315 else if (load_count[1 + port] == 0) 7148 else if (load_count[BP_PATH(bp)][1 + port] == 0)
5316 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 7149 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
5317 else 7150 else
5318 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 7151 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
@@ -5322,12 +7155,18 @@ unload_error:
5322 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT)) 7155 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
5323 bnx2x__link_reset(bp); 7156 bnx2x__link_reset(bp);
5324 7157
7158 /* Disable HW interrupts, NAPI */
7159 bnx2x_netif_stop(bp, 1);
7160
7161 /* Release IRQs */
7162 bnx2x_free_irq(bp);
7163
5325 /* Reset the chip */ 7164 /* Reset the chip */
5326 bnx2x_reset_chip(bp, reset_code); 7165 bnx2x_reset_chip(bp, reset_code);
5327 7166
5328 /* Report UNLOAD_DONE to MCP */ 7167 /* Report UNLOAD_DONE to MCP */
5329 if (!BP_NOMCP(bp)) 7168 if (!BP_NOMCP(bp))
5330 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); 7169 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
5331 7170
5332} 7171}
5333 7172
@@ -5353,7 +7192,6 @@ void bnx2x_disable_close_the_gate(struct bnx2x *bp)
5353 } 7192 }
5354} 7193}
5355 7194
5356
5357/* Close gates #2, #3 and #4: */ 7195/* Close gates #2, #3 and #4: */
5358static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 7196static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
5359{ 7197{
@@ -5391,26 +7229,27 @@ static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
5391 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 7229 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5392} 7230}
5393 7231
5394/* Restore the value of the `magic' bit. 7232/**
7233 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
5395 * 7234 *
5396 * @param pdev Device handle. 7235 * @bp: driver handle
5397 * @param magic_val Old value of the `magic' bit. 7236 * @magic_val: old value of the `magic' bit.
5398 */ 7237 */
5399static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 7238static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
5400{ 7239{
5401 /* Restore the `magic' bit value... */ 7240 /* Restore the `magic' bit value... */
5402 /* u32 val = SHMEM_RD(bp, mf_cfg.shared_mf_config.clp_mb);
5403 SHMEM_WR(bp, mf_cfg.shared_mf_config.clp_mb,
5404 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); */
5405 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 7241 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
5406 MF_CFG_WR(bp, shared_mf_config.clp_mb, 7242 MF_CFG_WR(bp, shared_mf_config.clp_mb,
5407 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 7243 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5408} 7244}
5409 7245
5410/* Prepares for MCP reset: takes care of CLP configurations. 7246/**
7247 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7248 *
7249 * @bp: driver handle
7250 * @magic_val: old value of 'magic' bit.
5411 * 7251 *
5412 * @param bp 7252 * Takes care of CLP configurations.
5413 * @param magic_val Old value of 'magic' bit.
5414 */ 7253 */
5415static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 7254static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
5416{ 7255{
@@ -5435,10 +7274,10 @@ static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
5435#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 7274#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
5436#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 7275#define MCP_ONE_TIMEOUT 100 /* 100 ms */
5437 7276
5438/* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10, 7277/**
5439 * depending on the HW type. 7278 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
5440 * 7279 *
5441 * @param bp 7280 * @bp: driver handle
5442 */ 7281 */
5443static inline void bnx2x_mcp_wait_one(struct bnx2x *bp) 7282static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
5444{ 7283{
@@ -5450,51 +7289,35 @@ static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
5450 msleep(MCP_ONE_TIMEOUT); 7289 msleep(MCP_ONE_TIMEOUT);
5451} 7290}
5452 7291
5453static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 7292/*
7293 * initializes bp->common.shmem_base and waits for validity signature to appear
7294 */
7295static int bnx2x_init_shmem(struct bnx2x *bp)
5454{ 7296{
5455 u32 shmem, cnt, validity_offset, val; 7297 int cnt = 0;
5456 int rc = 0; 7298 u32 val = 0;
5457
5458 msleep(100);
5459
5460 /* Get shmem offset */
5461 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
5462 if (shmem == 0) {
5463 BNX2X_ERR("Shmem 0 return failure\n");
5464 rc = -ENOTTY;
5465 goto exit_lbl;
5466 }
5467 7299
5468 validity_offset = offsetof(struct shmem_region, validity_map[0]); 7300 do {
7301 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7302 if (bp->common.shmem_base) {
7303 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7304 if (val & SHR_MEM_VALIDITY_MB)
7305 return 0;
7306 }
5469 7307
5470 /* Wait for MCP to come up */ 7308 bnx2x_mcp_wait_one(bp);
5471 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
5472 /* TBD: its best to check validity map of last port.
5473 * currently checks on port 0.
5474 */
5475 val = REG_RD(bp, shmem + validity_offset);
5476 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
5477 shmem + validity_offset, val);
5478 7309
5479 /* check that shared memory is valid. */ 7310 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
5480 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
5481 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
5482 break;
5483 7311
5484 bnx2x_mcp_wait_one(bp); 7312 BNX2X_ERR("BAD MCP validity signature\n");
5485 }
5486 7313
5487 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val); 7314 return -ENODEV;
7315}
5488 7316
5489 /* Check that shared memory is valid. This indicates that MCP is up. */ 7317static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
5490 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) != 7318{
5491 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) { 7319 int rc = bnx2x_init_shmem(bp);
5492 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
5493 rc = -ENOTTY;
5494 goto exit_lbl;
5495 }
5496 7320
5497exit_lbl:
5498 /* Restore the `magic' bit value */ 7321 /* Restore the `magic' bit value */
5499 if (!CHIP_IS_E1(bp)) 7322 if (!CHIP_IS_E1(bp))
5500 bnx2x_clp_reset_done(bp, magic_val); 7323 bnx2x_clp_reset_done(bp, magic_val);
@@ -5805,39 +7628,23 @@ reset_task_exit:
5805 * Init service functions 7628 * Init service functions
5806 */ 7629 */
5807 7630
5808static inline u32 bnx2x_get_pretend_reg(struct bnx2x *bp, int func) 7631static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
5809{ 7632{
5810 switch (func) { 7633 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
5811 case 0: return PXP2_REG_PGL_PRETEND_FUNC_F0; 7634 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
5812 case 1: return PXP2_REG_PGL_PRETEND_FUNC_F1; 7635 return base + (BP_ABS_FUNC(bp)) * stride;
5813 case 2: return PXP2_REG_PGL_PRETEND_FUNC_F2;
5814 case 3: return PXP2_REG_PGL_PRETEND_FUNC_F3;
5815 case 4: return PXP2_REG_PGL_PRETEND_FUNC_F4;
5816 case 5: return PXP2_REG_PGL_PRETEND_FUNC_F5;
5817 case 6: return PXP2_REG_PGL_PRETEND_FUNC_F6;
5818 case 7: return PXP2_REG_PGL_PRETEND_FUNC_F7;
5819 default:
5820 BNX2X_ERR("Unsupported function index: %d\n", func);
5821 return (u32)(-1);
5822 }
5823} 7636}
5824 7637
5825static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp, int orig_func) 7638static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
5826{ 7639{
5827 u32 reg = bnx2x_get_pretend_reg(bp, orig_func), new_val; 7640 u32 reg = bnx2x_get_pretend_reg(bp);
5828 7641
5829 /* Flush all outstanding writes */ 7642 /* Flush all outstanding writes */
5830 mmiowb(); 7643 mmiowb();
5831 7644
5832 /* Pretend to be function 0 */ 7645 /* Pretend to be function 0 */
5833 REG_WR(bp, reg, 0); 7646 REG_WR(bp, reg, 0);
5834 /* Flush the GRC transaction (in the chip) */ 7647 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
5835 new_val = REG_RD(bp, reg);
5836 if (new_val != 0) {
5837 BNX2X_ERR("Hmmm... Pretend register wasn't updated: (0,%d)!\n",
5838 new_val);
5839 BUG();
5840 }
5841 7648
5842 /* From now we are in the "like-E1" mode */ 7649 /* From now we are in the "like-E1" mode */
5843 bnx2x_int_disable(bp); 7650 bnx2x_int_disable(bp);
@@ -5845,22 +7652,17 @@ static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp, int orig_func)
5845 /* Flush all outstanding writes */ 7652 /* Flush all outstanding writes */
5846 mmiowb(); 7653 mmiowb();
5847 7654
5848 /* Restore the original funtion settings */ 7655 /* Restore the original function */
5849 REG_WR(bp, reg, orig_func); 7656 REG_WR(bp, reg, BP_ABS_FUNC(bp));
5850 new_val = REG_RD(bp, reg); 7657 REG_RD(bp, reg);
5851 if (new_val != orig_func) {
5852 BNX2X_ERR("Hmmm... Pretend register wasn't updated: (%d,%d)!\n",
5853 orig_func, new_val);
5854 BUG();
5855 }
5856} 7658}
5857 7659
5858static inline void bnx2x_undi_int_disable(struct bnx2x *bp, int func) 7660static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
5859{ 7661{
5860 if (CHIP_IS_E1H(bp)) 7662 if (CHIP_IS_E1(bp))
5861 bnx2x_undi_int_disable_e1h(bp, func);
5862 else
5863 bnx2x_int_disable(bp); 7663 bnx2x_int_disable(bp);
7664 else
7665 bnx2x_undi_int_disable_e1h(bp);
5864} 7666}
5865 7667
5866static void __devinit bnx2x_undi_unload(struct bnx2x *bp) 7668static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
@@ -5877,8 +7679,8 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
5877 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 7679 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
5878 if (val == 0x7) { 7680 if (val == 0x7) {
5879 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7681 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
5880 /* save our func */ 7682 /* save our pf_num */
5881 int func = BP_FUNC(bp); 7683 int orig_pf_num = bp->pf_num;
5882 u32 swap_en; 7684 u32 swap_en;
5883 u32 swap_val; 7685 u32 swap_val;
5884 7686
@@ -5888,32 +7690,33 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
5888 BNX2X_DEV_INFO("UNDI is active! reset device\n"); 7690 BNX2X_DEV_INFO("UNDI is active! reset device\n");
5889 7691
5890 /* try unload UNDI on port 0 */ 7692 /* try unload UNDI on port 0 */
5891 bp->func = 0; 7693 bp->pf_num = 0;
5892 bp->fw_seq = 7694 bp->fw_seq =
5893 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) & 7695 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
5894 DRV_MSG_SEQ_NUMBER_MASK); 7696 DRV_MSG_SEQ_NUMBER_MASK);
5895 reset_code = bnx2x_fw_command(bp, reset_code); 7697 reset_code = bnx2x_fw_command(bp, reset_code, 0);
5896 7698
5897 /* if UNDI is loaded on the other port */ 7699 /* if UNDI is loaded on the other port */
5898 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { 7700 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
5899 7701
5900 /* send "DONE" for previous unload */ 7702 /* send "DONE" for previous unload */
5901 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); 7703 bnx2x_fw_command(bp,
7704 DRV_MSG_CODE_UNLOAD_DONE, 0);
5902 7705
5903 /* unload UNDI on port 1 */ 7706 /* unload UNDI on port 1 */
5904 bp->func = 1; 7707 bp->pf_num = 1;
5905 bp->fw_seq = 7708 bp->fw_seq =
5906 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) & 7709 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
5907 DRV_MSG_SEQ_NUMBER_MASK); 7710 DRV_MSG_SEQ_NUMBER_MASK);
5908 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 7711 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
5909 7712
5910 bnx2x_fw_command(bp, reset_code); 7713 bnx2x_fw_command(bp, reset_code, 0);
5911 } 7714 }
5912 7715
5913 /* now it's safe to release the lock */ 7716 /* now it's safe to release the lock */
5914 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); 7717 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5915 7718
5916 bnx2x_undi_int_disable(bp, func); 7719 bnx2x_undi_int_disable(bp);
5917 7720
5918 /* close input traffic and wait for it */ 7721 /* close input traffic and wait for it */
5919 /* Do not rcv packets to BRB */ 7722 /* Do not rcv packets to BRB */
@@ -5949,14 +7752,13 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
5949 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); 7752 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
5950 7753
5951 /* send unload done to the MCP */ 7754 /* send unload done to the MCP */
5952 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); 7755 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
5953 7756
5954 /* restore our func and fw_seq */ 7757 /* restore our func and fw_seq */
5955 bp->func = func; 7758 bp->pf_num = orig_pf_num;
5956 bp->fw_seq = 7759 bp->fw_seq =
5957 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) & 7760 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
5958 DRV_MSG_SEQ_NUMBER_MASK); 7761 DRV_MSG_SEQ_NUMBER_MASK);
5959
5960 } else 7762 } else
5961 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); 7763 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5962 } 7764 }
@@ -5978,6 +7780,40 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
5978 val = REG_RD(bp, MISC_REG_BOND_ID); 7780 val = REG_RD(bp, MISC_REG_BOND_ID);
5979 id |= (val & 0xf); 7781 id |= (val & 0xf);
5980 bp->common.chip_id = id; 7782 bp->common.chip_id = id;
7783
7784 /* Set doorbell size */
7785 bp->db_size = (1 << BNX2X_DB_SHIFT);
7786
7787 if (CHIP_IS_E2(bp)) {
7788 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7789 if ((val & 1) == 0)
7790 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7791 else
7792 val = (val >> 1) & 1;
7793 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7794 "2_PORT_MODE");
7795 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7796 CHIP_2_PORT_MODE;
7797
7798 if (CHIP_MODE_IS_4_PORT(bp))
7799 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7800 else
7801 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7802 } else {
7803 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7804 bp->pfid = bp->pf_num; /* 0..7 */
7805 }
7806
7807 /*
7808 * set base FW non-default (fast path) status block id, this value is
7809 * used to initialize the fw_sb_id saved on the fp/queue structure to
7810 * determine the id used by the FW.
7811 */
7812 if (CHIP_IS_E1x(bp))
7813 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7814 else /* E2 */
7815 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7816
5981 bp->link_params.chip_id = bp->common.chip_id; 7817 bp->link_params.chip_id = bp->common.chip_id;
5982 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 7818 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
5983 7819
@@ -5994,25 +7830,23 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
5994 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 7830 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
5995 bp->common.flash_size, bp->common.flash_size); 7831 bp->common.flash_size, bp->common.flash_size);
5996 7832
5997 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 7833 bnx2x_init_shmem(bp);
5998 bp->common.shmem2_base = REG_RD(bp, MISC_REG_GENERIC_CR_0); 7834
7835 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7836 MISC_REG_GENERIC_CR_1 :
7837 MISC_REG_GENERIC_CR_0));
7838
5999 bp->link_params.shmem_base = bp->common.shmem_base; 7839 bp->link_params.shmem_base = bp->common.shmem_base;
7840 bp->link_params.shmem2_base = bp->common.shmem2_base;
6000 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 7841 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
6001 bp->common.shmem_base, bp->common.shmem2_base); 7842 bp->common.shmem_base, bp->common.shmem2_base);
6002 7843
6003 if (!bp->common.shmem_base || 7844 if (!bp->common.shmem_base) {
6004 (bp->common.shmem_base < 0xA0000) ||
6005 (bp->common.shmem_base >= 0xC0000)) {
6006 BNX2X_DEV_INFO("MCP not active\n"); 7845 BNX2X_DEV_INFO("MCP not active\n");
6007 bp->flags |= NO_MCP_FLAG; 7846 bp->flags |= NO_MCP_FLAG;
6008 return; 7847 return;
6009 } 7848 }
6010 7849
6011 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
6012 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6013 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6014 BNX2X_ERROR("BAD MCP validity signature\n");
6015
6016 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 7850 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
6017 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 7851 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
6018 7852
@@ -6035,20 +7869,20 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6035 if (val < BNX2X_BC_VER) { 7869 if (val < BNX2X_BC_VER) {
6036 /* for now only warn 7870 /* for now only warn
6037 * later we might need to enforce this */ 7871 * later we might need to enforce this */
6038 BNX2X_ERROR("This driver needs bc_ver %X but found %X, " 7872 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
6039 "please upgrade BC\n", BNX2X_BC_VER, val); 7873 "please upgrade BC\n", BNX2X_BC_VER, val);
6040 } 7874 }
6041 bp->link_params.feature_config_flags |= 7875 bp->link_params.feature_config_flags |=
6042 (val >= REQ_BC_VER_4_VRFY_OPT_MDL) ? 7876 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
6043 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 7877 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7878
7879 bp->link_params.feature_config_flags |=
7880 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7881 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
7882
7883 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7884 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
6044 7885
6045 if (BP_E1HVN(bp) == 0) {
6046 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
6047 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
6048 } else {
6049 /* no WOL capability for E1HVN != 0 */
6050 bp->flags |= NO_WOL_FLAG;
6051 }
6052 BNX2X_DEV_INFO("%sWoL capable\n", 7886 BNX2X_DEV_INFO("%sWoL capable\n",
6053 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 7887 (bp->flags & NO_WOL_FLAG) ? "not " : "");
6054 7888
@@ -6061,404 +7895,349 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6061 val, val2, val3, val4); 7895 val, val2, val3, val4);
6062} 7896}
6063 7897
7898#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7899#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7900
7901static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7902{
7903 int pfid = BP_FUNC(bp);
7904 int vn = BP_E1HVN(bp);
7905 int igu_sb_id;
7906 u32 val;
7907 u8 fid;
7908
7909 bp->igu_base_sb = 0xff;
7910 bp->igu_sb_cnt = 0;
7911 if (CHIP_INT_MODE_IS_BC(bp)) {
7912 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
7913 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7914
7915 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7916 FP_SB_MAX_E1x;
7917
7918 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7919 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7920
7921 return;
7922 }
7923
7924 /* IGU in normal mode - read CAM */
7925 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7926 igu_sb_id++) {
7927 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7928 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7929 continue;
7930 fid = IGU_FID(val);
7931 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7932 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7933 continue;
7934 if (IGU_VEC(val) == 0)
7935 /* default status block */
7936 bp->igu_dsb_id = igu_sb_id;
7937 else {
7938 if (bp->igu_base_sb == 0xff)
7939 bp->igu_base_sb = igu_sb_id;
7940 bp->igu_sb_cnt++;
7941 }
7942 }
7943 }
7944 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
7945 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7946 if (bp->igu_sb_cnt == 0)
7947 BNX2X_ERR("CAM configuration error\n");
7948}
7949
6064static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp, 7950static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
6065 u32 switch_cfg) 7951 u32 switch_cfg)
6066{ 7952{
6067 int port = BP_PORT(bp); 7953 int cfg_size = 0, idx, port = BP_PORT(bp);
6068 u32 ext_phy_type;
6069
6070 switch (switch_cfg) {
6071 case SWITCH_CFG_1G:
6072 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
6073
6074 ext_phy_type =
6075 SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6076 switch (ext_phy_type) {
6077 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
6078 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6079 ext_phy_type);
6080
6081 bp->port.supported |= (SUPPORTED_10baseT_Half |
6082 SUPPORTED_10baseT_Full |
6083 SUPPORTED_100baseT_Half |
6084 SUPPORTED_100baseT_Full |
6085 SUPPORTED_1000baseT_Full |
6086 SUPPORTED_2500baseX_Full |
6087 SUPPORTED_TP |
6088 SUPPORTED_FIBRE |
6089 SUPPORTED_Autoneg |
6090 SUPPORTED_Pause |
6091 SUPPORTED_Asym_Pause);
6092 break;
6093 7954
6094 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: 7955 /* Aggregation of supported attributes of all external phys */
6095 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n", 7956 bp->port.supported[0] = 0;
6096 ext_phy_type); 7957 bp->port.supported[1] = 0;
6097 7958 switch (bp->link_params.num_phys) {
6098 bp->port.supported |= (SUPPORTED_10baseT_Half | 7959 case 1:
6099 SUPPORTED_10baseT_Full | 7960 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
6100 SUPPORTED_100baseT_Half | 7961 cfg_size = 1;
6101 SUPPORTED_100baseT_Full | 7962 break;
6102 SUPPORTED_1000baseT_Full | 7963 case 2:
6103 SUPPORTED_TP | 7964 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
6104 SUPPORTED_FIBRE | 7965 cfg_size = 1;
6105 SUPPORTED_Autoneg | 7966 break;
6106 SUPPORTED_Pause | 7967 case 3:
6107 SUPPORTED_Asym_Pause); 7968 if (bp->link_params.multi_phy_config &
6108 break; 7969 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
7970 bp->port.supported[1] =
7971 bp->link_params.phy[EXT_PHY1].supported;
7972 bp->port.supported[0] =
7973 bp->link_params.phy[EXT_PHY2].supported;
7974 } else {
7975 bp->port.supported[0] =
7976 bp->link_params.phy[EXT_PHY1].supported;
7977 bp->port.supported[1] =
7978 bp->link_params.phy[EXT_PHY2].supported;
7979 }
7980 cfg_size = 2;
7981 break;
7982 }
6109 7983
6110 default: 7984 if (!(bp->port.supported[0] || bp->port.supported[1])) {
6111 BNX2X_ERR("NVRAM config error. " 7985 BNX2X_ERR("NVRAM config error. BAD phy config."
6112 "BAD SerDes ext_phy_config 0x%x\n", 7986 "PHY1 config 0x%x, PHY2 config 0x%x\n",
6113 bp->link_params.ext_phy_config); 7987 SHMEM_RD(bp,
7988 dev_info.port_hw_config[port].external_phy_config),
7989 SHMEM_RD(bp,
7990 dev_info.port_hw_config[port].external_phy_config2));
6114 return; 7991 return;
6115 } 7992 }
6116 7993
7994 switch (switch_cfg) {
7995 case SWITCH_CFG_1G:
6117 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + 7996 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
6118 port*0x10); 7997 port*0x10);
6119 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 7998 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
6120 break; 7999 break;
6121 8000
6122 case SWITCH_CFG_10G: 8001 case SWITCH_CFG_10G:
6123 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
6124
6125 ext_phy_type =
6126 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6127 switch (ext_phy_type) {
6128 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6129 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6130 ext_phy_type);
6131
6132 bp->port.supported |= (SUPPORTED_10baseT_Half |
6133 SUPPORTED_10baseT_Full |
6134 SUPPORTED_100baseT_Half |
6135 SUPPORTED_100baseT_Full |
6136 SUPPORTED_1000baseT_Full |
6137 SUPPORTED_2500baseX_Full |
6138 SUPPORTED_10000baseT_Full |
6139 SUPPORTED_TP |
6140 SUPPORTED_FIBRE |
6141 SUPPORTED_Autoneg |
6142 SUPPORTED_Pause |
6143 SUPPORTED_Asym_Pause);
6144 break;
6145
6146 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6147 BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
6148 ext_phy_type);
6149
6150 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6151 SUPPORTED_1000baseT_Full |
6152 SUPPORTED_FIBRE |
6153 SUPPORTED_Autoneg |
6154 SUPPORTED_Pause |
6155 SUPPORTED_Asym_Pause);
6156 break;
6157
6158 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6159 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
6160 ext_phy_type);
6161
6162 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6163 SUPPORTED_2500baseX_Full |
6164 SUPPORTED_1000baseT_Full |
6165 SUPPORTED_FIBRE |
6166 SUPPORTED_Autoneg |
6167 SUPPORTED_Pause |
6168 SUPPORTED_Asym_Pause);
6169 break;
6170
6171 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6172 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
6173 ext_phy_type);
6174
6175 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6176 SUPPORTED_FIBRE |
6177 SUPPORTED_Pause |
6178 SUPPORTED_Asym_Pause);
6179 break;
6180
6181 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6182 BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
6183 ext_phy_type);
6184
6185 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6186 SUPPORTED_1000baseT_Full |
6187 SUPPORTED_FIBRE |
6188 SUPPORTED_Pause |
6189 SUPPORTED_Asym_Pause);
6190 break;
6191
6192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6193 BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
6194 ext_phy_type);
6195
6196 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6197 SUPPORTED_1000baseT_Full |
6198 SUPPORTED_Autoneg |
6199 SUPPORTED_FIBRE |
6200 SUPPORTED_Pause |
6201 SUPPORTED_Asym_Pause);
6202 break;
6203
6204 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6205 BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n",
6206 ext_phy_type);
6207
6208 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6209 SUPPORTED_1000baseT_Full |
6210 SUPPORTED_Autoneg |
6211 SUPPORTED_FIBRE |
6212 SUPPORTED_Pause |
6213 SUPPORTED_Asym_Pause);
6214 break;
6215
6216 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6217 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
6218 ext_phy_type);
6219
6220 bp->port.supported |= (SUPPORTED_10000baseT_Full |
6221 SUPPORTED_TP |
6222 SUPPORTED_Autoneg |
6223 SUPPORTED_Pause |
6224 SUPPORTED_Asym_Pause);
6225 break;
6226
6227 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
6228 BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM8481)\n",
6229 ext_phy_type);
6230
6231 bp->port.supported |= (SUPPORTED_10baseT_Half |
6232 SUPPORTED_10baseT_Full |
6233 SUPPORTED_100baseT_Half |
6234 SUPPORTED_100baseT_Full |
6235 SUPPORTED_1000baseT_Full |
6236 SUPPORTED_10000baseT_Full |
6237 SUPPORTED_TP |
6238 SUPPORTED_Autoneg |
6239 SUPPORTED_Pause |
6240 SUPPORTED_Asym_Pause);
6241 break;
6242
6243 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6244 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
6245 bp->link_params.ext_phy_config);
6246 break;
6247
6248 default:
6249 BNX2X_ERR("NVRAM config error. "
6250 "BAD XGXS ext_phy_config 0x%x\n",
6251 bp->link_params.ext_phy_config);
6252 return;
6253 }
6254
6255 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + 8002 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
6256 port*0x18); 8003 port*0x18);
6257 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 8004 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
6258
6259 break; 8005 break;
6260 8006
6261 default: 8007 default:
6262 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 8008 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
6263 bp->port.link_config); 8009 bp->port.link_config[0]);
6264 return; 8010 return;
6265 } 8011 }
6266 bp->link_params.phy_addr = bp->port.phy_addr; 8012 /* mask what we support according to speed_cap_mask per configuration */
6267 8013 for (idx = 0; idx < cfg_size; idx++) {
6268 /* mask what we support according to speed_cap_mask */ 8014 if (!(bp->link_params.speed_cap_mask[idx] &
6269 if (!(bp->link_params.speed_cap_mask &
6270 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 8015 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
6271 bp->port.supported &= ~SUPPORTED_10baseT_Half; 8016 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
6272 8017
6273 if (!(bp->link_params.speed_cap_mask & 8018 if (!(bp->link_params.speed_cap_mask[idx] &
6274 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 8019 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
6275 bp->port.supported &= ~SUPPORTED_10baseT_Full; 8020 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
6276 8021
6277 if (!(bp->link_params.speed_cap_mask & 8022 if (!(bp->link_params.speed_cap_mask[idx] &
6278 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 8023 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
6279 bp->port.supported &= ~SUPPORTED_100baseT_Half; 8024 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
6280 8025
6281 if (!(bp->link_params.speed_cap_mask & 8026 if (!(bp->link_params.speed_cap_mask[idx] &
6282 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 8027 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
6283 bp->port.supported &= ~SUPPORTED_100baseT_Full; 8028 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
6284 8029
6285 if (!(bp->link_params.speed_cap_mask & 8030 if (!(bp->link_params.speed_cap_mask[idx] &
6286 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 8031 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
6287 bp->port.supported &= ~(SUPPORTED_1000baseT_Half | 8032 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
6288 SUPPORTED_1000baseT_Full); 8033 SUPPORTED_1000baseT_Full);
6289 8034
6290 if (!(bp->link_params.speed_cap_mask & 8035 if (!(bp->link_params.speed_cap_mask[idx] &
6291 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 8036 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6292 bp->port.supported &= ~SUPPORTED_2500baseX_Full; 8037 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
6293 8038
6294 if (!(bp->link_params.speed_cap_mask & 8039 if (!(bp->link_params.speed_cap_mask[idx] &
6295 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 8040 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
6296 bp->port.supported &= ~SUPPORTED_10000baseT_Full; 8041 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
6297 8042
6298 BNX2X_DEV_INFO("supported 0x%x\n", bp->port.supported); 8043 }
8044
8045 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8046 bp->port.supported[1]);
6299} 8047}
6300 8048
6301static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp) 8049static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
6302{ 8050{
6303 bp->link_params.req_duplex = DUPLEX_FULL; 8051 u32 link_config, idx, cfg_size = 0;
8052 bp->port.advertising[0] = 0;
8053 bp->port.advertising[1] = 0;
8054 switch (bp->link_params.num_phys) {
8055 case 1:
8056 case 2:
8057 cfg_size = 1;
8058 break;
8059 case 3:
8060 cfg_size = 2;
8061 break;
8062 }
8063 for (idx = 0; idx < cfg_size; idx++) {
8064 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8065 link_config = bp->port.link_config[idx];
8066 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8067 case PORT_FEATURE_LINK_SPEED_AUTO:
8068 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8069 bp->link_params.req_line_speed[idx] =
8070 SPEED_AUTO_NEG;
8071 bp->port.advertising[idx] |=
8072 bp->port.supported[idx];
8073 } else {
8074 /* force 10G, no AN */
8075 bp->link_params.req_line_speed[idx] =
8076 SPEED_10000;
8077 bp->port.advertising[idx] |=
8078 (ADVERTISED_10000baseT_Full |
8079 ADVERTISED_FIBRE);
8080 continue;
8081 }
8082 break;
6304 8083
6305 switch (bp->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) { 8084 case PORT_FEATURE_LINK_SPEED_10M_FULL:
6306 case PORT_FEATURE_LINK_SPEED_AUTO: 8085 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
6307 if (bp->port.supported & SUPPORTED_Autoneg) { 8086 bp->link_params.req_line_speed[idx] =
6308 bp->link_params.req_line_speed = SPEED_AUTO_NEG; 8087 SPEED_10;
6309 bp->port.advertising = bp->port.supported; 8088 bp->port.advertising[idx] |=
6310 } else { 8089 (ADVERTISED_10baseT_Full |
6311 u32 ext_phy_type = 8090 ADVERTISED_TP);
6312 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 8091 } else {
8092 BNX2X_ERROR("NVRAM config error. "
8093 "Invalid link_config 0x%x"
8094 " speed_cap_mask 0x%x\n",
8095 link_config,
8096 bp->link_params.speed_cap_mask[idx]);
8097 return;
8098 }
8099 break;
6313 8100
6314 if ((ext_phy_type == 8101 case PORT_FEATURE_LINK_SPEED_10M_HALF:
6315 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || 8102 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
6316 (ext_phy_type == 8103 bp->link_params.req_line_speed[idx] =
6317 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) { 8104 SPEED_10;
6318 /* force 10G, no AN */ 8105 bp->link_params.req_duplex[idx] =
6319 bp->link_params.req_line_speed = SPEED_10000; 8106 DUPLEX_HALF;
6320 bp->port.advertising = 8107 bp->port.advertising[idx] |=
6321 (ADVERTISED_10000baseT_Full | 8108 (ADVERTISED_10baseT_Half |
6322 ADVERTISED_FIBRE); 8109 ADVERTISED_TP);
6323 break; 8110 } else {
8111 BNX2X_ERROR("NVRAM config error. "
8112 "Invalid link_config 0x%x"
8113 " speed_cap_mask 0x%x\n",
8114 link_config,
8115 bp->link_params.speed_cap_mask[idx]);
8116 return;
6324 } 8117 }
6325 BNX2X_ERR("NVRAM config error. " 8118 break;
6326 "Invalid link_config 0x%x"
6327 " Autoneg not supported\n",
6328 bp->port.link_config);
6329 return;
6330 }
6331 break;
6332 8119
6333 case PORT_FEATURE_LINK_SPEED_10M_FULL: 8120 case PORT_FEATURE_LINK_SPEED_100M_FULL:
6334 if (bp->port.supported & SUPPORTED_10baseT_Full) { 8121 if (bp->port.supported[idx] &
6335 bp->link_params.req_line_speed = SPEED_10; 8122 SUPPORTED_100baseT_Full) {
6336 bp->port.advertising = (ADVERTISED_10baseT_Full | 8123 bp->link_params.req_line_speed[idx] =
6337 ADVERTISED_TP); 8124 SPEED_100;
6338 } else { 8125 bp->port.advertising[idx] |=
6339 BNX2X_ERROR("NVRAM config error. " 8126 (ADVERTISED_100baseT_Full |
6340 "Invalid link_config 0x%x" 8127 ADVERTISED_TP);
6341 " speed_cap_mask 0x%x\n", 8128 } else {
6342 bp->port.link_config, 8129 BNX2X_ERROR("NVRAM config error. "
6343 bp->link_params.speed_cap_mask); 8130 "Invalid link_config 0x%x"
6344 return; 8131 " speed_cap_mask 0x%x\n",
6345 } 8132 link_config,
6346 break; 8133 bp->link_params.speed_cap_mask[idx]);
8134 return;
8135 }
8136 break;
6347 8137
6348 case PORT_FEATURE_LINK_SPEED_10M_HALF: 8138 case PORT_FEATURE_LINK_SPEED_100M_HALF:
6349 if (bp->port.supported & SUPPORTED_10baseT_Half) { 8139 if (bp->port.supported[idx] &
6350 bp->link_params.req_line_speed = SPEED_10; 8140 SUPPORTED_100baseT_Half) {
6351 bp->link_params.req_duplex = DUPLEX_HALF; 8141 bp->link_params.req_line_speed[idx] =
6352 bp->port.advertising = (ADVERTISED_10baseT_Half | 8142 SPEED_100;
6353 ADVERTISED_TP); 8143 bp->link_params.req_duplex[idx] =
6354 } else { 8144 DUPLEX_HALF;
6355 BNX2X_ERROR("NVRAM config error. " 8145 bp->port.advertising[idx] |=
8146 (ADVERTISED_100baseT_Half |
8147 ADVERTISED_TP);
8148 } else {
8149 BNX2X_ERROR("NVRAM config error. "
6356 "Invalid link_config 0x%x" 8150 "Invalid link_config 0x%x"
6357 " speed_cap_mask 0x%x\n", 8151 " speed_cap_mask 0x%x\n",
6358 bp->port.link_config, 8152 link_config,
6359 bp->link_params.speed_cap_mask); 8153 bp->link_params.speed_cap_mask[idx]);
6360 return; 8154 return;
6361 } 8155 }
6362 break; 8156 break;
6363 8157
6364 case PORT_FEATURE_LINK_SPEED_100M_FULL: 8158 case PORT_FEATURE_LINK_SPEED_1G:
6365 if (bp->port.supported & SUPPORTED_100baseT_Full) { 8159 if (bp->port.supported[idx] &
6366 bp->link_params.req_line_speed = SPEED_100; 8160 SUPPORTED_1000baseT_Full) {
6367 bp->port.advertising = (ADVERTISED_100baseT_Full | 8161 bp->link_params.req_line_speed[idx] =
6368 ADVERTISED_TP); 8162 SPEED_1000;
6369 } else { 8163 bp->port.advertising[idx] |=
6370 BNX2X_ERROR("NVRAM config error. " 8164 (ADVERTISED_1000baseT_Full |
8165 ADVERTISED_TP);
8166 } else {
8167 BNX2X_ERROR("NVRAM config error. "
6371 "Invalid link_config 0x%x" 8168 "Invalid link_config 0x%x"
6372 " speed_cap_mask 0x%x\n", 8169 " speed_cap_mask 0x%x\n",
6373 bp->port.link_config, 8170 link_config,
6374 bp->link_params.speed_cap_mask); 8171 bp->link_params.speed_cap_mask[idx]);
6375 return; 8172 return;
6376 } 8173 }
6377 break; 8174 break;
6378 8175
6379 case PORT_FEATURE_LINK_SPEED_100M_HALF: 8176 case PORT_FEATURE_LINK_SPEED_2_5G:
6380 if (bp->port.supported & SUPPORTED_100baseT_Half) { 8177 if (bp->port.supported[idx] &
6381 bp->link_params.req_line_speed = SPEED_100; 8178 SUPPORTED_2500baseX_Full) {
6382 bp->link_params.req_duplex = DUPLEX_HALF; 8179 bp->link_params.req_line_speed[idx] =
6383 bp->port.advertising = (ADVERTISED_100baseT_Half | 8180 SPEED_2500;
8181 bp->port.advertising[idx] |=
8182 (ADVERTISED_2500baseX_Full |
6384 ADVERTISED_TP); 8183 ADVERTISED_TP);
6385 } else { 8184 } else {
6386 BNX2X_ERROR("NVRAM config error. " 8185 BNX2X_ERROR("NVRAM config error. "
6387 "Invalid link_config 0x%x" 8186 "Invalid link_config 0x%x"
6388 " speed_cap_mask 0x%x\n", 8187 " speed_cap_mask 0x%x\n",
6389 bp->port.link_config, 8188 link_config,
6390 bp->link_params.speed_cap_mask); 8189 bp->link_params.speed_cap_mask[idx]);
6391 return; 8190 return;
6392 } 8191 }
6393 break; 8192 break;
6394 8193
6395 case PORT_FEATURE_LINK_SPEED_1G: 8194 case PORT_FEATURE_LINK_SPEED_10G_CX4:
6396 if (bp->port.supported & SUPPORTED_1000baseT_Full) { 8195 case PORT_FEATURE_LINK_SPEED_10G_KX4:
6397 bp->link_params.req_line_speed = SPEED_1000; 8196 case PORT_FEATURE_LINK_SPEED_10G_KR:
6398 bp->port.advertising = (ADVERTISED_1000baseT_Full | 8197 if (bp->port.supported[idx] &
6399 ADVERTISED_TP); 8198 SUPPORTED_10000baseT_Full) {
6400 } else { 8199 bp->link_params.req_line_speed[idx] =
6401 BNX2X_ERROR("NVRAM config error. " 8200 SPEED_10000;
8201 bp->port.advertising[idx] |=
8202 (ADVERTISED_10000baseT_Full |
8203 ADVERTISED_FIBRE);
8204 } else {
8205 BNX2X_ERROR("NVRAM config error. "
6402 "Invalid link_config 0x%x" 8206 "Invalid link_config 0x%x"
6403 " speed_cap_mask 0x%x\n", 8207 " speed_cap_mask 0x%x\n",
6404 bp->port.link_config, 8208 link_config,
6405 bp->link_params.speed_cap_mask); 8209 bp->link_params.speed_cap_mask[idx]);
6406 return; 8210 return;
6407 } 8211 }
6408 break; 8212 break;
6409 8213
6410 case PORT_FEATURE_LINK_SPEED_2_5G: 8214 default:
6411 if (bp->port.supported & SUPPORTED_2500baseX_Full) {
6412 bp->link_params.req_line_speed = SPEED_2500;
6413 bp->port.advertising = (ADVERTISED_2500baseX_Full |
6414 ADVERTISED_TP);
6415 } else {
6416 BNX2X_ERROR("NVRAM config error. " 8215 BNX2X_ERROR("NVRAM config error. "
6417 "Invalid link_config 0x%x" 8216 "BAD link speed link_config 0x%x\n",
6418 " speed_cap_mask 0x%x\n", 8217 link_config);
6419 bp->port.link_config, 8218 bp->link_params.req_line_speed[idx] =
6420 bp->link_params.speed_cap_mask); 8219 SPEED_AUTO_NEG;
6421 return; 8220 bp->port.advertising[idx] =
8221 bp->port.supported[idx];
8222 break;
6422 } 8223 }
6423 break;
6424 8224
6425 case PORT_FEATURE_LINK_SPEED_10G_CX4: 8225 bp->link_params.req_flow_ctrl[idx] = (link_config &
6426 case PORT_FEATURE_LINK_SPEED_10G_KX4: 8226 PORT_FEATURE_FLOW_CONTROL_MASK);
6427 case PORT_FEATURE_LINK_SPEED_10G_KR: 8227 if ((bp->link_params.req_flow_ctrl[idx] ==
6428 if (bp->port.supported & SUPPORTED_10000baseT_Full) { 8228 BNX2X_FLOW_CTRL_AUTO) &&
6429 bp->link_params.req_line_speed = SPEED_10000; 8229 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
6430 bp->port.advertising = (ADVERTISED_10000baseT_Full | 8230 bp->link_params.req_flow_ctrl[idx] =
6431 ADVERTISED_FIBRE); 8231 BNX2X_FLOW_CTRL_NONE;
6432 } else {
6433 BNX2X_ERROR("NVRAM config error. "
6434 "Invalid link_config 0x%x"
6435 " speed_cap_mask 0x%x\n",
6436 bp->port.link_config,
6437 bp->link_params.speed_cap_mask);
6438 return;
6439 } 8232 }
6440 break;
6441 8233
6442 default: 8234 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
6443 BNX2X_ERROR("NVRAM config error. " 8235 " 0x%x advertising 0x%x\n",
6444 "BAD link speed link_config 0x%x\n", 8236 bp->link_params.req_line_speed[idx],
6445 bp->port.link_config); 8237 bp->link_params.req_duplex[idx],
6446 bp->link_params.req_line_speed = SPEED_AUTO_NEG; 8238 bp->link_params.req_flow_ctrl[idx],
6447 bp->port.advertising = bp->port.supported; 8239 bp->port.advertising[idx]);
6448 break;
6449 } 8240 }
6450
6451 bp->link_params.req_flow_ctrl = (bp->port.link_config &
6452 PORT_FEATURE_FLOW_CONTROL_MASK);
6453 if ((bp->link_params.req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
6454 !(bp->port.supported & SUPPORTED_Autoneg))
6455 bp->link_params.req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6456
6457 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x"
6458 " advertising 0x%x\n",
6459 bp->link_params.req_line_speed,
6460 bp->link_params.req_duplex,
6461 bp->link_params.req_flow_ctrl, bp->port.advertising);
6462} 8241}
6463 8242
6464static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 8243static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
@@ -6472,50 +8251,29 @@ static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
6472static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 8251static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
6473{ 8252{
6474 int port = BP_PORT(bp); 8253 int port = BP_PORT(bp);
6475 u32 val, val2;
6476 u32 config; 8254 u32 config;
6477 u16 i; 8255 u32 ext_phy_type, ext_phy_config;
6478 u32 ext_phy_type;
6479 8256
6480 bp->link_params.bp = bp; 8257 bp->link_params.bp = bp;
6481 bp->link_params.port = port; 8258 bp->link_params.port = port;
6482 8259
6483 bp->link_params.lane_config = 8260 bp->link_params.lane_config =
6484 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 8261 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
6485 bp->link_params.ext_phy_config =
6486 SHMEM_RD(bp,
6487 dev_info.port_hw_config[port].external_phy_config);
6488 /* BCM8727_NOC => BCM8727 no over current */
6489 if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
6490 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
6491 bp->link_params.ext_phy_config &=
6492 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
6493 bp->link_params.ext_phy_config |=
6494 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
6495 bp->link_params.feature_config_flags |=
6496 FEATURE_CONFIG_BCM8727_NOC;
6497 }
6498 8262
6499 bp->link_params.speed_cap_mask = 8263 bp->link_params.speed_cap_mask[0] =
6500 SHMEM_RD(bp, 8264 SHMEM_RD(bp,
6501 dev_info.port_hw_config[port].speed_capability_mask); 8265 dev_info.port_hw_config[port].speed_capability_mask);
6502 8266 bp->link_params.speed_cap_mask[1] =
6503 bp->port.link_config = 8267 SHMEM_RD(bp,
8268 dev_info.port_hw_config[port].speed_capability_mask2);
8269 bp->port.link_config[0] =
6504 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 8270 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
6505 8271
6506 /* Get the 4 lanes xgxs config rx and tx */ 8272 bp->port.link_config[1] =
6507 for (i = 0; i < 2; i++) { 8273 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
6508 val = SHMEM_RD(bp,
6509 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
6510 bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
6511 bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
6512
6513 val = SHMEM_RD(bp,
6514 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
6515 bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
6516 bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
6517 }
6518 8274
8275 bp->link_params.multi_phy_config =
8276 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
6519 /* If the device is capable of WoL, set the default state according 8277 /* If the device is capable of WoL, set the default state according
6520 * to the HW 8278 * to the HW
6521 */ 8279 */
@@ -6523,14 +8281,15 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
6523 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 8281 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
6524 (config & PORT_FEATURE_WOL_ENABLED)); 8282 (config & PORT_FEATURE_WOL_ENABLED));
6525 8283
6526 BNX2X_DEV_INFO("lane_config 0x%08x ext_phy_config 0x%08x" 8284 BNX2X_DEV_INFO("lane_config 0x%08x "
6527 " speed_cap_mask 0x%08x link_config 0x%08x\n", 8285 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
6528 bp->link_params.lane_config, 8286 bp->link_params.lane_config,
6529 bp->link_params.ext_phy_config, 8287 bp->link_params.speed_cap_mask[0],
6530 bp->link_params.speed_cap_mask, bp->port.link_config); 8288 bp->port.link_config[0]);
6531 8289
6532 bp->link_params.switch_cfg |= (bp->port.link_config & 8290 bp->link_params.switch_cfg = (bp->port.link_config[0] &
6533 PORT_FEATURE_CONNECTED_SWITCH_MASK); 8291 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8292 bnx2x_phy_probe(&bp->link_params);
6534 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 8293 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
6535 8294
6536 bnx2x_link_settings_requested(bp); 8295 bnx2x_link_settings_requested(bp);
@@ -6539,106 +8298,317 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
6539 * If connected directly, work with the internal PHY, otherwise, work 8298 * If connected directly, work with the internal PHY, otherwise, work
6540 * with the external PHY 8299 * with the external PHY
6541 */ 8300 */
6542 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 8301 ext_phy_config =
8302 SHMEM_RD(bp,
8303 dev_info.port_hw_config[port].external_phy_config);
8304 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6543 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8305 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6544 bp->mdio.prtad = bp->link_params.phy_addr; 8306 bp->mdio.prtad = bp->port.phy_addr;
6545 8307
6546 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 8308 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
6547 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 8309 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
6548 bp->mdio.prtad = 8310 bp->mdio.prtad =
6549 XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config); 8311 XGXS_EXT_PHY_ADDR(ext_phy_config);
8312
8313 /*
8314 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8315 * In MF mode, it is set to cover self test cases
8316 */
8317 if (IS_MF(bp))
8318 bp->port.need_hw_lock = 1;
8319 else
8320 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8321 bp->common.shmem_base,
8322 bp->common.shmem2_base);
8323}
8324
8325#ifdef BCM_CNIC
8326static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8327{
8328 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8329 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8330 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8331 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8332
8333 /* Get the number of maximum allowed iSCSI and FCoE connections */
8334 bp->cnic_eth_dev.max_iscsi_conn =
8335 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8336 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8337
8338 bp->cnic_eth_dev.max_fcoe_conn =
8339 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8340 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8341
8342 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8343 bp->cnic_eth_dev.max_iscsi_conn,
8344 bp->cnic_eth_dev.max_fcoe_conn);
8345
8346 /* If mamimum allowed number of connections is zero -
8347 * disable the feature.
8348 */
8349 if (!bp->cnic_eth_dev.max_iscsi_conn)
8350 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8351
8352 if (!bp->cnic_eth_dev.max_fcoe_conn)
8353 bp->flags |= NO_FCOE_FLAG;
8354}
8355#endif
8356
8357static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8358{
8359 u32 val, val2;
8360 int func = BP_ABS_FUNC(bp);
8361 int port = BP_PORT(bp);
8362#ifdef BCM_CNIC
8363 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8364 u8 *fip_mac = bp->fip_mac;
8365#endif
8366
8367 if (BP_NOMCP(bp)) {
8368 BNX2X_ERROR("warning: random MAC workaround active\n");
8369 random_ether_addr(bp->dev->dev_addr);
8370 } else if (IS_MF(bp)) {
8371 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8372 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8373 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8374 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8375 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8376
8377#ifdef BCM_CNIC
8378 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8379 * FCoE MAC then the appropriate feature should be disabled.
8380 */
8381 if (IS_MF_SI(bp)) {
8382 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8383 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8384 val2 = MF_CFG_RD(bp, func_ext_config[func].
8385 iscsi_mac_addr_upper);
8386 val = MF_CFG_RD(bp, func_ext_config[func].
8387 iscsi_mac_addr_lower);
8388 BNX2X_DEV_INFO("Read iSCSI MAC: "
8389 "0x%x:0x%04x\n", val2, val);
8390 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8391 } else
8392 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8393
8394 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8395 val2 = MF_CFG_RD(bp, func_ext_config[func].
8396 fcoe_mac_addr_upper);
8397 val = MF_CFG_RD(bp, func_ext_config[func].
8398 fcoe_mac_addr_lower);
8399 BNX2X_DEV_INFO("Read FCoE MAC to "
8400 "0x%x:0x%04x\n", val2, val);
8401 bnx2x_set_mac_buf(fip_mac, val, val2);
8402
8403 } else
8404 bp->flags |= NO_FCOE_FLAG;
8405 }
8406#endif
8407 } else {
8408 /* in SF read MACs from port configuration */
8409 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8410 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8411 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8412
8413#ifdef BCM_CNIC
8414 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8415 iscsi_mac_upper);
8416 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8417 iscsi_mac_lower);
8418 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8419#endif
8420 }
6550 8421
6551 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
6552 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
6553 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
6554 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 8422 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
6555 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 8423 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
6556 8424
6557#ifdef BCM_CNIC 8425#ifdef BCM_CNIC
6558 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].iscsi_mac_upper); 8426 /* Set the FCoE MAC in modes other then MF_SI */
6559 val = SHMEM_RD(bp, dev_info.port_hw_config[port].iscsi_mac_lower); 8427 if (!CHIP_IS_E1x(bp)) {
6560 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2); 8428 if (IS_MF_SD(bp))
8429 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8430 else if (!IS_MF(bp))
8431 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
8432 }
8433
8434 /* Disable iSCSI if MAC configuration is
8435 * invalid.
8436 */
8437 if (!is_valid_ether_addr(iscsi_mac)) {
8438 bp->flags |= NO_ISCSI_FLAG;
8439 memset(iscsi_mac, 0, ETH_ALEN);
8440 }
8441
8442 /* Disable FCoE if MAC configuration is
8443 * invalid.
8444 */
8445 if (!is_valid_ether_addr(fip_mac)) {
8446 bp->flags |= NO_FCOE_FLAG;
8447 memset(bp->fip_mac, 0, ETH_ALEN);
8448 }
6561#endif 8449#endif
6562} 8450}
6563 8451
6564static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 8452static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
6565{ 8453{
6566 int func = BP_FUNC(bp); 8454 int /*abs*/func = BP_ABS_FUNC(bp);
6567 u32 val, val2; 8455 int vn;
8456 u32 val = 0;
6568 int rc = 0; 8457 int rc = 0;
6569 8458
6570 bnx2x_get_common_hwinfo(bp); 8459 bnx2x_get_common_hwinfo(bp);
6571 8460
6572 bp->e1hov = 0; 8461 if (CHIP_IS_E1x(bp)) {
6573 bp->e1hmf = 0; 8462 bp->common.int_block = INT_BLOCK_HC;
6574 if (CHIP_IS_E1H(bp) && !BP_NOMCP(bp)) { 8463
6575 bp->mf_config = 8464 bp->igu_dsb_id = DEF_SB_IGU_ID;
6576 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); 8465 bp->igu_base_sb = 0;
8466 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8467 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8468 } else {
8469 bp->common.int_block = INT_BLOCK_IGU;
8470 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8471 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8472 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8473 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8474 } else
8475 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
8476
8477 bnx2x_get_igu_cam_info(bp);
8478
8479 }
8480 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8481 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8482
8483 /*
8484 * Initialize MF configuration
8485 */
8486
8487 bp->mf_ov = 0;
8488 bp->mf_mode = 0;
8489 vn = BP_E1HVN(bp);
8490
8491 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8492 DP(NETIF_MSG_PROBE,
8493 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8494 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8495 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8496 if (SHMEM2_HAS(bp, mf_cfg_addr))
8497 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8498 else
8499 bp->common.mf_cfg_base = bp->common.shmem_base +
8500 offsetof(struct shmem_region, func_mb) +
8501 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8502 /*
8503 * get mf configuration:
8504 * 1. existence of MF configuration
8505 * 2. MAC address must be legal (check only upper bytes)
8506 * for Switch-Independent mode;
8507 * OVLAN must be legal for Switch-Dependent mode
8508 * 3. SF_MODE configures specific MF mode
8509 */
8510 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8511 /* get mf configuration */
8512 val = SHMEM_RD(bp,
8513 dev_info.shared_feature_config.config);
8514 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8515
8516 switch (val) {
8517 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8518 val = MF_CFG_RD(bp, func_mf_config[func].
8519 mac_upper);
8520 /* check for legal mac (upper bytes)*/
8521 if (val != 0xffff) {
8522 bp->mf_mode = MULTI_FUNCTION_SI;
8523 bp->mf_config[vn] = MF_CFG_RD(bp,
8524 func_mf_config[func].config);
8525 } else
8526 DP(NETIF_MSG_PROBE, "illegal MAC "
8527 "address for SI\n");
8528 break;
8529 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8530 /* get OV configuration */
8531 val = MF_CFG_RD(bp,
8532 func_mf_config[FUNC_0].e1hov_tag);
8533 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8534
8535 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8536 bp->mf_mode = MULTI_FUNCTION_SD;
8537 bp->mf_config[vn] = MF_CFG_RD(bp,
8538 func_mf_config[func].config);
8539 } else
8540 DP(NETIF_MSG_PROBE, "illegal OV for "
8541 "SD\n");
8542 break;
8543 default:
8544 /* Unknown configuration: reset mf_config */
8545 bp->mf_config[vn] = 0;
8546 DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
8547 val);
8548 }
8549 }
6577 8550
6578 val = (SHMEM_RD(bp, mf_cfg.func_mf_config[FUNC_0].e1hov_tag) &
6579 FUNC_MF_CFG_E1HOV_TAG_MASK);
6580 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
6581 bp->e1hmf = 1;
6582 BNX2X_DEV_INFO("%s function mode\n", 8551 BNX2X_DEV_INFO("%s function mode\n",
6583 IS_E1HMF(bp) ? "multi" : "single"); 8552 IS_MF(bp) ? "multi" : "single");
6584 8553
6585 if (IS_E1HMF(bp)) { 8554 switch (bp->mf_mode) {
6586 val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func]. 8555 case MULTI_FUNCTION_SD:
6587 e1hov_tag) & 8556 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
6588 FUNC_MF_CFG_E1HOV_TAG_MASK); 8557 FUNC_MF_CFG_E1HOV_TAG_MASK;
6589 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 8558 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
6590 bp->e1hov = val; 8559 bp->mf_ov = val;
6591 BNX2X_DEV_INFO("E1HOV for func %d is %d " 8560 BNX2X_DEV_INFO("MF OV for func %d is %d"
6592 "(0x%04x)\n", 8561 " (0x%04x)\n", func,
6593 func, bp->e1hov, bp->e1hov); 8562 bp->mf_ov, bp->mf_ov);
6594 } else { 8563 } else {
6595 BNX2X_ERROR("No valid E1HOV for func %d," 8564 BNX2X_ERR("No valid MF OV for func %d,"
6596 " aborting\n", func); 8565 " aborting\n", func);
6597 rc = -EPERM; 8566 rc = -EPERM;
6598 } 8567 }
6599 } else { 8568 break;
6600 if (BP_E1HVN(bp)) { 8569 case MULTI_FUNCTION_SI:
6601 BNX2X_ERROR("VN %d in single function mode," 8570 BNX2X_DEV_INFO("func %d is in MF "
6602 " aborting\n", BP_E1HVN(bp)); 8571 "switch-independent mode\n", func);
8572 break;
8573 default:
8574 if (vn) {
8575 BNX2X_ERR("VN %d in single function mode,"
8576 " aborting\n", vn);
6603 rc = -EPERM; 8577 rc = -EPERM;
6604 } 8578 }
8579 break;
6605 } 8580 }
8581
6606 } 8582 }
6607 8583
8584 /* adjust igu_sb_cnt to MF for E1x */
8585 if (CHIP_IS_E1x(bp) && IS_MF(bp))
8586 bp->igu_sb_cnt /= E1HVN_MAX;
8587
8588 /*
8589 * adjust E2 sb count: to be removed when FW will support
8590 * more then 16 L2 clients
8591 */
8592#define MAX_L2_CLIENTS 16
8593 if (CHIP_IS_E2(bp))
8594 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8595 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8596
6608 if (!BP_NOMCP(bp)) { 8597 if (!BP_NOMCP(bp)) {
6609 bnx2x_get_port_hwinfo(bp); 8598 bnx2x_get_port_hwinfo(bp);
6610 8599
6611 bp->fw_seq = (SHMEM_RD(bp, func_mb[func].drv_mb_header) & 8600 bp->fw_seq =
6612 DRV_MSG_SEQ_NUMBER_MASK); 8601 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8602 DRV_MSG_SEQ_NUMBER_MASK);
6613 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 8603 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
6614 } 8604 }
6615 8605
6616 if (IS_E1HMF(bp)) { 8606 /* Get MAC addresses */
6617 val2 = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_upper); 8607 bnx2x_get_mac_hwinfo(bp);
6618 val = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_lower);
6619 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
6620 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
6621 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
6622 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
6623 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
6624 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
6625 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
6626 bp->dev->dev_addr[5] = (u8)(val & 0xff);
6627 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
6628 ETH_ALEN);
6629 memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
6630 ETH_ALEN);
6631 }
6632
6633 return rc;
6634 }
6635 8608
6636 if (BP_NOMCP(bp)) { 8609#ifdef BCM_CNIC
6637 /* only supposed to happen on emulation/FPGA */ 8610 bnx2x_get_cnic_info(bp);
6638 BNX2X_ERROR("warning: random MAC workaround active\n"); 8611#endif
6639 random_ether_addr(bp->dev->dev_addr);
6640 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
6641 }
6642 8612
6643 return rc; 8613 return rc;
6644} 8614}
@@ -6709,7 +8679,7 @@ out_not_found:
6709 8679
6710static int __devinit bnx2x_init_bp(struct bnx2x *bp) 8680static int __devinit bnx2x_init_bp(struct bnx2x *bp)
6711{ 8681{
6712 int func = BP_FUNC(bp); 8682 int func;
6713 int timer_interval; 8683 int timer_interval;
6714 int rc; 8684 int rc;
6715 8685
@@ -6729,7 +8699,13 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
6729 8699
6730 rc = bnx2x_get_hwinfo(bp); 8700 rc = bnx2x_get_hwinfo(bp);
6731 8701
8702 if (!rc)
8703 rc = bnx2x_alloc_mem_bp(bp);
8704
6732 bnx2x_read_fwinfo(bp); 8705 bnx2x_read_fwinfo(bp);
8706
8707 func = BP_FUNC(bp);
8708
6733 /* need to reset chip if undi was active */ 8709 /* need to reset chip if undi was active */
6734 if (!BP_NOMCP(bp)) 8710 if (!BP_NOMCP(bp))
6735 bnx2x_undi_unload(bp); 8711 bnx2x_undi_unload(bp);
@@ -6741,18 +8717,9 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
6741 dev_err(&bp->pdev->dev, "MCP disabled, " 8717 dev_err(&bp->pdev->dev, "MCP disabled, "
6742 "must load devices in order!\n"); 8718 "must load devices in order!\n");
6743 8719
6744 /* Set multi queue mode */
6745 if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
6746 ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
6747 dev_err(&bp->pdev->dev, "Multi disabled since int_mode "
6748 "requested is not MSI-X\n");
6749 multi_mode = ETH_RSS_MODE_DISABLED;
6750 }
6751 bp->multi_mode = multi_mode; 8720 bp->multi_mode = multi_mode;
6752 bp->int_mode = int_mode; 8721 bp->int_mode = int_mode;
6753 8722
6754 bp->dev->features |= NETIF_F_GRO;
6755
6756 /* Set TPA flags */ 8723 /* Set TPA flags */
6757 if (disable_tpa) { 8724 if (disable_tpa) {
6758 bp->flags &= ~TPA_ENABLE_FLAG; 8725 bp->flags &= ~TPA_ENABLE_FLAG;
@@ -6771,13 +8738,10 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
6771 bp->mrrs = mrrs; 8738 bp->mrrs = mrrs;
6772 8739
6773 bp->tx_ring_size = MAX_TX_AVAIL; 8740 bp->tx_ring_size = MAX_TX_AVAIL;
6774 bp->rx_ring_size = MAX_RX_AVAIL;
6775
6776 bp->rx_csum = 1;
6777 8741
6778 /* make sure that the numbers are in the right granularity */ 8742 /* make sure that the numbers are in the right granularity */
6779 bp->tx_ticks = (50 / (4 * BNX2X_BTR)) * (4 * BNX2X_BTR); 8743 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
6780 bp->rx_ticks = (25 / (4 * BNX2X_BTR)) * (4 * BNX2X_BTR); 8744 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
6781 8745
6782 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); 8746 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
6783 bp->current_interval = (poll ? poll : timer_interval); 8747 bp->current_interval = (poll ? poll : timer_interval);
@@ -6787,6 +8751,9 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
6787 bp->timer.data = (unsigned long) bp; 8751 bp->timer.data = (unsigned long) bp;
6788 bp->timer.function = bnx2x_timer; 8752 bp->timer.function = bnx2x_timer;
6789 8753
8754 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
8755 bnx2x_dcbx_init_params(bp);
8756
6790 return rc; 8757 return rc;
6791} 8758}
6792 8759
@@ -6853,12 +8820,197 @@ static int bnx2x_close(struct net_device *dev)
6853 return 0; 8820 return 0;
6854} 8821}
6855 8822
8823#define E1_MAX_UC_LIST 29
8824#define E1H_MAX_UC_LIST 30
8825#define E2_MAX_UC_LIST 14
8826static inline u8 bnx2x_max_uc_list(struct bnx2x *bp)
8827{
8828 if (CHIP_IS_E1(bp))
8829 return E1_MAX_UC_LIST;
8830 else if (CHIP_IS_E1H(bp))
8831 return E1H_MAX_UC_LIST;
8832 else
8833 return E2_MAX_UC_LIST;
8834}
8835
8836
8837static inline u8 bnx2x_uc_list_cam_offset(struct bnx2x *bp)
8838{
8839 if (CHIP_IS_E1(bp))
8840 /* CAM Entries for Port0:
8841 * 0 - prim ETH MAC
8842 * 1 - BCAST MAC
8843 * 2 - iSCSI L2 ring ETH MAC
8844 * 3-31 - UC MACs
8845 *
8846 * Port1 entries are allocated the same way starting from
8847 * entry 32.
8848 */
8849 return 3 + 32 * BP_PORT(bp);
8850 else if (CHIP_IS_E1H(bp)) {
8851 /* CAM Entries:
8852 * 0-7 - prim ETH MAC for each function
8853 * 8-15 - iSCSI L2 ring ETH MAC for each function
8854 * 16 till 255 UC MAC lists for each function
8855 *
8856 * Remark: There is no FCoE support for E1H, thus FCoE related
8857 * MACs are not considered.
8858 */
8859 return E1H_FUNC_MAX * (CAM_ISCSI_ETH_LINE + 1) +
8860 bnx2x_max_uc_list(bp) * BP_FUNC(bp);
8861 } else {
8862 /* CAM Entries (there is a separate CAM per engine):
8863 * 0-4 - prim ETH MAC for each function
8864 * 4-7 - iSCSI L2 ring ETH MAC for each function
8865 * 8-11 - FIP ucast L2 MAC for each function
8866 * 12-15 - ALL_ENODE_MACS mcast MAC for each function
8867 * 16 till 71 UC MAC lists for each function
8868 */
8869 u8 func_idx =
8870 (CHIP_MODE_IS_4_PORT(bp) ? BP_FUNC(bp) : BP_VN(bp));
8871
8872 return E2_FUNC_MAX * (CAM_MAX_PF_LINE + 1) +
8873 bnx2x_max_uc_list(bp) * func_idx;
8874 }
8875}
8876
8877/* set uc list, do not wait as wait implies sleep and
8878 * set_rx_mode can be invoked from non-sleepable context.
8879 *
8880 * Instead we use the same ramrod data buffer each time we need
8881 * to configure a list of addresses, and use the fact that the
8882 * list of MACs is changed in an incremental way and that the
8883 * function is called under the netif_addr_lock. A temporary
8884 * inconsistent CAM configuration (possible in case of very fast
8885 * sequence of add/del/add on the host side) will shortly be
8886 * restored by the handler of the last ramrod.
8887 */
8888static int bnx2x_set_uc_list(struct bnx2x *bp)
8889{
8890 int i = 0, old;
8891 struct net_device *dev = bp->dev;
8892 u8 offset = bnx2x_uc_list_cam_offset(bp);
8893 struct netdev_hw_addr *ha;
8894 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8895 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8896
8897 if (netdev_uc_count(dev) > bnx2x_max_uc_list(bp))
8898 return -EINVAL;
8899
8900 netdev_for_each_uc_addr(ha, dev) {
8901 /* copy mac */
8902 config_cmd->config_table[i].msb_mac_addr =
8903 swab16(*(u16 *)&bnx2x_uc_addr(ha)[0]);
8904 config_cmd->config_table[i].middle_mac_addr =
8905 swab16(*(u16 *)&bnx2x_uc_addr(ha)[2]);
8906 config_cmd->config_table[i].lsb_mac_addr =
8907 swab16(*(u16 *)&bnx2x_uc_addr(ha)[4]);
8908
8909 config_cmd->config_table[i].vlan_id = 0;
8910 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
8911 config_cmd->config_table[i].clients_bit_vector =
8912 cpu_to_le32(1 << BP_L_ID(bp));
8913
8914 SET_FLAG(config_cmd->config_table[i].flags,
8915 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8916 T_ETH_MAC_COMMAND_SET);
8917
8918 DP(NETIF_MSG_IFUP,
8919 "setting UCAST[%d] (%04x:%04x:%04x)\n", i,
8920 config_cmd->config_table[i].msb_mac_addr,
8921 config_cmd->config_table[i].middle_mac_addr,
8922 config_cmd->config_table[i].lsb_mac_addr);
8923
8924 i++;
8925
8926 /* Set uc MAC in NIG */
8927 bnx2x_set_mac_in_nig(bp, 1, bnx2x_uc_addr(ha),
8928 LLH_CAM_ETH_LINE + i);
8929 }
8930 old = config_cmd->hdr.length;
8931 if (old > i) {
8932 for (; i < old; i++) {
8933 if (CAM_IS_INVALID(config_cmd->
8934 config_table[i])) {
8935 /* already invalidated */
8936 break;
8937 }
8938 /* invalidate */
8939 SET_FLAG(config_cmd->config_table[i].flags,
8940 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8941 T_ETH_MAC_COMMAND_INVALIDATE);
8942 }
8943 }
8944
8945 wmb();
8946
8947 config_cmd->hdr.length = i;
8948 config_cmd->hdr.offset = offset;
8949 config_cmd->hdr.client_id = 0xff;
8950 /* Mark that this ramrod doesn't use bp->set_mac_pending for
8951 * synchronization.
8952 */
8953 config_cmd->hdr.echo = 0;
8954
8955 mb();
8956
8957 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8958 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8959
8960}
8961
8962void bnx2x_invalidate_uc_list(struct bnx2x *bp)
8963{
8964 int i;
8965 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8966 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8967 int ramrod_flags = WAIT_RAMROD_COMMON;
8968 u8 offset = bnx2x_uc_list_cam_offset(bp);
8969 u8 max_list_size = bnx2x_max_uc_list(bp);
8970
8971 for (i = 0; i < max_list_size; i++) {
8972 SET_FLAG(config_cmd->config_table[i].flags,
8973 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8974 T_ETH_MAC_COMMAND_INVALIDATE);
8975 bnx2x_set_mac_in_nig(bp, 0, NULL, LLH_CAM_ETH_LINE + 1 + i);
8976 }
8977
8978 wmb();
8979
8980 config_cmd->hdr.length = max_list_size;
8981 config_cmd->hdr.offset = offset;
8982 config_cmd->hdr.client_id = 0xff;
8983 /* We'll wait for a completion this time... */
8984 config_cmd->hdr.echo = 1;
8985
8986 bp->set_mac_pending = 1;
8987
8988 mb();
8989
8990 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8991 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8992
8993 /* Wait for a completion */
8994 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
8995 ramrod_flags);
8996
8997}
8998
8999static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9000{
9001 /* some multicasts */
9002 if (CHIP_IS_E1(bp)) {
9003 return bnx2x_set_e1_mc_list(bp);
9004 } else { /* E1H and newer */
9005 return bnx2x_set_e1h_mc_list(bp);
9006 }
9007}
9008
6856/* called with netif_tx_lock from dev_mcast.c */ 9009/* called with netif_tx_lock from dev_mcast.c */
6857void bnx2x_set_rx_mode(struct net_device *dev) 9010void bnx2x_set_rx_mode(struct net_device *dev)
6858{ 9011{
6859 struct bnx2x *bp = netdev_priv(dev); 9012 struct bnx2x *bp = netdev_priv(dev);
6860 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 9013 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
6861 int port = BP_PORT(bp);
6862 9014
6863 if (bp->state != BNX2X_STATE_OPEN) { 9015 if (bp->state != BNX2X_STATE_OPEN) {
6864 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 9016 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
@@ -6869,112 +9021,22 @@ void bnx2x_set_rx_mode(struct net_device *dev)
6869 9021
6870 if (dev->flags & IFF_PROMISC) 9022 if (dev->flags & IFF_PROMISC)
6871 rx_mode = BNX2X_RX_MODE_PROMISC; 9023 rx_mode = BNX2X_RX_MODE_PROMISC;
6872 9024 else if (dev->flags & IFF_ALLMULTI)
6873 else if ((dev->flags & IFF_ALLMULTI) ||
6874 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
6875 CHIP_IS_E1(bp)))
6876 rx_mode = BNX2X_RX_MODE_ALLMULTI; 9025 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9026 else {
9027 /* some multicasts */
9028 if (bnx2x_set_mc_list(bp))
9029 rx_mode = BNX2X_RX_MODE_ALLMULTI;
6877 9030
6878 else { /* some multicasts */ 9031 /* some unicasts */
6879 if (CHIP_IS_E1(bp)) { 9032 if (bnx2x_set_uc_list(bp))
6880 int i, old, offset; 9033 rx_mode = BNX2X_RX_MODE_PROMISC;
6881 struct netdev_hw_addr *ha;
6882 struct mac_configuration_cmd *config =
6883 bnx2x_sp(bp, mcast_config);
6884
6885 i = 0;
6886 netdev_for_each_mc_addr(ha, dev) {
6887 config->config_table[i].
6888 cam_entry.msb_mac_addr =
6889 swab16(*(u16 *)&ha->addr[0]);
6890 config->config_table[i].
6891 cam_entry.middle_mac_addr =
6892 swab16(*(u16 *)&ha->addr[2]);
6893 config->config_table[i].
6894 cam_entry.lsb_mac_addr =
6895 swab16(*(u16 *)&ha->addr[4]);
6896 config->config_table[i].cam_entry.flags =
6897 cpu_to_le16(port);
6898 config->config_table[i].
6899 target_table_entry.flags = 0;
6900 config->config_table[i].target_table_entry.
6901 clients_bit_vector =
6902 cpu_to_le32(1 << BP_L_ID(bp));
6903 config->config_table[i].
6904 target_table_entry.vlan_id = 0;
6905
6906 DP(NETIF_MSG_IFUP,
6907 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6908 config->config_table[i].
6909 cam_entry.msb_mac_addr,
6910 config->config_table[i].
6911 cam_entry.middle_mac_addr,
6912 config->config_table[i].
6913 cam_entry.lsb_mac_addr);
6914 i++;
6915 }
6916 old = config->hdr.length;
6917 if (old > i) {
6918 for (; i < old; i++) {
6919 if (CAM_IS_INVALID(config->
6920 config_table[i])) {
6921 /* already invalidated */
6922 break;
6923 }
6924 /* invalidate */
6925 CAM_INVALIDATE(config->
6926 config_table[i]);
6927 }
6928 }
6929
6930 if (CHIP_REV_IS_SLOW(bp))
6931 offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
6932 else
6933 offset = BNX2X_MAX_MULTICAST*(1 + port);
6934
6935 config->hdr.length = i;
6936 config->hdr.offset = offset;
6937 config->hdr.client_id = bp->fp->cl_id;
6938 config->hdr.reserved1 = 0;
6939
6940 bp->set_mac_pending++;
6941 smp_wmb();
6942
6943 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6944 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
6945 U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
6946 0);
6947 } else { /* E1H */
6948 /* Accept one or more multicasts */
6949 struct netdev_hw_addr *ha;
6950 u32 mc_filter[MC_HASH_SIZE];
6951 u32 crc, bit, regidx;
6952 int i;
6953
6954 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
6955
6956 netdev_for_each_mc_addr(ha, dev) {
6957 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
6958 ha->addr);
6959
6960 crc = crc32c_le(0, ha->addr, ETH_ALEN);
6961 bit = (crc >> 24) & 0xff;
6962 regidx = bit >> 5;
6963 bit &= 0x1f;
6964 mc_filter[regidx] |= (1 << bit);
6965 }
6966
6967 for (i = 0; i < MC_HASH_SIZE; i++)
6968 REG_WR(bp, MC_HASH_OFFSET(bp, i),
6969 mc_filter[i]);
6970 }
6971 } 9034 }
6972 9035
6973 bp->rx_mode = rx_mode; 9036 bp->rx_mode = rx_mode;
6974 bnx2x_set_storm_rx_mode(bp); 9037 bnx2x_set_storm_rx_mode(bp);
6975} 9038}
6976 9039
6977
6978/* called with rtnl_lock */ 9040/* called with rtnl_lock */
6979static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 9041static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
6980 int devad, u16 addr) 9042 int devad, u16 addr)
@@ -6982,23 +9044,15 @@ static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
6982 struct bnx2x *bp = netdev_priv(netdev); 9044 struct bnx2x *bp = netdev_priv(netdev);
6983 u16 value; 9045 u16 value;
6984 int rc; 9046 int rc;
6985 u32 phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6986 9047
6987 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 9048 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
6988 prtad, devad, addr); 9049 prtad, devad, addr);
6989 9050
6990 if (prtad != bp->mdio.prtad) {
6991 DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n",
6992 prtad, bp->mdio.prtad);
6993 return -EINVAL;
6994 }
6995
6996 /* The HW expects different devad if CL22 is used */ 9051 /* The HW expects different devad if CL22 is used */
6997 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 9052 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
6998 9053
6999 bnx2x_acquire_phy_lock(bp); 9054 bnx2x_acquire_phy_lock(bp);
7000 rc = bnx2x_cl45_read(bp, BP_PORT(bp), phy_type, prtad, 9055 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
7001 devad, addr, &value);
7002 bnx2x_release_phy_lock(bp); 9056 bnx2x_release_phy_lock(bp);
7003 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 9057 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
7004 9058
@@ -7012,24 +9066,16 @@ static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
7012 u16 addr, u16 value) 9066 u16 addr, u16 value)
7013{ 9067{
7014 struct bnx2x *bp = netdev_priv(netdev); 9068 struct bnx2x *bp = netdev_priv(netdev);
7015 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7016 int rc; 9069 int rc;
7017 9070
7018 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 9071 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
7019 " value 0x%x\n", prtad, devad, addr, value); 9072 " value 0x%x\n", prtad, devad, addr, value);
7020 9073
7021 if (prtad != bp->mdio.prtad) {
7022 DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n",
7023 prtad, bp->mdio.prtad);
7024 return -EINVAL;
7025 }
7026
7027 /* The HW expects different devad if CL22 is used */ 9074 /* The HW expects different devad if CL22 is used */
7028 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 9075 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
7029 9076
7030 bnx2x_acquire_phy_lock(bp); 9077 bnx2x_acquire_phy_lock(bp);
7031 rc = bnx2x_cl45_write(bp, BP_PORT(bp), ext_phy_type, prtad, 9078 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
7032 devad, addr, value);
7033 bnx2x_release_phy_lock(bp); 9079 bnx2x_release_phy_lock(bp);
7034 return rc; 9080 return rc;
7035} 9081}
@@ -7064,15 +9110,15 @@ static const struct net_device_ops bnx2x_netdev_ops = {
7064 .ndo_open = bnx2x_open, 9110 .ndo_open = bnx2x_open,
7065 .ndo_stop = bnx2x_close, 9111 .ndo_stop = bnx2x_close,
7066 .ndo_start_xmit = bnx2x_start_xmit, 9112 .ndo_start_xmit = bnx2x_start_xmit,
7067 .ndo_set_multicast_list = bnx2x_set_rx_mode, 9113 .ndo_select_queue = bnx2x_select_queue,
9114 .ndo_set_rx_mode = bnx2x_set_rx_mode,
7068 .ndo_set_mac_address = bnx2x_change_mac_addr, 9115 .ndo_set_mac_address = bnx2x_change_mac_addr,
7069 .ndo_validate_addr = eth_validate_addr, 9116 .ndo_validate_addr = eth_validate_addr,
7070 .ndo_do_ioctl = bnx2x_ioctl, 9117 .ndo_do_ioctl = bnx2x_ioctl,
7071 .ndo_change_mtu = bnx2x_change_mtu, 9118 .ndo_change_mtu = bnx2x_change_mtu,
9119 .ndo_fix_features = bnx2x_fix_features,
9120 .ndo_set_features = bnx2x_set_features,
7072 .ndo_tx_timeout = bnx2x_tx_timeout, 9121 .ndo_tx_timeout = bnx2x_tx_timeout,
7073#ifdef BCM_VLAN
7074 .ndo_vlan_rx_register = bnx2x_vlan_rx_register,
7075#endif
7076#ifdef CONFIG_NET_POLL_CONTROLLER 9122#ifdef CONFIG_NET_POLL_CONTROLLER
7077 .ndo_poll_controller = poll_bnx2x, 9123 .ndo_poll_controller = poll_bnx2x,
7078#endif 9124#endif
@@ -7090,7 +9136,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
7090 bp->dev = dev; 9136 bp->dev = dev;
7091 bp->pdev = pdev; 9137 bp->pdev = pdev;
7092 bp->flags = 0; 9138 bp->flags = 0;
7093 bp->func = PCI_FUNC(pdev->devfn); 9139 bp->pf_num = PCI_FUNC(pdev->devfn);
7094 9140
7095 rc = pci_enable_device(pdev); 9141 rc = pci_enable_device(pdev);
7096 if (rc) { 9142 if (rc) {
@@ -7172,7 +9218,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
7172 } 9218 }
7173 9219
7174 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), 9220 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
7175 min_t(u64, BNX2X_DB_SIZE, 9221 min_t(u64, BNX2X_DB_SIZE(bp),
7176 pci_resource_len(pdev, 2))); 9222 pci_resource_len(pdev, 2)));
7177 if (!bp->doorbells) { 9223 if (!bp->doorbells) {
7178 dev_err(&bp->pdev->dev, 9224 dev_err(&bp->pdev->dev,
@@ -7198,22 +9244,23 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
7198 9244
7199 dev->netdev_ops = &bnx2x_netdev_ops; 9245 dev->netdev_ops = &bnx2x_netdev_ops;
7200 bnx2x_set_ethtool_ops(dev); 9246 bnx2x_set_ethtool_ops(dev);
7201 dev->features |= NETIF_F_SG; 9247
7202 dev->features |= NETIF_F_HW_CSUM; 9248 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9249 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9250 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9251
9252 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9253 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9254
9255 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
7203 if (bp->flags & USING_DAC_FLAG) 9256 if (bp->flags & USING_DAC_FLAG)
7204 dev->features |= NETIF_F_HIGHDMA; 9257 dev->features |= NETIF_F_HIGHDMA;
7205 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN); 9258
7206 dev->features |= NETIF_F_TSO6; 9259 /* Add Loopback capability to the device */
7207#ifdef BCM_VLAN 9260 dev->hw_features |= NETIF_F_LOOPBACK;
7208 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); 9261
7209 bp->flags |= (HW_VLAN_RX_FLAG | HW_VLAN_TX_FLAG); 9262#ifdef BCM_DCBNL
7210 9263 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
7211 dev->vlan_features |= NETIF_F_SG;
7212 dev->vlan_features |= NETIF_F_HW_CSUM;
7213 if (bp->flags & USING_DAC_FLAG)
7214 dev->vlan_features |= NETIF_F_HIGHDMA;
7215 dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
7216 dev->vlan_features |= NETIF_F_TSO6;
7217#endif 9264#endif
7218 9265
7219 /* get_port_hwinfo() will set prtad and mmds properly */ 9266 /* get_port_hwinfo() will set prtad and mmds properly */
@@ -7259,7 +9306,7 @@ static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
7259 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; 9306 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
7260} 9307}
7261 9308
7262static int __devinit bnx2x_check_firmware(struct bnx2x *bp) 9309static int bnx2x_check_firmware(struct bnx2x *bp)
7263{ 9310{
7264 const struct firmware *firmware = bp->firmware; 9311 const struct firmware *firmware = bp->firmware;
7265 struct bnx2x_fw_file_hdr *fw_hdr; 9312 struct bnx2x_fw_file_hdr *fw_hdr;
@@ -7348,6 +9395,30 @@ static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
7348 } 9395 }
7349} 9396}
7350 9397
9398/**
9399 * IRO array is stored in the following format:
9400 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9401 */
9402static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9403{
9404 const __be32 *source = (const __be32 *)_source;
9405 struct iro *target = (struct iro *)_target;
9406 u32 i, j, tmp;
9407
9408 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9409 target[i].base = be32_to_cpu(source[j]);
9410 j++;
9411 tmp = be32_to_cpu(source[j]);
9412 target[i].m1 = (tmp >> 16) & 0xffff;
9413 target[i].m2 = tmp & 0xffff;
9414 j++;
9415 tmp = be32_to_cpu(source[j]);
9416 target[i].m3 = (tmp >> 16) & 0xffff;
9417 target[i].size = tmp & 0xffff;
9418 j++;
9419 }
9420}
9421
7351static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 9422static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
7352{ 9423{
7353 const __be16 *source = (const __be16 *)_source; 9424 const __be16 *source = (const __be16 *)_source;
@@ -7370,7 +9441,7 @@ do { \
7370 (u8 *)bp->arr, len); \ 9441 (u8 *)bp->arr, len); \
7371} while (0) 9442} while (0)
7372 9443
7373static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev) 9444int bnx2x_init_firmware(struct bnx2x *bp)
7374{ 9445{
7375 const char *fw_file_name; 9446 const char *fw_file_name;
7376 struct bnx2x_fw_file_hdr *fw_hdr; 9447 struct bnx2x_fw_file_hdr *fw_hdr;
@@ -7380,22 +9451,24 @@ static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
7380 fw_file_name = FW_FILE_NAME_E1; 9451 fw_file_name = FW_FILE_NAME_E1;
7381 else if (CHIP_IS_E1H(bp)) 9452 else if (CHIP_IS_E1H(bp))
7382 fw_file_name = FW_FILE_NAME_E1H; 9453 fw_file_name = FW_FILE_NAME_E1H;
9454 else if (CHIP_IS_E2(bp))
9455 fw_file_name = FW_FILE_NAME_E2;
7383 else { 9456 else {
7384 dev_err(dev, "Unsupported chip revision\n"); 9457 BNX2X_ERR("Unsupported chip revision\n");
7385 return -EINVAL; 9458 return -EINVAL;
7386 } 9459 }
7387 9460
7388 dev_info(dev, "Loading %s\n", fw_file_name); 9461 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
7389 9462
7390 rc = request_firmware(&bp->firmware, fw_file_name, dev); 9463 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
7391 if (rc) { 9464 if (rc) {
7392 dev_err(dev, "Can't load firmware file %s\n", fw_file_name); 9465 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
7393 goto request_firmware_exit; 9466 goto request_firmware_exit;
7394 } 9467 }
7395 9468
7396 rc = bnx2x_check_firmware(bp); 9469 rc = bnx2x_check_firmware(bp);
7397 if (rc) { 9470 if (rc) {
7398 dev_err(dev, "Corrupt firmware file %s\n", fw_file_name); 9471 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
7399 goto request_firmware_exit; 9472 goto request_firmware_exit;
7400 } 9473 }
7401 9474
@@ -7429,9 +9502,13 @@ static int __devinit bnx2x_init_firmware(struct bnx2x *bp, struct device *dev)
7429 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 9502 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
7430 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 9503 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
7431 be32_to_cpu(fw_hdr->csem_pram_data.offset); 9504 be32_to_cpu(fw_hdr->csem_pram_data.offset);
9505 /* IRO */
9506 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
7432 9507
7433 return 0; 9508 return 0;
7434 9509
9510iro_alloc_err:
9511 kfree(bp->init_ops_offsets);
7435init_offsets_alloc_err: 9512init_offsets_alloc_err:
7436 kfree(bp->init_ops); 9513 kfree(bp->init_ops);
7437init_ops_alloc_err: 9514init_ops_alloc_err:
@@ -7442,6 +9519,15 @@ request_firmware_exit:
7442 return rc; 9519 return rc;
7443} 9520}
7444 9521
9522static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9523{
9524 int cid_count = L2_FP_COUNT(l2_cid_count);
9525
9526#ifdef BCM_CNIC
9527 cid_count += CNIC_CID_MAX;
9528#endif
9529 return roundup(cid_count, QM_CID_ROUND);
9530}
7445 9531
7446static int __devinit bnx2x_init_one(struct pci_dev *pdev, 9532static int __devinit bnx2x_init_one(struct pci_dev *pdev,
7447 const struct pci_device_id *ent) 9533 const struct pci_device_id *ent)
@@ -7449,10 +9535,30 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
7449 struct net_device *dev = NULL; 9535 struct net_device *dev = NULL;
7450 struct bnx2x *bp; 9536 struct bnx2x *bp;
7451 int pcie_width, pcie_speed; 9537 int pcie_width, pcie_speed;
7452 int rc; 9538 int rc, cid_count;
9539
9540 switch (ent->driver_data) {
9541 case BCM57710:
9542 case BCM57711:
9543 case BCM57711E:
9544 cid_count = FP_SB_MAX_E1x;
9545 break;
9546
9547 case BCM57712:
9548 case BCM57712E:
9549 cid_count = FP_SB_MAX_E2;
9550 break;
9551
9552 default:
9553 pr_err("Unknown board_type (%ld), aborting\n",
9554 ent->driver_data);
9555 return -ENODEV;
9556 }
9557
9558 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
7453 9559
7454 /* dev zeroed in init_etherdev */ 9560 /* dev zeroed in init_etherdev */
7455 dev = alloc_etherdev_mq(sizeof(*bp), MAX_CONTEXT); 9561 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
7456 if (!dev) { 9562 if (!dev) {
7457 dev_err(&pdev->dev, "Cannot allocate net device\n"); 9563 dev_err(&pdev->dev, "Cannot allocate net device\n");
7458 return -ENOMEM; 9564 return -ENOMEM;
@@ -7463,6 +9569,8 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
7463 9569
7464 pci_set_drvdata(pdev, dev); 9570 pci_set_drvdata(pdev, dev);
7465 9571
9572 bp->l2_cid_count = cid_count;
9573
7466 rc = bnx2x_init_dev(pdev, dev); 9574 rc = bnx2x_init_dev(pdev, dev);
7467 if (rc < 0) { 9575 if (rc < 0) {
7468 free_netdev(dev); 9576 free_netdev(dev);
@@ -7473,12 +9581,23 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
7473 if (rc) 9581 if (rc)
7474 goto init_one_exit; 9582 goto init_one_exit;
7475 9583
7476 /* Set init arrays */ 9584 /* calc qm_cid_count */
7477 rc = bnx2x_init_firmware(bp, &pdev->dev); 9585 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
7478 if (rc) { 9586
7479 dev_err(&pdev->dev, "Error loading firmware\n"); 9587#ifdef BCM_CNIC
7480 goto init_one_exit; 9588 /* disable FCOE L2 queue for E1x*/
7481 } 9589 if (CHIP_IS_E1x(bp))
9590 bp->flags |= NO_FCOE_FLAG;
9591
9592#endif
9593
9594 /* Configure interrupt mode: try to enable MSI-X/MSI if
9595 * needed, set bp->num_queues appropriately.
9596 */
9597 bnx2x_set_int_mode(bp);
9598
9599 /* Add all NAPI objects */
9600 bnx2x_add_all_napi(bp);
7482 9601
7483 rc = register_netdev(dev); 9602 rc = register_netdev(dev);
7484 if (rc) { 9603 if (rc) {
@@ -7486,11 +9605,24 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
7486 goto init_one_exit; 9605 goto init_one_exit;
7487 } 9606 }
7488 9607
9608#ifdef BCM_CNIC
9609 if (!NO_FCOE(bp)) {
9610 /* Add storage MAC address */
9611 rtnl_lock();
9612 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9613 rtnl_unlock();
9614 }
9615#endif
9616
7489 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 9617 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
9618
7490 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx," 9619 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
7491 " IRQ %d, ", board_info[ent->driver_data].name, 9620 " IRQ %d, ", board_info[ent->driver_data].name,
7492 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 9621 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
7493 pcie_width, (pcie_speed == 2) ? "5GHz (Gen2)" : "2.5GHz", 9622 pcie_width,
9623 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9624 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9625 "5GHz (Gen2)" : "2.5GHz",
7494 dev->base_addr, bp->pdev->irq); 9626 dev->base_addr, bp->pdev->irq);
7495 pr_cont("node addr %pM\n", dev->dev_addr); 9627 pr_cont("node addr %pM\n", dev->dev_addr);
7496 9628
@@ -7525,22 +9657,45 @@ static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
7525 } 9657 }
7526 bp = netdev_priv(dev); 9658 bp = netdev_priv(dev);
7527 9659
9660#ifdef BCM_CNIC
9661 /* Delete storage MAC address */
9662 if (!NO_FCOE(bp)) {
9663 rtnl_lock();
9664 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9665 rtnl_unlock();
9666 }
9667#endif
9668
9669#ifdef BCM_DCBNL
9670 /* Delete app tlvs from dcbnl */
9671 bnx2x_dcbnl_update_applist(bp, true);
9672#endif
9673
7528 unregister_netdev(dev); 9674 unregister_netdev(dev);
7529 9675
9676 /* Delete all NAPI objects */
9677 bnx2x_del_all_napi(bp);
9678
9679 /* Power on: we can't let PCI layer write to us while we are in D3 */
9680 bnx2x_set_power_state(bp, PCI_D0);
9681
9682 /* Disable MSI/MSI-X */
9683 bnx2x_disable_msi(bp);
9684
9685 /* Power off */
9686 bnx2x_set_power_state(bp, PCI_D3hot);
9687
7530 /* Make sure RESET task is not scheduled before continuing */ 9688 /* Make sure RESET task is not scheduled before continuing */
7531 cancel_delayed_work_sync(&bp->reset_task); 9689 cancel_delayed_work_sync(&bp->reset_task);
7532 9690
7533 kfree(bp->init_ops_offsets);
7534 kfree(bp->init_ops);
7535 kfree(bp->init_data);
7536 release_firmware(bp->firmware);
7537
7538 if (bp->regview) 9691 if (bp->regview)
7539 iounmap(bp->regview); 9692 iounmap(bp->regview);
7540 9693
7541 if (bp->doorbells) 9694 if (bp->doorbells)
7542 iounmap(bp->doorbells); 9695 iounmap(bp->doorbells);
7543 9696
9697 bnx2x_free_mem_bp(bp);
9698
7544 free_netdev(dev); 9699 free_netdev(dev);
7545 9700
7546 if (atomic_read(&pdev->enable_cnt) == 1) 9701 if (atomic_read(&pdev->enable_cnt) == 1)
@@ -7566,22 +9721,14 @@ static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
7566 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 9721 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
7567 9722
7568 /* Release IRQs */ 9723 /* Release IRQs */
7569 bnx2x_free_irq(bp, false); 9724 bnx2x_free_irq(bp);
7570
7571 if (CHIP_IS_E1(bp)) {
7572 struct mac_configuration_cmd *config =
7573 bnx2x_sp(bp, mcast_config);
7574
7575 for (i = 0; i < config->hdr.length; i++)
7576 CAM_INVALIDATE(config->config_table[i]);
7577 }
7578 9725
7579 /* Free SKBs, SGEs, TPA pool and driver internals */ 9726 /* Free SKBs, SGEs, TPA pool and driver internals */
7580 bnx2x_free_skbs(bp); 9727 bnx2x_free_skbs(bp);
7581 for_each_queue(bp, i) 9728
9729 for_each_rx_queue(bp, i)
7582 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 9730 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
7583 for_each_queue(bp, i) 9731
7584 netif_napi_del(&bnx2x_fp(bp, i, napi));
7585 bnx2x_free_mem(bp); 9732 bnx2x_free_mem(bp);
7586 9733
7587 bp->state = BNX2X_STATE_CLOSED; 9734 bp->state = BNX2X_STATE_CLOSED;
@@ -7613,8 +9760,9 @@ static void bnx2x_eeh_recover(struct bnx2x *bp)
7613 BNX2X_ERR("BAD MCP validity signature\n"); 9760 BNX2X_ERR("BAD MCP validity signature\n");
7614 9761
7615 if (!BP_NOMCP(bp)) { 9762 if (!BP_NOMCP(bp)) {
7616 bp->fw_seq = (SHMEM_RD(bp, func_mb[BP_FUNC(bp)].drv_mb_header) 9763 bp->fw_seq =
7617 & DRV_MSG_SEQ_NUMBER_MASK); 9764 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9765 DRV_MSG_SEQ_NUMBER_MASK);
7618 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 9766 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
7619 } 9767 }
7620} 9768}
@@ -7697,7 +9845,8 @@ static void bnx2x_io_resume(struct pci_dev *pdev)
7697 struct bnx2x *bp = netdev_priv(dev); 9845 struct bnx2x *bp = netdev_priv(dev);
7698 9846
7699 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 9847 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
7700 printk(KERN_ERR "Handling parity error recovery. Try again later\n"); 9848 printk(KERN_ERR "Handling parity error recovery. "
9849 "Try again later\n");
7701 return; 9850 return;
7702 } 9851 }
7703 9852
@@ -7772,19 +9921,60 @@ static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
7772#endif 9921#endif
7773 9922
7774 spin_lock_bh(&bp->spq_lock); 9923 spin_lock_bh(&bp->spq_lock);
9924 BUG_ON(bp->cnic_spq_pending < count);
7775 bp->cnic_spq_pending -= count; 9925 bp->cnic_spq_pending -= count;
7776 9926
7777 for (; bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending;
7778 bp->cnic_spq_pending++) {
7779 9927
7780 if (!bp->cnic_kwq_pending) 9928 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9929 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9930 & SPE_HDR_CONN_TYPE) >>
9931 SPE_HDR_CONN_TYPE_SHIFT;
9932
9933 /* Set validation for iSCSI L2 client before sending SETUP
9934 * ramrod
9935 */
9936 if (type == ETH_CONNECTION_TYPE) {
9937 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9938 hdr.conn_and_cmd_data) >>
9939 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9940
9941 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9942 bnx2x_set_ctx_validation(&bp->context.
9943 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9944 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9945 }
9946
9947 /* There may be not more than 8 L2 and not more than 8 L5 SPEs
9948 * We also check that the number of outstanding
9949 * COMMON ramrods is not more than the EQ and SPQ can
9950 * accommodate.
9951 */
9952 if (type == ETH_CONNECTION_TYPE) {
9953 if (!atomic_read(&bp->cq_spq_left))
9954 break;
9955 else
9956 atomic_dec(&bp->cq_spq_left);
9957 } else if (type == NONE_CONNECTION_TYPE) {
9958 if (!atomic_read(&bp->eq_spq_left))
9959 break;
9960 else
9961 atomic_dec(&bp->eq_spq_left);
9962 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9963 (type == FCOE_CONNECTION_TYPE)) {
9964 if (bp->cnic_spq_pending >=
9965 bp->cnic_eth_dev.max_kwqe_pending)
9966 break;
9967 else
9968 bp->cnic_spq_pending++;
9969 } else {
9970 BNX2X_ERR("Unknown SPE type: %d\n", type);
9971 bnx2x_panic();
7781 break; 9972 break;
9973 }
7782 9974
7783 spe = bnx2x_sp_get_next(bp); 9975 spe = bnx2x_sp_get_next(bp);
7784 *spe = *bp->cnic_kwq_cons; 9976 *spe = *bp->cnic_kwq_cons;
7785 9977
7786 bp->cnic_kwq_pending--;
7787
7788 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 9978 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
7789 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 9979 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
7790 9980
@@ -7822,8 +10012,8 @@ static int bnx2x_cnic_sp_queue(struct net_device *dev,
7822 10012
7823 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 10013 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
7824 spe->hdr.conn_and_cmd_data, spe->hdr.type, 10014 spe->hdr.conn_and_cmd_data, spe->hdr.type,
7825 spe->data.mac_config_addr.hi, 10015 spe->data.update_data_addr.hi,
7826 spe->data.mac_config_addr.lo, 10016 spe->data.update_data_addr.lo,
7827 bp->cnic_kwq_pending); 10017 bp->cnic_kwq_pending);
7828 10018
7829 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 10019 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
@@ -7846,7 +10036,8 @@ static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
7846 int rc = 0; 10036 int rc = 0;
7847 10037
7848 mutex_lock(&bp->cnic_mutex); 10038 mutex_lock(&bp->cnic_mutex);
7849 c_ops = bp->cnic_ops; 10039 c_ops = rcu_dereference_protected(bp->cnic_ops,
10040 lockdep_is_held(&bp->cnic_mutex));
7850 if (c_ops) 10041 if (c_ops)
7851 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 10042 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
7852 mutex_unlock(&bp->cnic_mutex); 10043 mutex_unlock(&bp->cnic_mutex);
@@ -7889,7 +10080,7 @@ static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
7889 ctl.data.comp.cid = cid; 10080 ctl.data.comp.cid = cid;
7890 10081
7891 bnx2x_cnic_ctl_send_bh(bp, &ctl); 10082 bnx2x_cnic_ctl_send_bh(bp, &ctl);
7892 bnx2x_cnic_sp_post(bp, 1); 10083 bnx2x_cnic_sp_post(bp, 0);
7893} 10084}
7894 10085
7895static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 10086static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
@@ -7906,8 +10097,8 @@ static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
7906 break; 10097 break;
7907 } 10098 }
7908 10099
7909 case DRV_CTL_COMPLETION_CMD: { 10100 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
7910 int count = ctl->data.comp.comp_count; 10101 int count = ctl->data.credit.credit_count;
7911 10102
7912 bnx2x_cnic_sp_post(bp, count); 10103 bnx2x_cnic_sp_post(bp, count);
7913 break; 10104 break;
@@ -7917,8 +10108,27 @@ static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
7917 case DRV_CTL_START_L2_CMD: { 10108 case DRV_CTL_START_L2_CMD: {
7918 u32 cli = ctl->data.ring.client_id; 10109 u32 cli = ctl->data.ring.client_id;
7919 10110
7920 bp->rx_mode_cl_mask |= (1 << cli); 10111 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
7921 bnx2x_set_storm_rx_mode(bp); 10112 bnx2x_del_fcoe_eth_macs(bp);
10113
10114 /* Set iSCSI MAC address */
10115 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
10116
10117 mmiowb();
10118 barrier();
10119
10120 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10121 * because it's the only way for UIO Client to accept
10122 * multicasts (in non-promiscuous mode only one Client per
10123 * function will receive multicast packets (leading in our
10124 * case).
10125 */
10126 bnx2x_rxq_set_mac_filters(bp, cli,
10127 BNX2X_ACCEPT_UNICAST |
10128 BNX2X_ACCEPT_BROADCAST |
10129 BNX2X_ACCEPT_ALL_MULTICAST);
10130 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10131
7922 break; 10132 break;
7923 } 10133 }
7924 10134
@@ -7926,8 +10136,28 @@ static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
7926 case DRV_CTL_STOP_L2_CMD: { 10136 case DRV_CTL_STOP_L2_CMD: {
7927 u32 cli = ctl->data.ring.client_id; 10137 u32 cli = ctl->data.ring.client_id;
7928 10138
7929 bp->rx_mode_cl_mask &= ~(1 << cli); 10139 /* Stop accepting on iSCSI L2 ring */
7930 bnx2x_set_storm_rx_mode(bp); 10140 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10141 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10142
10143 mmiowb();
10144 barrier();
10145
10146 /* Unset iSCSI L2 MAC */
10147 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
10148 break;
10149 }
10150 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10151 int count = ctl->data.credit.credit_count;
10152
10153 smp_mb__before_atomic_inc();
10154 atomic_add(count, &bp->cq_spq_left);
10155 smp_mb__after_atomic_inc();
10156 break;
10157 }
10158
10159 case DRV_CTL_ISCSI_STOPPED_CMD: {
10160 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_ISCSI_STOPPED);
7931 break; 10161 break;
7932 } 10162 }
7933 10163
@@ -7951,10 +10181,16 @@ void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
7951 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 10181 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
7952 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 10182 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
7953 } 10183 }
7954 cp->irq_arr[0].status_blk = bp->cnic_sb; 10184 if (CHIP_IS_E2(bp))
10185 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10186 else
10187 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10188
7955 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp); 10189 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
10190 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
7956 cp->irq_arr[1].status_blk = bp->def_status_blk; 10191 cp->irq_arr[1].status_blk = bp->def_status_blk;
7957 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 10192 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10193 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
7958 10194
7959 cp->num_irq = 2; 10195 cp->num_irq = 2;
7960} 10196}
@@ -7986,12 +10222,10 @@ static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
7986 10222
7987 cp->num_irq = 0; 10223 cp->num_irq = 0;
7988 cp->drv_state = CNIC_DRV_STATE_REGD; 10224 cp->drv_state = CNIC_DRV_STATE_REGD;
7989 10225 cp->iro_arr = bp->iro_arr;
7990 bnx2x_init_sb(bp, bp->cnic_sb, bp->cnic_sb_mapping, CNIC_SB_ID(bp));
7991 10226
7992 bnx2x_setup_cnic_irq_info(bp); 10227 bnx2x_setup_cnic_irq_info(bp);
7993 bnx2x_set_iscsi_eth_mac_addr(bp, 1); 10228
7994 bp->cnic_flags |= BNX2X_CNIC_FLAG_MAC_SET;
7995 rcu_assign_pointer(bp->cnic_ops, ops); 10229 rcu_assign_pointer(bp->cnic_ops, ops);
7996 10230
7997 return 0; 10231 return 0;
@@ -8003,10 +10237,6 @@ static int bnx2x_unregister_cnic(struct net_device *dev)
8003 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 10237 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
8004 10238
8005 mutex_lock(&bp->cnic_mutex); 10239 mutex_lock(&bp->cnic_mutex);
8006 if (bp->cnic_flags & BNX2X_CNIC_FLAG_MAC_SET) {
8007 bp->cnic_flags &= ~BNX2X_CNIC_FLAG_MAC_SET;
8008 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
8009 }
8010 cp->drv_state = 0; 10240 cp->drv_state = 0;
8011 rcu_assign_pointer(bp->cnic_ops, NULL); 10241 rcu_assign_pointer(bp->cnic_ops, NULL);
8012 mutex_unlock(&bp->cnic_mutex); 10242 mutex_unlock(&bp->cnic_mutex);
@@ -8022,21 +10252,48 @@ struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
8022 struct bnx2x *bp = netdev_priv(dev); 10252 struct bnx2x *bp = netdev_priv(dev);
8023 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 10253 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
8024 10254
10255 /* If both iSCSI and FCoE are disabled - return NULL in
10256 * order to indicate CNIC that it should not try to work
10257 * with this device.
10258 */
10259 if (NO_ISCSI(bp) && NO_FCOE(bp))
10260 return NULL;
10261
8025 cp->drv_owner = THIS_MODULE; 10262 cp->drv_owner = THIS_MODULE;
8026 cp->chip_id = CHIP_ID(bp); 10263 cp->chip_id = CHIP_ID(bp);
8027 cp->pdev = bp->pdev; 10264 cp->pdev = bp->pdev;
8028 cp->io_base = bp->regview; 10265 cp->io_base = bp->regview;
8029 cp->io_base2 = bp->doorbells; 10266 cp->io_base2 = bp->doorbells;
8030 cp->max_kwqe_pending = 8; 10267 cp->max_kwqe_pending = 8;
8031 cp->ctx_blk_size = CNIC_CTX_PER_ILT * sizeof(union cdu_context); 10268 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
8032 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 1; 10269 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10270 bnx2x_cid_ilt_lines(bp);
8033 cp->ctx_tbl_len = CNIC_ILT_LINES; 10271 cp->ctx_tbl_len = CNIC_ILT_LINES;
8034 cp->starting_cid = BCM_CNIC_CID_START; 10272 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
8035 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 10273 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
8036 cp->drv_ctl = bnx2x_drv_ctl; 10274 cp->drv_ctl = bnx2x_drv_ctl;
8037 cp->drv_register_cnic = bnx2x_register_cnic; 10275 cp->drv_register_cnic = bnx2x_register_cnic;
8038 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 10276 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
8039 10277 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10278 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10279 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
10280 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10281
10282 if (NO_ISCSI_OOO(bp))
10283 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10284
10285 if (NO_ISCSI(bp))
10286 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10287
10288 if (NO_FCOE(bp))
10289 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10290
10291 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10292 "starting cid %d\n",
10293 cp->ctx_blk_size,
10294 cp->ctx_tbl_offset,
10295 cp->ctx_tbl_len,
10296 cp->starting_cid);
8040 return cp; 10297 return cp;
8041} 10298}
8042EXPORT_SYMBOL(bnx2x_cnic_probe); 10299EXPORT_SYMBOL(bnx2x_cnic_probe);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-07 05:34:54 -0400