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Diffstat (limited to 'drivers/net/bnx2x/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c981
1 files changed, 828 insertions, 153 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 347f3239ad1f..873463966a0e 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -105,12 +105,6 @@
105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
106#define GP_STATUS_10G_CX4 \ 106#define GP_STATUS_10G_CX4 \
107 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 107 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
108#define GP_STATUS_12G_HIG \
109 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
110#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
111#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
112#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
113#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
114#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 108#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
115#define GP_STATUS_10G_KX4 \ 109#define GP_STATUS_10G_KX4 \
116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
@@ -128,16 +122,6 @@
128#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 122#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
129#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 123#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
130#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 124#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
131#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
132#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
133#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
134#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
135#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
136#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
137#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
138#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
139#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
140#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
141 125
142#define PHY_XGXS_FLAG 0x1 126#define PHY_XGXS_FLAG 0x1
143#define PHY_SGMII_FLAG 0x2 127#define PHY_SGMII_FLAG 0x2
@@ -167,8 +151,103 @@
167#define EDC_MODE_PASSIVE_DAC 0x0055 151#define EDC_MODE_PASSIVE_DAC 0x0055
168 152
169 153
154/* BRB thresholds for E2*/
155#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
156#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
157
158#define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
159#define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
160
161#define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
162#define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
163
164#define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
165#define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
166
167/* BRB thresholds for E3A0 */
168#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
169#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
170
171#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
172#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
173
174#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
175#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
176
177#define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
178#define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
179
180
181/* BRB thresholds for E3B0 2 port mode*/
182#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
183#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
184
185#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
186#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
187
188#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
189#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
190
191#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
192#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
193
194/* only for E3B0*/
195#define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
196#define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
197
198/* Lossy +Lossless GUARANTIED == GUART */
199#define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
200/* Lossless +Lossless*/
201#define PFC_E3B0_2P_PAUSE_LB_GUART 236
202/* Lossy +Lossy*/
203#define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
204
205/* Lossy +Lossless*/
206#define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
207/* Lossless +Lossless*/
208#define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
209/* Lossy +Lossy*/
210#define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
211#define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
212
213#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
214#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
215
216/* BRB thresholds for E3B0 4 port mode */
217#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
218#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
219
220#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
221#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
222
223#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
224#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
225
226#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
227#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
228
229
230/* only for E3B0*/
231#define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
232#define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
233#define PFC_E3B0_4P_LB_GUART 120
234
235#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
236#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
237
238#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
239#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
240
241#define DCBX_INVALID_COS (0xFF)
242
170#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 243#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
171#define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 244#define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
245#define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
246#define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
247#define ETS_E3B0_PBF_MIN_W_VAL (10000)
248
249#define MAX_PACKET_SIZE (9700)
250
172/**********************************************************/ 251/**********************************************************/
173/* INTERFACE */ 252/* INTERFACE */
174/**********************************************************/ 253/**********************************************************/
@@ -390,6 +469,53 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
390/* PFC section */ 469/* PFC section */
391/******************************************************************/ 470/******************************************************************/
392 471
472static void bnx2x_update_pfc_xmac(struct link_params *params,
473 struct link_vars *vars,
474 u8 is_lb)
475{
476 struct bnx2x *bp = params->bp;
477 u32 xmac_base;
478 u32 pause_val, pfc0_val, pfc1_val;
479
480 /* XMAC base adrr */
481 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
482
483 /* Initialize pause and pfc registers */
484 pause_val = 0x18000;
485 pfc0_val = 0xFFFF8000;
486 pfc1_val = 0x2;
487
488 /* No PFC support */
489 if (!(params->feature_config_flags &
490 FEATURE_CONFIG_PFC_ENABLED)) {
491
492 /*
493 * RX flow control - Process pause frame in receive direction
494 */
495 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
496 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
497
498 /*
499 * TX flow control - Send pause packet when buffer is full
500 */
501 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
502 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
503 } else {/* PFC support */
504 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
505 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
506 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
507 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
508 }
509
510 /* Write pause and PFC registers */
511 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
512 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
513 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
514
515 udelay(30);
516}
517
518
393static void bnx2x_bmac2_get_pfc_stat(struct link_params *params, 519static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
394 u32 pfc_frames_sent[2], 520 u32 pfc_frames_sent[2],
395 u32 pfc_frames_received[2]) 521 u32 pfc_frames_received[2])
@@ -533,6 +659,233 @@ static void bnx2x_emac_init(struct link_params *params,
533 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); 659 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
534} 660}
535 661
662static void bnx2x_set_xumac_nig(struct link_params *params,
663 u16 tx_pause_en,
664 u8 enable)
665{
666 struct bnx2x *bp = params->bp;
667
668 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
669 enable);
670 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
671 enable);
672 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
673 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
674}
675
676static void bnx2x_umac_enable(struct link_params *params,
677 struct link_vars *vars, u8 lb)
678{
679 u32 val;
680 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
681 struct bnx2x *bp = params->bp;
682 /* Reset UMAC */
683 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
684 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
685 usleep_range(1000, 1000);
686
687 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
688 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
689
690 DP(NETIF_MSG_LINK, "enabling UMAC\n");
691
692 /**
693 * This register determines on which events the MAC will assert
694 * error on the i/f to the NIG along w/ EOP.
695 */
696
697 /**
698 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
699 * params->port*0x14, 0xfffff.
700 */
701 /* This register opens the gate for the UMAC despite its name */
702 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
703
704 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
705 UMAC_COMMAND_CONFIG_REG_PAD_EN |
706 UMAC_COMMAND_CONFIG_REG_SW_RESET |
707 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
708 switch (vars->line_speed) {
709 case SPEED_10:
710 val |= (0<<2);
711 break;
712 case SPEED_100:
713 val |= (1<<2);
714 break;
715 case SPEED_1000:
716 val |= (2<<2);
717 break;
718 case SPEED_2500:
719 val |= (3<<2);
720 break;
721 default:
722 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
723 vars->line_speed);
724 break;
725 }
726 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
727 udelay(50);
728
729 /* Enable RX and TX */
730 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
731 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
732 UMAC_COMMAND_CONFIG_REG_RX_ENA;
733 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
734 udelay(50);
735
736 /* Remove SW Reset */
737 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
738
739 /* Check loopback mode */
740 if (lb)
741 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
742 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
743
744 /*
745 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
746 * length used by the MAC receive logic to check frames.
747 */
748 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
749 bnx2x_set_xumac_nig(params,
750 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
751 vars->mac_type = MAC_TYPE_UMAC;
752
753}
754
755static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
756{
757 u32 port4mode_ovwr_val;
758 /* Check 4-port override enabled */
759 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
760 if (port4mode_ovwr_val & (1<<0)) {
761 /* Return 4-port mode override value */
762 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
763 }
764 /* Return 4-port mode from input pin */
765 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
766}
767
768/* Define the XMAC mode */
769static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
770{
771 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
772
773 /**
774 * In 4-port mode, need to set the mode only once, so if XMAC is
775 * already out of reset, it means the mode has already been set,
776 * and it must not* reset the XMAC again, since it controls both
777 * ports of the path
778 **/
779
780 if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
781 MISC_REGISTERS_RESET_REG_2_XMAC)) {
782 DP(NETIF_MSG_LINK, "XMAC already out of reset"
783 " in 4-port mode\n");
784 return;
785 }
786
787 /* Hard reset */
788 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
789 MISC_REGISTERS_RESET_REG_2_XMAC);
790 usleep_range(1000, 1000);
791
792 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
793 MISC_REGISTERS_RESET_REG_2_XMAC);
794 if (is_port4mode) {
795 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
796
797 /* Set the number of ports on the system side to up to 2 */
798 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
799
800 /* Set the number of ports on the Warp Core to 10G */
801 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
802 } else {
803 /* Set the number of ports on the system side to 1 */
804 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
805 if (max_speed == SPEED_10000) {
806 DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
807 " port per path\n");
808 /* Set the number of ports on the Warp Core to 10G */
809 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
810 } else {
811 DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
812 " per path\n");
813 /* Set the number of ports on the Warp Core to 20G */
814 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
815 }
816 }
817 /* Soft reset */
818 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
819 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
820 usleep_range(1000, 1000);
821
822 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
823 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
824
825}
826
827static void bnx2x_xmac_disable(struct link_params *params)
828{
829 u8 port = params->port;
830 struct bnx2x *bp = params->bp;
831 u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
832
833 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
834 MISC_REGISTERS_RESET_REG_2_XMAC) {
835 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
836 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
837 usleep_range(1000, 1000);
838 bnx2x_set_xumac_nig(params, 0, 0);
839 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
840 XMAC_CTRL_REG_SOFT_RESET);
841 }
842}
843
844static int bnx2x_xmac_enable(struct link_params *params,
845 struct link_vars *vars, u8 lb)
846{
847 u32 val, xmac_base;
848 struct bnx2x *bp = params->bp;
849 DP(NETIF_MSG_LINK, "enabling XMAC\n");
850
851 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
852
853 bnx2x_xmac_init(bp, vars->line_speed);
854
855 /*
856 * This register determines on which events the MAC will assert
857 * error on the i/f to the NIG along w/ EOP.
858 */
859
860 /*
861 * This register tells the NIG whether to send traffic to UMAC
862 * or XMAC
863 */
864 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
865
866 /* Set Max packet size */
867 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
868
869 /* CRC append for Tx packets */
870 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
871
872 /* update PFC */
873 bnx2x_update_pfc_xmac(params, vars, 0);
874
875 /* Enable TX and RX */
876 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
877
878 /* Check loopback mode */
879 if (lb)
880 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
881 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
882 bnx2x_set_xumac_nig(params,
883 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
884
885 vars->mac_type = MAC_TYPE_XMAC;
886
887 return 0;
888}
536static int bnx2x_emac_enable(struct link_params *params, 889static int bnx2x_emac_enable(struct link_params *params,
537 struct link_vars *vars, u8 lb) 890 struct link_vars *vars, u8 lb)
538{ 891{
@@ -785,95 +1138,341 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
785 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 1138 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
786} 1139}
787 1140
788static void bnx2x_update_pfc_brb(struct link_params *params, 1141
789 struct link_vars *vars, 1142/* PFC BRB internal port configuration params */
790 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 1143struct bnx2x_pfc_brb_threshold_val {
1144 u32 pause_xoff;
1145 u32 pause_xon;
1146 u32 full_xoff;
1147 u32 full_xon;
1148};
1149
1150struct bnx2x_pfc_brb_e3b0_val {
1151 u32 full_lb_xoff_th;
1152 u32 full_lb_xon_threshold;
1153 u32 lb_guarantied;
1154 u32 mac_0_class_t_guarantied;
1155 u32 mac_0_class_t_guarantied_hyst;
1156 u32 mac_1_class_t_guarantied;
1157 u32 mac_1_class_t_guarantied_hyst;
1158};
1159
1160struct bnx2x_pfc_brb_th_val {
1161 struct bnx2x_pfc_brb_threshold_val pauseable_th;
1162 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
1163};
1164static int bnx2x_pfc_brb_get_config_params(
1165 struct link_params *params,
1166 struct bnx2x_pfc_brb_th_val *config_val)
1167{
1168 struct bnx2x *bp = params->bp;
1169 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
1170 if (CHIP_IS_E2(bp)) {
1171 config_val->pauseable_th.pause_xoff =
1172 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
1173 config_val->pauseable_th.pause_xon =
1174 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
1175 config_val->pauseable_th.full_xoff =
1176 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
1177 config_val->pauseable_th.full_xon =
1178 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
1179 /* non pause able*/
1180 config_val->non_pauseable_th.pause_xoff =
1181 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
1182 config_val->non_pauseable_th.pause_xon =
1183 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
1184 config_val->non_pauseable_th.full_xoff =
1185 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
1186 config_val->non_pauseable_th.full_xon =
1187 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
1188 } else if (CHIP_IS_E3A0(bp)) {
1189 config_val->pauseable_th.pause_xoff =
1190 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
1191 config_val->pauseable_th.pause_xon =
1192 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
1193 config_val->pauseable_th.full_xoff =
1194 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
1195 config_val->pauseable_th.full_xon =
1196 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
1197 /* non pause able*/
1198 config_val->non_pauseable_th.pause_xoff =
1199 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
1200 config_val->non_pauseable_th.pause_xon =
1201 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
1202 config_val->non_pauseable_th.full_xoff =
1203 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
1204 config_val->non_pauseable_th.full_xon =
1205 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
1206 } else if (CHIP_IS_E3B0(bp)) {
1207 if (params->phy[INT_PHY].flags &
1208 FLAGS_4_PORT_MODE) {
1209 config_val->pauseable_th.pause_xoff =
1210 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
1211 config_val->pauseable_th.pause_xon =
1212 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
1213 config_val->pauseable_th.full_xoff =
1214 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
1215 config_val->pauseable_th.full_xon =
1216 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
1217 /* non pause able*/
1218 config_val->non_pauseable_th.pause_xoff =
1219 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
1220 config_val->non_pauseable_th.pause_xon =
1221 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
1222 config_val->non_pauseable_th.full_xoff =
1223 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
1224 config_val->non_pauseable_th.full_xon =
1225 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
1226 } else {
1227 config_val->pauseable_th.pause_xoff =
1228 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
1229 config_val->pauseable_th.pause_xon =
1230 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
1231 config_val->pauseable_th.full_xoff =
1232 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
1233 config_val->pauseable_th.full_xon =
1234 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
1235 /* non pause able*/
1236 config_val->non_pauseable_th.pause_xoff =
1237 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
1238 config_val->non_pauseable_th.pause_xon =
1239 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
1240 config_val->non_pauseable_th.full_xoff =
1241 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
1242 config_val->non_pauseable_th.full_xon =
1243 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
1244 }
1245 } else
1246 return -EINVAL;
1247
1248 return 0;
1249}
1250
1251
1252static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
1253 struct bnx2x_pfc_brb_e3b0_val
1254 *e3b0_val,
1255 u32 cos0_pauseable,
1256 u32 cos1_pauseable)
1257{
1258 if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
1259 e3b0_val->full_lb_xoff_th =
1260 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
1261 e3b0_val->full_lb_xon_threshold =
1262 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
1263 e3b0_val->lb_guarantied =
1264 PFC_E3B0_4P_LB_GUART;
1265 e3b0_val->mac_0_class_t_guarantied =
1266 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
1267 e3b0_val->mac_0_class_t_guarantied_hyst =
1268 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
1269 e3b0_val->mac_1_class_t_guarantied =
1270 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
1271 e3b0_val->mac_1_class_t_guarantied_hyst =
1272 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
1273 } else {
1274 e3b0_val->full_lb_xoff_th =
1275 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
1276 e3b0_val->full_lb_xon_threshold =
1277 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
1278 e3b0_val->mac_0_class_t_guarantied_hyst =
1279 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
1280 e3b0_val->mac_1_class_t_guarantied =
1281 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
1282 e3b0_val->mac_1_class_t_guarantied_hyst =
1283 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
1284
1285 if (cos0_pauseable != cos1_pauseable) {
1286 /* nonpauseable= Lossy + pauseable = Lossless*/
1287 e3b0_val->lb_guarantied =
1288 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
1289 e3b0_val->mac_0_class_t_guarantied =
1290 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
1291 } else if (cos0_pauseable) {
1292 /* Lossless +Lossless*/
1293 e3b0_val->lb_guarantied =
1294 PFC_E3B0_2P_PAUSE_LB_GUART;
1295 e3b0_val->mac_0_class_t_guarantied =
1296 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
1297 } else {
1298 /* Lossy +Lossy*/
1299 e3b0_val->lb_guarantied =
1300 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
1301 e3b0_val->mac_0_class_t_guarantied =
1302 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
1303 }
1304 }
1305}
1306static int bnx2x_update_pfc_brb(struct link_params *params,
1307 struct link_vars *vars,
1308 struct bnx2x_nig_brb_pfc_port_params
1309 *pfc_params)
791{ 1310{
792 struct bnx2x *bp = params->bp; 1311 struct bnx2x *bp = params->bp;
1312 struct bnx2x_pfc_brb_th_val config_val = { {0} };
1313 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
1314 &config_val.pauseable_th;
1315 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
793 int set_pfc = params->feature_config_flags & 1316 int set_pfc = params->feature_config_flags &
794 FEATURE_CONFIG_PFC_ENABLED; 1317 FEATURE_CONFIG_PFC_ENABLED;
1318 int bnx2x_status = 0;
1319 u8 port = params->port;
795 1320
796 /* default - pause configuration */ 1321 /* default - pause configuration */
797 u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE; 1322 reg_th_config = &config_val.pauseable_th;
798 u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE; 1323 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
799 u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE; 1324 if (0 != bnx2x_status)
800 u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE; 1325 return bnx2x_status;
801 1326
802 if (set_pfc && pfc_params) 1327 if (set_pfc && pfc_params)
803 /* First COS */ 1328 /* First COS */
804 if (!pfc_params->cos0_pauseable) { 1329 if (!pfc_params->cos0_pauseable)
805 pause_xoff_th = 1330 reg_th_config = &config_val.non_pauseable_th;
806 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
807 pause_xon_th =
808 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
809 full_xoff_th =
810 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
811 full_xon_th =
812 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
813 }
814 /* 1331 /*
815 * The number of free blocks below which the pause signal to class 0 1332 * The number of free blocks below which the pause signal to class 0
816 * of MAC #n is asserted. n=0,1 1333 * of MAC #n is asserted. n=0,1
817 */ 1334 */
818 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th); 1335 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
1336 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
1337 reg_th_config->pause_xoff);
819 /* 1338 /*
820 * The number of free blocks above which the pause signal to class 0 1339 * The number of free blocks above which the pause signal to class 0
821 * of MAC #n is de-asserted. n=0,1 1340 * of MAC #n is de-asserted. n=0,1
822 */ 1341 */
823 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th); 1342 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
1343 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
824 /* 1344 /*
825 * The number of free blocks below which the full signal to class 0 1345 * The number of free blocks below which the full signal to class 0
826 * of MAC #n is asserted. n=0,1 1346 * of MAC #n is asserted. n=0,1
827 */ 1347 */
828 REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th); 1348 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
1349 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
829 /* 1350 /*
830 * The number of free blocks above which the full signal to class 0 1351 * The number of free blocks above which the full signal to class 0
831 * of MAC #n is de-asserted. n=0,1 1352 * of MAC #n is de-asserted. n=0,1
832 */ 1353 */
833 REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th); 1354 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
1355 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
834 1356
835 if (set_pfc && pfc_params) { 1357 if (set_pfc && pfc_params) {
836 /* Second COS */ 1358 /* Second COS */
837 if (pfc_params->cos1_pauseable) { 1359 if (pfc_params->cos1_pauseable)
838 pause_xoff_th = 1360 reg_th_config = &config_val.pauseable_th;
839 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE; 1361 else
840 pause_xon_th = 1362 reg_th_config = &config_val.non_pauseable_th;
841 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
842 full_xoff_th =
843 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
844 full_xon_th =
845 PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
846 } else {
847 pause_xoff_th =
848 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
849 pause_xon_th =
850 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
851 full_xoff_th =
852 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
853 full_xon_th =
854 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
855 }
856 /* 1363 /*
857 * The number of free blocks below which the pause signal to 1364 * The number of free blocks below which the pause signal to
858 * class 1 of MAC #n is asserted. n=0,1 1365 * class 1 of MAC #n is asserted. n=0,1
859 */ 1366 **/
860 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th); 1367 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
1368 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
1369 reg_th_config->pause_xoff);
861 /* 1370 /*
862 * The number of free blocks above which the pause signal to 1371 * The number of free blocks above which the pause signal to
863 * class 1 of MAC #n is de-asserted. n=0,1 1372 * class 1 of MAC #n is de-asserted. n=0,1
864 */ 1373 */
865 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th); 1374 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
1375 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
1376 reg_th_config->pause_xon);
866 /* 1377 /*
867 * The number of free blocks below which the full signal to 1378 * The number of free blocks below which the full signal to
868 * class 1 of MAC #n is asserted. n=0,1 1379 * class 1 of MAC #n is asserted. n=0,1
869 */ 1380 */
870 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th); 1381 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
1382 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
1383 reg_th_config->full_xoff);
871 /* 1384 /*
872 * The number of free blocks above which the full signal to 1385 * The number of free blocks above which the full signal to
873 * class 1 of MAC #n is de-asserted. n=0,1 1386 * class 1 of MAC #n is de-asserted. n=0,1
874 */ 1387 */
875 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th); 1388 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
876 } 1389 BRB1_REG_FULL_1_XON_THRESHOLD_0,
1390 reg_th_config->full_xon);
1391
1392
1393 if (CHIP_IS_E3B0(bp)) {
1394 /*Should be done by init tool */
1395 /*
1396 * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
1397 * reset value
1398 * 944
1399 */
1400
1401 /**
1402 * The hysteresis on the guarantied buffer space for the Lb port
1403 * before signaling XON.
1404 **/
1405 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
1406
1407 bnx2x_pfc_brb_get_e3b0_config_params(
1408 params,
1409 &e3b0_val,
1410 pfc_params->cos0_pauseable,
1411 pfc_params->cos1_pauseable);
1412 /**
1413 * The number of free blocks below which the full signal to the
1414 * LB port is asserted.
1415 */
1416 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
1417 e3b0_val.full_lb_xoff_th);
1418 /**
1419 * The number of free blocks above which the full signal to the
1420 * LB port is de-asserted.
1421 */
1422 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
1423 e3b0_val.full_lb_xon_threshold);
1424 /**
1425 * The number of blocks guarantied for the MAC #n port. n=0,1
1426 */
1427
1428 /*The number of blocks guarantied for the LB port.*/
1429 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
1430 e3b0_val.lb_guarantied);
1431
1432 /**
1433 * The number of blocks guarantied for the MAC #n port.
1434 */
1435 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
1436 2 * e3b0_val.mac_0_class_t_guarantied);
1437 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
1438 2 * e3b0_val.mac_1_class_t_guarantied);
1439 /**
1440 * The number of blocks guarantied for class #t in MAC0. t=0,1
1441 */
1442 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
1443 e3b0_val.mac_0_class_t_guarantied);
1444 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
1445 e3b0_val.mac_0_class_t_guarantied);
1446 /**
1447 * The hysteresis on the guarantied buffer space for class in
1448 * MAC0. t=0,1
1449 */
1450 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
1451 e3b0_val.mac_0_class_t_guarantied_hyst);
1452 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
1453 e3b0_val.mac_0_class_t_guarantied_hyst);
1454
1455 /**
1456 * The number of blocks guarantied for class #t in MAC1.t=0,1
1457 */
1458 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
1459 e3b0_val.mac_1_class_t_guarantied);
1460 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
1461 e3b0_val.mac_1_class_t_guarantied);
1462 /**
1463 * The hysteresis on the guarantied buffer space for class #t
1464 * in MAC1. t=0,1
1465 */
1466 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
1467 e3b0_val.mac_1_class_t_guarantied_hyst);
1468 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
1469 e3b0_val.mac_1_class_t_guarantied_hyst);
1470
1471 }
1472
1473 }
1474
1475 return bnx2x_status;
877} 1476}
878 1477
879/****************************************************************************** 1478/******************************************************************************
@@ -931,9 +1530,9 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
931 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 1530 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
932 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0; 1531 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
933 u32 pkt_priority_to_cos = 0; 1532 u32 pkt_priority_to_cos = 0;
934 u32 val;
935 struct bnx2x *bp = params->bp; 1533 struct bnx2x *bp = params->bp;
936 int port = params->port; 1534 u8 port = params->port;
1535
937 int set_pfc = params->feature_config_flags & 1536 int set_pfc = params->feature_config_flags &
938 FEATURE_CONFIG_PFC_ENABLED; 1537 FEATURE_CONFIG_PFC_ENABLED;
939 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 1538 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
@@ -954,6 +1553,9 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
954 pause_enable = 0; 1553 pause_enable = 0;
955 llfc_out_en = 0; 1554 llfc_out_en = 0;
956 llfc_enable = 0; 1555 llfc_enable = 0;
1556 if (CHIP_IS_E3(bp))
1557 ppp_enable = 0;
1558 else
957 ppp_enable = 1; 1559 ppp_enable = 1;
958 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 1560 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
959 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 1561 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
@@ -972,6 +1574,9 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
972 xcm0_out_en = 1; 1574 xcm0_out_en = 1;
973 } 1575 }
974 1576
1577 if (CHIP_IS_E3(bp))
1578 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
1579 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
975 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : 1580 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
976 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 1581 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
977 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : 1582 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
@@ -993,20 +1598,6 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
993 /* HW PFC TX enable */ 1598 /* HW PFC TX enable */
994 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable); 1599 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
995 1600
996 /* 0x2 = BMAC, 0x1= EMAC */
997 switch (vars->mac_type) {
998 case MAC_TYPE_EMAC:
999 val = 1;
1000 break;
1001 case MAC_TYPE_BMAC:
1002 val = 0;
1003 break;
1004 default:
1005 val = 0;
1006 break;
1007 }
1008 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
1009
1010 if (nig_params) { 1601 if (nig_params) {
1011 u8 i = 0; 1602 u8 i = 0;
1012 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 1603 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
@@ -1028,8 +1619,7 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
1028 pkt_priority_to_cos); 1619 pkt_priority_to_cos);
1029} 1620}
1030 1621
1031 1622int bnx2x_update_pfc(struct link_params *params,
1032void bnx2x_update_pfc(struct link_params *params,
1033 struct link_vars *vars, 1623 struct link_vars *vars,
1034 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 1624 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
1035{ 1625{
@@ -1040,38 +1630,48 @@ void bnx2x_update_pfc(struct link_params *params,
1040 */ 1630 */
1041 u32 val; 1631 u32 val;
1042 struct bnx2x *bp = params->bp; 1632 struct bnx2x *bp = params->bp;
1043 1633 int bnx2x_status = 0;
1634 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
1044 /* update NIG params */ 1635 /* update NIG params */
1045 bnx2x_update_pfc_nig(params, vars, pfc_params); 1636 bnx2x_update_pfc_nig(params, vars, pfc_params);
1046 1637
1047 /* update BRB params */ 1638 /* update BRB params */
1048 bnx2x_update_pfc_brb(params, vars, pfc_params); 1639 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
1640 if (0 != bnx2x_status)
1641 return bnx2x_status;
1049 1642
1050 if (!vars->link_up) 1643 if (!vars->link_up)
1051 return; 1644 return bnx2x_status;
1052
1053 val = REG_RD(bp, MISC_REG_RESET_REG_2);
1054 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1055 == 0) {
1056 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
1057 bnx2x_emac_enable(params, vars, 0);
1058 return;
1059 }
1060 1645
1061 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); 1646 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
1062 if (CHIP_IS_E2(bp)) 1647 if (CHIP_IS_E3(bp))
1063 bnx2x_update_pfc_bmac2(params, vars, 0); 1648 bnx2x_update_pfc_xmac(params, vars, 0);
1064 else 1649 else {
1065 bnx2x_update_pfc_bmac1(params, vars); 1650 val = REG_RD(bp, MISC_REG_RESET_REG_2);
1651 if ((val &
1652 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1653 == 0) {
1654 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
1655 bnx2x_emac_enable(params, vars, 0);
1656 return bnx2x_status;
1657 }
1066 1658
1067 val = 0; 1659 if (CHIP_IS_E2(bp))
1068 if ((params->feature_config_flags & 1660 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
1069 FEATURE_CONFIG_PFC_ENABLED) || 1661 else
1070 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) 1662 bnx2x_update_pfc_bmac1(params, vars);
1071 val = 1; 1663
1072 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 1664 val = 0;
1665 if ((params->feature_config_flags &
1666 FEATURE_CONFIG_PFC_ENABLED) ||
1667 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1668 val = 1;
1669 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1670 }
1671 return bnx2x_status;
1073} 1672}
1074 1673
1674
1075static int bnx2x_bmac1_enable(struct link_params *params, 1675static int bnx2x_bmac1_enable(struct link_params *params,
1076 struct link_vars *vars, 1676 struct link_vars *vars,
1077 u8 is_lb) 1677 u8 is_lb)
@@ -1819,7 +2419,7 @@ void bnx2x_link_status_update(struct link_params *params,
1819 struct link_vars *vars) 2419 struct link_vars *vars)
1820{ 2420{
1821 struct bnx2x *bp = params->bp; 2421 struct bnx2x *bp = params->bp;
1822 u8 link_10g; 2422 u8 link_10g_plus;
1823 u8 port = params->port; 2423 u8 port = params->port;
1824 u32 sync_offset, media_types; 2424 u32 sync_offset, media_types;
1825 /* Update PHY configuration */ 2425 /* Update PHY configuration */
@@ -1893,17 +2493,19 @@ void bnx2x_link_status_update(struct link_params *params,
1893 } 2493 }
1894 2494
1895 /* anything 10 and over uses the bmac */ 2495 /* anything 10 and over uses the bmac */
1896 link_10g = ((vars->line_speed == SPEED_10000) || 2496 link_10g_plus = (vars->line_speed >= SPEED_10000);
1897 (vars->line_speed == SPEED_12000) || 2497
1898 (vars->line_speed == SPEED_12500) || 2498 if (link_10g_plus) {
1899 (vars->line_speed == SPEED_13000) || 2499 if (USES_WARPCORE(bp))
1900 (vars->line_speed == SPEED_15000) || 2500 vars->mac_type = MAC_TYPE_XMAC;
1901 (vars->line_speed == SPEED_16000)); 2501 else
1902 if (link_10g)
1903 vars->mac_type = MAC_TYPE_BMAC; 2502 vars->mac_type = MAC_TYPE_BMAC;
2503 } else {
2504 if (USES_WARPCORE(bp))
2505 vars->mac_type = MAC_TYPE_UMAC;
1904 else 2506 else
1905 vars->mac_type = MAC_TYPE_EMAC; 2507 vars->mac_type = MAC_TYPE_EMAC;
1906 2508 }
1907 } else { /* link down */ 2509 } else { /* link down */
1908 DP(NETIF_MSG_LINK, "phy link down\n"); 2510 DP(NETIF_MSG_LINK, "phy link down\n");
1909 2511
@@ -3507,14 +4109,21 @@ static int bnx2x_update_link_down(struct link_params *params,
3507 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 4109 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3508 4110
3509 /* disable emac */ 4111 /* disable emac */
3510 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 4112 if (!CHIP_IS_E3(bp))
4113 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3511 4114
3512 msleep(10); 4115 msleep(10);
3513 4116 /* reset BigMac/Xmac */
3514 /* reset BigMac */ 4117 if (CHIP_IS_E1x(bp) ||
3515 bnx2x_bmac_rx_disable(bp, params->port); 4118 CHIP_IS_E2(bp)) {
3516 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 4119 bnx2x_bmac_rx_disable(bp, params->port);
4120 REG_WR(bp, GRCBASE_MISC +
4121 MISC_REGISTERS_RESET_REG_2_CLEAR,
3517 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 4122 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4123 }
4124 if (CHIP_IS_E3(bp))
4125 bnx2x_xmac_disable(params);
4126
3518 return 0; 4127 return 0;
3519} 4128}
3520 4129
@@ -3535,25 +4144,36 @@ static int bnx2x_update_link_up(struct link_params *params,
3535 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 4144 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3536 vars->link_status |= 4145 vars->link_status |=
3537 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 4146 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
3538 4147 if (USES_WARPCORE(bp)) {
3539 if (link_10g) { 4148 if (link_10g)
3540 bnx2x_bmac_enable(params, vars, 0); 4149 bnx2x_xmac_enable(params, vars, 0);
4150 else
4151 bnx2x_umac_enable(params, vars, 0);
3541 bnx2x_set_led(params, vars, 4152 bnx2x_set_led(params, vars,
3542 LED_MODE_OPER, SPEED_10000); 4153 LED_MODE_OPER, vars->line_speed);
3543 } else { 4154 }
3544 rc = bnx2x_emac_program(params, vars); 4155 if ((CHIP_IS_E1x(bp) ||
3545 4156 CHIP_IS_E2(bp))) {
3546 bnx2x_emac_enable(params, vars, 0); 4157 if (link_10g) {
4158 bnx2x_bmac_enable(params, vars, 0);
3547 4159
3548 /* AN complete? */ 4160 bnx2x_set_led(params, vars,
3549 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 4161 LED_MODE_OPER, SPEED_10000);
3550 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 4162 } else {
3551 SINGLE_MEDIA_DIRECT(params)) 4163 rc = bnx2x_emac_program(params, vars);
3552 bnx2x_set_gmii_tx_driver(params); 4164 bnx2x_emac_enable(params, vars, 0);
4165
4166 /* AN complete? */
4167 if ((vars->link_status &
4168 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
4169 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
4170 SINGLE_MEDIA_DIRECT(params))
4171 bnx2x_set_gmii_tx_driver(params);
4172 }
3553 } 4173 }
3554 4174
3555 /* PBF - link up */ 4175 /* PBF - link up */
3556 if (!(CHIP_IS_E2(bp))) 4176 if (CHIP_IS_E1x(bp))
3557 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, 4177 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3558 vars->line_speed); 4178 vars->line_speed);
3559 4179
@@ -3617,7 +4237,8 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3617 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 4237 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3618 4238
3619 /* disable emac */ 4239 /* disable emac */
3620 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 4240 if (!CHIP_IS_E3(bp))
4241 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3621 4242
3622 /* 4243 /*
3623 * Step 1: 4244 * Step 1:
@@ -7871,6 +8492,43 @@ void bnx2x_init_emac_loopback(struct link_params *params,
7871 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 8492 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7872} 8493}
7873 8494
8495void bnx2x_init_xmac_loopback(struct link_params *params,
8496 struct link_vars *vars)
8497{
8498 struct bnx2x *bp = params->bp;
8499 vars->link_up = 1;
8500 if (!params->req_line_speed[0])
8501 vars->line_speed = SPEED_10000;
8502 else
8503 vars->line_speed = params->req_line_speed[0];
8504 vars->duplex = DUPLEX_FULL;
8505 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8506 vars->mac_type = MAC_TYPE_XMAC;
8507 vars->phy_flags = PHY_XGXS_FLAG;
8508 /*
8509 * Set WC to loopback mode since link is required to provide clock
8510 * to the XMAC in 20G mode
8511 */
8512
8513 bnx2x_xmac_enable(params, vars, 1);
8514 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
8515}
8516
8517void bnx2x_init_umac_loopback(struct link_params *params,
8518 struct link_vars *vars)
8519{
8520 struct bnx2x *bp = params->bp;
8521 vars->link_up = 1;
8522 vars->line_speed = SPEED_1000;
8523 vars->duplex = DUPLEX_FULL;
8524 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8525 vars->mac_type = MAC_TYPE_UMAC;
8526 vars->phy_flags = PHY_XGXS_FLAG;
8527 bnx2x_umac_enable(params, vars, 1);
8528
8529 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
8530}
8531
7874void bnx2x_init_xgxs_loopback(struct link_params *params, 8532void bnx2x_init_xgxs_loopback(struct link_params *params,
7875 struct link_vars *vars) 8533 struct link_vars *vars)
7876{ 8534{
@@ -7883,17 +8541,23 @@ void bnx2x_init_xgxs_loopback(struct link_params *params,
7883 else 8541 else
7884 vars->line_speed = SPEED_10000; 8542 vars->line_speed = SPEED_10000;
7885 8543
7886 8544 if (!USES_WARPCORE(bp))
7887 bnx2x_xgxs_deassert(params); 8545 bnx2x_xgxs_deassert(params);
7888 bnx2x_link_initialize(params, vars); 8546 bnx2x_link_initialize(params, vars);
7889 8547
7890 if (params->req_line_speed[0] == SPEED_1000) { 8548 if (params->req_line_speed[0] == SPEED_1000) {
7891 bnx2x_emac_program(params, vars); 8549 if (USES_WARPCORE(bp))
7892 bnx2x_emac_enable(params, vars, 0); 8550 bnx2x_umac_enable(params, vars, 0);
7893 8551 else {
7894 } else 8552 bnx2x_emac_program(params, vars);
7895 bnx2x_bmac_enable(params, vars, 0); 8553 bnx2x_emac_enable(params, vars, 0);
7896 8554 }
8555 } else {
8556 if (USES_WARPCORE(bp))
8557 bnx2x_xmac_enable(params, vars, 0);
8558 else
8559 bnx2x_bmac_enable(params, vars, 0);
8560 }
7897 8561
7898 if (params->loopback_mode == LOOPBACK_XGXS) { 8562 if (params->loopback_mode == LOOPBACK_XGXS) {
7899 /* set 10G XGXS loopback */ 8563 /* set 10G XGXS loopback */
@@ -7957,17 +8621,23 @@ int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7957 case LOOPBACK_EMAC: 8621 case LOOPBACK_EMAC:
7958 bnx2x_init_emac_loopback(params, vars); 8622 bnx2x_init_emac_loopback(params, vars);
7959 break; 8623 break;
8624 case LOOPBACK_XMAC:
8625 bnx2x_init_xmac_loopback(params, vars);
8626 break;
8627 case LOOPBACK_UMAC:
8628 bnx2x_init_umac_loopback(params, vars);
8629 break;
7960 case LOOPBACK_XGXS: 8630 case LOOPBACK_XGXS:
7961 case LOOPBACK_EXT_PHY: 8631 case LOOPBACK_EXT_PHY:
7962 bnx2x_init_xgxs_loopback(params, vars); 8632 bnx2x_init_xgxs_loopback(params, vars);
7963 break; 8633 break;
7964 default: 8634 default:
7965 /* No loopback */ 8635 if (!CHIP_IS_E3(bp)) {
7966 if (params->switch_cfg == SWITCH_CFG_10G) 8636 if (params->switch_cfg == SWITCH_CFG_10G)
7967 bnx2x_xgxs_deassert(params); 8637 bnx2x_xgxs_deassert(params);
7968 else 8638 else
7969 bnx2x_serdes_deassert(bp, params->port); 8639 bnx2x_serdes_deassert(bp, params->port);
7970 8640 }
7971 bnx2x_link_initialize(params, vars); 8641 bnx2x_link_initialize(params, vars);
7972 msleep(30); 8642 msleep(30);
7973 bnx2x_link_int_enable(params); 8643 bnx2x_link_int_enable(params);
@@ -7995,14 +8665,19 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7995 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 8665 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7996 8666
7997 /* disable nig egress interface */ 8667 /* disable nig egress interface */
7998 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 8668 if (!CHIP_IS_E3(bp)) {
7999 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 8669 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
8670 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
8671 }
8000 8672
8001 /* Stop BigMac rx */ 8673 /* Stop BigMac rx */
8002 bnx2x_bmac_rx_disable(bp, port); 8674 if (!CHIP_IS_E3(bp))
8003 8675 bnx2x_bmac_rx_disable(bp, port);
8676 else
8677 bnx2x_xmac_disable(params);
8004 /* disable emac */ 8678 /* disable emac */
8005 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 8679 if (!CHIP_IS_E3(bp))
8680 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
8006 8681
8007 msleep(10); 8682 msleep(10);
8008 /* The PHY reset is controlled by GPIO 1 8683 /* The PHY reset is controlled by GPIO 1
@@ -8038,10 +8713,10 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
8038 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 8713 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
8039 8714
8040 /* disable nig ingress interface */ 8715 /* disable nig ingress interface */
8041 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 8716 if (!CHIP_IS_E3(bp)) {
8042 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 8717 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
8043 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); 8718 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
8044 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 8719 }
8045 vars->link_up = 0; 8720 vars->link_up = 0;
8046 return 0; 8721 return 0;
8047} 8722}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 09:21:50 -0400