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-rw-r--r--drivers/net/bnx2x/bnx2x_cmn.h918
1 files changed, 699 insertions, 219 deletions
diff --git a/drivers/net/bnx2x/bnx2x_cmn.h b/drivers/net/bnx2x/bnx2x_cmn.h
index d1979b1a7ed2..1a3545bd8a92 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/bnx2x/bnx2x_cmn.h
@@ -1,6 +1,6 @@
1/* bnx2x_cmn.h: Broadcom Everest network driver. 1/* bnx2x_cmn.h: Broadcom Everest network driver.
2 * 2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation 3 * Copyright (c) 2007-2011 Broadcom Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 6 * it under the terms of the GNU General Public License as published by
@@ -23,249 +23,279 @@
23 23
24#include "bnx2x.h" 24#include "bnx2x.h"
25 25
26extern int num_queues;
27
28/************************ Macros ********************************/
29#define BNX2X_PCI_FREE(x, y, size) \
30 do { \
31 if (x) { \
32 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
33 x = NULL; \
34 y = 0; \
35 } \
36 } while (0)
37
38#define BNX2X_FREE(x) \
39 do { \
40 if (x) { \
41 kfree((void *)x); \
42 x = NULL; \
43 } \
44 } while (0)
45
46#define BNX2X_PCI_ALLOC(x, y, size) \
47 do { \
48 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
49 if (x == NULL) \
50 goto alloc_mem_err; \
51 memset((void *)x, 0, size); \
52 } while (0)
53
54#define BNX2X_ALLOC(x, size) \
55 do { \
56 x = kzalloc(size, GFP_KERNEL); \
57 if (x == NULL) \
58 goto alloc_mem_err; \
59 } while (0)
26 60
27/*********************** Interfaces **************************** 61/*********************** Interfaces ****************************
28 * Functions that need to be implemented by each driver version 62 * Functions that need to be implemented by each driver version
29 */ 63 */
30 64
31/** 65/**
32 * Initialize link parameters structure variables. 66 * bnx2x_initial_phy_init - initialize link parameters structure variables.
33 * 67 *
34 * @param bp 68 * @bp: driver handle
35 * @param load_mode 69 * @load_mode: current mode
36 *
37 * @return u8
38 */ 70 */
39u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 71u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
40 72
41/** 73/**
42 * Configure hw according to link parameters structure. 74 * bnx2x_link_set - configure hw according to link parameters structure.
43 * 75 *
44 * @param bp 76 * @bp: driver handle
45 */ 77 */
46void bnx2x_link_set(struct bnx2x *bp); 78void bnx2x_link_set(struct bnx2x *bp);
47 79
48/** 80/**
49 * Query link status 81 * bnx2x_link_test - query link status.
50 * 82 *
51 * @param bp 83 * @bp: driver handle
84 * @is_serdes: bool
52 * 85 *
53 * @return 0 - link is UP 86 * Returns 0 if link is UP.
54 */ 87 */
55u8 bnx2x_link_test(struct bnx2x *bp); 88u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
56 89
57/** 90/**
58 * Handles link status change 91 * bnx2x__link_status_update - handles link status change.
59 * 92 *
60 * @param bp 93 * @bp: driver handle
61 */ 94 */
62void bnx2x__link_status_update(struct bnx2x *bp); 95void bnx2x__link_status_update(struct bnx2x *bp);
63 96
64/** 97/**
65 * MSI-X slowpath interrupt handler 98 * bnx2x_link_report - report link status to upper layer.
66 * 99 *
67 * @param irq 100 * @bp: driver handle
68 * @param dev_instance 101 */
102void bnx2x_link_report(struct bnx2x *bp);
103
104/* None-atomic version of bnx2x_link_report() */
105void __bnx2x_link_report(struct bnx2x *bp);
106
107/**
108 * bnx2x_get_mf_speed - calculate MF speed.
69 * 109 *
70 * @return irqreturn_t 110 * @bp: driver handle
111 *
112 * Takes into account current linespeed and MF configuration.
71 */ 113 */
72irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 114u16 bnx2x_get_mf_speed(struct bnx2x *bp);
73 115
74/** 116/**
75 * non MSI-X interrupt handler 117 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
76 * 118 *
77 * @param irq 119 * @irq: irq number
78 * @param dev_instance 120 * @dev_instance: private instance
121 */
122irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
123
124/**
125 * bnx2x_interrupt - non MSI-X interrupt handler
79 * 126 *
80 * @return irqreturn_t 127 * @irq: irq number
128 * @dev_instance: private instance
81 */ 129 */
82irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 130irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
83#ifdef BCM_CNIC 131#ifdef BCM_CNIC
84 132
85/** 133/**
86 * Send command to cnic driver 134 * bnx2x_cnic_notify - send command to cnic driver
87 * 135 *
88 * @param bp 136 * @bp: driver handle
89 * @param cmd 137 * @cmd: command
90 */ 138 */
91int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 139int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
92 140
93/** 141/**
94 * Provides cnic information for proper interrupt handling 142 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
95 * 143 *
96 * @param bp 144 * @bp: driver handle
97 */ 145 */
98void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 146void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
99#endif 147#endif
100 148
101/** 149/**
102 * Enable HW interrupts. 150 * bnx2x_int_enable - enable HW interrupts.
103 * 151 *
104 * @param bp 152 * @bp: driver handle
105 */ 153 */
106void bnx2x_int_enable(struct bnx2x *bp); 154void bnx2x_int_enable(struct bnx2x *bp);
107 155
108/** 156/**
109 * Disable interrupts. This function ensures that there are no 157 * bnx2x_int_disable_sync - disable interrupts.
110 * ISRs or SP DPCs (sp_task) are running after it returns. 158 *
159 * @bp: driver handle
160 * @disable_hw: true, disable HW interrupts.
111 * 161 *
112 * @param bp 162 * This function ensures that there are no
113 * @param disable_hw if true, disable HW interrupts. 163 * ISRs or SP DPCs (sp_task) are running after it returns.
114 */ 164 */
115void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 165void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
116 166
117/** 167/**
118 * Init HW blocks according to current initialization stage: 168 * bnx2x_init_firmware - loads device firmware
119 * COMMON, PORT or FUNCTION.
120 * 169 *
121 * @param bp 170 * @bp: driver handle
122 * @param load_code: COMMON, PORT or FUNCTION 171 */
172int bnx2x_init_firmware(struct bnx2x *bp);
173
174/**
175 * bnx2x_init_hw - init HW blocks according to current initialization stage.
123 * 176 *
124 * @return int 177 * @bp: driver handle
178 * @load_code: COMMON, PORT or FUNCTION
125 */ 179 */
126int bnx2x_init_hw(struct bnx2x *bp, u32 load_code); 180int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
127 181
128/** 182/**
129 * Init driver internals: 183 * bnx2x_nic_init - init driver internals.
184 *
185 * @bp: driver handle
186 * @load_code: COMMON, PORT or FUNCTION
187 *
188 * Initializes:
130 * - rings 189 * - rings
131 * - status blocks 190 * - status blocks
132 * - etc. 191 * - etc.
133 *
134 * @param bp
135 * @param load_code COMMON, PORT or FUNCTION
136 */ 192 */
137void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); 193void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
138 194
139/** 195/**
140 * Allocate driver's memory. 196 * bnx2x_alloc_mem - allocate driver's memory.
141 *
142 * @param bp
143 * 197 *
144 * @return int 198 * @bp: driver handle
145 */ 199 */
146int bnx2x_alloc_mem(struct bnx2x *bp); 200int bnx2x_alloc_mem(struct bnx2x *bp);
147 201
148/** 202/**
149 * Release driver's memory. 203 * bnx2x_free_mem - release driver's memory.
150 * 204 *
151 * @param bp 205 * @bp: driver handle
152 */ 206 */
153void bnx2x_free_mem(struct bnx2x *bp); 207void bnx2x_free_mem(struct bnx2x *bp);
154 208
155/** 209/**
156 * Bring up a leading (the first) eth Client. 210 * bnx2x_setup_client - setup eth client.
157 * 211 *
158 * @param bp 212 * @bp: driver handle
159 * 213 * @fp: pointer to fastpath structure
160 * @return int 214 * @is_leading: boolean
161 */ 215 */
162int bnx2x_setup_leading(struct bnx2x *bp); 216int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
217 int is_leading);
163 218
164/** 219/**
165 * Setup non-leading eth Client. 220 * bnx2x_set_num_queues - set number of queues according to mode.
166 *
167 * @param bp
168 * @param fp
169 * 221 *
170 * @return int 222 * @bp: driver handle
171 */ 223 */
172int bnx2x_setup_multi(struct bnx2x *bp, int index); 224void bnx2x_set_num_queues(struct bnx2x *bp);
173 225
174/** 226/**
175 * Set number of quueus according to mode and number of available 227 * bnx2x_chip_cleanup - cleanup chip internals.
176 * msi-x vectors
177 * 228 *
178 * @param bp 229 * @bp: driver handle
230 * @unload_mode: COMMON, PORT, FUNCTION
179 * 231 *
180 */
181void bnx2x_set_num_queues_msix(struct bnx2x *bp);
182
183/**
184 * Cleanup chip internals:
185 * - Cleanup MAC configuration. 232 * - Cleanup MAC configuration.
186 * - Close clients. 233 * - Closes clients.
187 * - etc. 234 * - etc.
188 *
189 * @param bp
190 * @param unload_mode
191 */ 235 */
192void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); 236void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
193 237
194/** 238/**
195 * Acquire HW lock. 239 * bnx2x_acquire_hw_lock - acquire HW lock.
196 * 240 *
197 * @param bp 241 * @bp: driver handle
198 * @param resource Resource bit which was locked 242 * @resource: resource bit which was locked
199 *
200 * @return int
201 */ 243 */
202int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 244int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
203 245
204/** 246/**
205 * Release HW lock. 247 * bnx2x_release_hw_lock - release HW lock.
206 *
207 * @param bp driver handle
208 * @param resource Resource bit which was locked
209 * 248 *
210 * @return int 249 * @bp: driver handle
250 * @resource: resource bit which was locked
211 */ 251 */
212int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 252int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
213 253
214/** 254/**
215 * Configure eth MAC address in the HW according to the value in 255 * bnx2x_set_eth_mac - configure eth MAC address in the HW
216 * netdev->dev_addr for 57711
217 * 256 *
218 * @param bp driver handle 257 * @bp: driver handle
219 * @param set 258 * @set: set or clear
220 */
221void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set);
222
223/**
224 * Configure eth MAC address in the HW according to the value in
225 * netdev->dev_addr for 57710
226 * 259 *
227 * @param bp driver handle 260 * Configures according to the value in netdev->dev_addr.
228 * @param set
229 */ 261 */
230void bnx2x_set_eth_mac_addr_e1(struct bnx2x *bp, int set); 262void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
231 263
232#ifdef BCM_CNIC 264#ifdef BCM_CNIC
233/** 265/**
234 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH 266 * bnx2x_set_fip_eth_mac_addr - Set/Clear FIP MAC(s)
235 * MAC(s). The function will wait until the ramrod completion
236 * returns.
237 * 267 *
238 * @param bp driver handle 268 * @bp: driver handle
239 * @param set set or clear the CAM entry 269 * @set: set or clear the CAM entry
240 * 270 *
241 * @return 0 if cussess, -ENODEV if ramrod doesn't return. 271 * Used next enties in the CAM after the ETH MAC(s).
272 * This function will wait until the ramdord completion returns.
273 * Return 0 if cussess, -ENODEV if ramrod doesn't return.
242 */ 274 */
243int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set); 275int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set);
244#endif
245 276
246/** 277/**
247 * Initialize status block in FW and HW 278 * bnx2x_set_all_enode_macs - Set/Clear ALL_ENODE mcast MAC.
248 * 279 *
249 * @param bp driver handle 280 * @bp: driver handle
250 * @param sb host_status_block 281 * @set: set or clear
251 * @param dma_addr_t mapping
252 * @param int sb_id
253 */ 282 */
254void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb, 283int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set);
255 dma_addr_t mapping, int sb_id); 284#endif
256 285
257/** 286/**
258 * Reconfigure FW/HW according to dev->flags rx mode 287 * bnx2x_set_rx_mode - set MAC filtering configurations.
259 * 288 *
260 * @param dev net_device 289 * @dev: netdevice
261 * 290 *
291 * called with netif_tx_lock from dev_mcast.c
262 */ 292 */
263void bnx2x_set_rx_mode(struct net_device *dev); 293void bnx2x_set_rx_mode(struct net_device *dev);
264 294
265/** 295/**
266 * Configure MAC filtering rules in a FW. 296 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW.
267 * 297 *
268 * @param bp driver handle 298 * @bp: driver handle
269 */ 299 */
270void bnx2x_set_storm_rx_mode(struct bnx2x *bp); 300void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
271 301
@@ -277,37 +307,160 @@ bool bnx2x_reset_is_done(struct bnx2x *bp);
277void bnx2x_disable_close_the_gate(struct bnx2x *bp); 307void bnx2x_disable_close_the_gate(struct bnx2x *bp);
278 308
279/** 309/**
280 * Perform statistics handling according to event 310 * bnx2x_stats_handle - perform statistics handling according to event.
281 * 311 *
282 * @param bp driver handle 312 * @bp: driver handle
283 * @param even tbnx2x_stats_event 313 * @event: bnx2x_stats_event
284 */ 314 */
285void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event); 315void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
286 316
287/** 317/**
288 * Configures FW with client paramteres (like HW VLAN removal) 318 * bnx2x_sp_event - handle ramrods completion.
289 * for each active client. 319 *
320 * @fp: fastpath handle for the event
321 * @rr_cqe: eth_rx_cqe
322 */
323void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
324
325/**
326 * bnx2x_func_start - init function
327 *
328 * @bp: driver handle
290 * 329 *
291 * @param bp 330 * Must be called before sending CLIENT_SETUP for the first client.
292 */ 331 */
293void bnx2x_set_client_config(struct bnx2x *bp); 332int bnx2x_func_start(struct bnx2x *bp);
294 333
295/** 334/**
296 * Handle sp events 335 * bnx2x_ilt_set_info - prepare ILT configurations.
297 * 336 *
298 * @param fp fastpath handle for the event 337 * @bp: driver handle
299 * @param rr_cqe eth_rx_cqe
300 */ 338 */
301void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 339void bnx2x_ilt_set_info(struct bnx2x *bp);
302 340
341/**
342 * bnx2x_dcbx_init - initialize dcbx protocol.
343 *
344 * @bp: driver handle
345 */
346void bnx2x_dcbx_init(struct bnx2x *bp);
347
348/**
349 * bnx2x_set_power_state - set power state to the requested value.
350 *
351 * @bp: driver handle
352 * @state: required state D0 or D3hot
353 *
354 * Currently only D0 and D3hot are supported.
355 */
356int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
357
358/**
359 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
360 *
361 * @bp: driver handle
362 * @value: new value
363 */
364void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
365
366/* dev_close main block */
367int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
368
369/* dev_open main block */
370int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
371
372/* hard_xmit callback */
373netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
374
375/* select_queue callback */
376u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
377
378int bnx2x_change_mac_addr(struct net_device *dev, void *p);
379
380/* NAPI poll Rx part */
381int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
382
383/* NAPI poll Tx part */
384int bnx2x_tx_int(struct bnx2x_fastpath *fp);
385
386/* suspend/resume callbacks */
387int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
388int bnx2x_resume(struct pci_dev *pdev);
389
390/* Release IRQ vectors */
391void bnx2x_free_irq(struct bnx2x *bp);
392
393void bnx2x_free_fp_mem(struct bnx2x *bp);
394int bnx2x_alloc_fp_mem(struct bnx2x *bp);
395
396void bnx2x_init_rx_rings(struct bnx2x *bp);
397void bnx2x_free_skbs(struct bnx2x *bp);
398void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
399void bnx2x_netif_start(struct bnx2x *bp);
400
401/**
402 * bnx2x_enable_msix - set msix configuration.
403 *
404 * @bp: driver handle
405 *
406 * fills msix_table, requests vectors, updates num_queues
407 * according to number of available vectors.
408 */
409int bnx2x_enable_msix(struct bnx2x *bp);
410
411/**
412 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
413 *
414 * @bp: driver handle
415 */
416int bnx2x_enable_msi(struct bnx2x *bp);
417
418/**
419 * bnx2x_poll - NAPI callback
420 *
421 * @napi: napi structure
422 * @budget:
423 *
424 */
425int bnx2x_poll(struct napi_struct *napi, int budget);
426
427/**
428 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
429 *
430 * @bp: driver handle
431 */
432int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
433
434/**
435 * bnx2x_free_mem_bp - release memories outsize main driver structure
436 *
437 * @bp: driver handle
438 */
439void bnx2x_free_mem_bp(struct bnx2x *bp);
440
441/**
442 * bnx2x_change_mtu - change mtu netdev callback
443 *
444 * @dev: net device
445 * @new_mtu: requested mtu
446 *
447 */
448int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
449
450u32 bnx2x_fix_features(struct net_device *dev, u32 features);
451int bnx2x_set_features(struct net_device *dev, u32 features);
452
453/**
454 * bnx2x_tx_timeout - tx timeout netdev callback
455 *
456 * @dev: net device
457 */
458void bnx2x_tx_timeout(struct net_device *dev);
303 459
304static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 460static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
305{ 461{
306 struct host_status_block *fpsb = fp->status_blk;
307
308 barrier(); /* status block is written to by the chip */ 462 barrier(); /* status block is written to by the chip */
309 fp->fp_c_idx = fpsb->c_status_block.status_block_index; 463 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
310 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
311} 464}
312 465
313static inline void bnx2x_update_rx_prod(struct bnx2x *bp, 466static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
@@ -334,8 +487,8 @@ static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
334 wmb(); 487 wmb();
335 488
336 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++) 489 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
337 REG_WR(bp, BAR_USTRORM_INTMEM + 490 REG_WR(bp,
338 USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4, 491 BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4,
339 ((u32 *)&rx_prods)[i]); 492 ((u32 *)&rx_prods)[i]);
340 493
341 mmiowb(); /* keep prod updates ordered */ 494 mmiowb(); /* keep prod updates ordered */
@@ -345,10 +498,77 @@ static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
345 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 498 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
346} 499}
347 500
501static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
502 u8 segment, u16 index, u8 op,
503 u8 update, u32 igu_addr)
504{
505 struct igu_regular cmd_data = {0};
506
507 cmd_data.sb_id_and_flags =
508 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
509 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
510 (update << IGU_REGULAR_BUPDATE_SHIFT) |
511 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
512
513 DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
514 cmd_data.sb_id_and_flags, igu_addr);
515 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
516
517 /* Make sure that ACK is written */
518 mmiowb();
519 barrier();
520}
521
522static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp,
523 u8 idu_sb_id, bool is_Pf)
524{
525 u32 data, ctl, cnt = 100;
526 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
527 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
528 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
529 u32 sb_bit = 1 << (idu_sb_id%32);
530 u32 func_encode = BP_FUNC(bp) |
531 ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
532 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
533
534 /* Not supported in BC mode */
535 if (CHIP_INT_MODE_IS_BC(bp))
536 return;
537
538 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
539 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
540 IGU_REGULAR_CLEANUP_SET |
541 IGU_REGULAR_BCLEANUP;
542
543 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
544 func_encode << IGU_CTRL_REG_FID_SHIFT |
545 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
546
547 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
548 data, igu_addr_data);
549 REG_WR(bp, igu_addr_data, data);
550 mmiowb();
551 barrier();
552 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
553 ctl, igu_addr_ctl);
554 REG_WR(bp, igu_addr_ctl, ctl);
555 mmiowb();
556 barrier();
557
558 /* wait for clean up to finish */
559 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
560 msleep(20);
348 561
349 562
350static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id, 563 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
351 u8 storm, u16 index, u8 op, u8 update) 564 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
565 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
566 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
567 }
568}
569
570static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
571 u8 storm, u16 index, u8 op, u8 update)
352{ 572{
353 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 573 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
354 COMMAND_REG_INT_ACK); 574 COMMAND_REG_INT_ACK);
@@ -369,7 +589,37 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
369 mmiowb(); 589 mmiowb();
370 barrier(); 590 barrier();
371} 591}
372static inline u16 bnx2x_ack_int(struct bnx2x *bp) 592
593static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
594 u16 index, u8 op, u8 update)
595{
596 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
597
598 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
599 igu_addr);
600}
601
602static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
603 u16 index, u8 op, u8 update)
604{
605 if (bp->common.int_block == INT_BLOCK_HC)
606 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
607 else {
608 u8 segment;
609
610 if (CHIP_INT_MODE_IS_BC(bp))
611 segment = storm;
612 else if (igu_sb_id != bp->igu_dsb_id)
613 segment = IGU_SEG_ACCESS_DEF;
614 else if (storm == ATTENTION_ID)
615 segment = IGU_SEG_ACCESS_ATTN;
616 else
617 segment = IGU_SEG_ACCESS_DEF;
618 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
619 }
620}
621
622static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
373{ 623{
374 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 624 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
375 COMMAND_REG_SIMD_MASK); 625 COMMAND_REG_SIMD_MASK);
@@ -378,18 +628,36 @@ static inline u16 bnx2x_ack_int(struct bnx2x *bp)
378 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n", 628 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
379 result, hc_addr); 629 result, hc_addr);
380 630
631 barrier();
381 return result; 632 return result;
382} 633}
383 634
384/* 635static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
385 * fast path service functions 636{
386 */ 637 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
638 u32 result = REG_RD(bp, igu_addr);
639
640 DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
641 result, igu_addr);
642
643 barrier();
644 return result;
645}
646
647static inline u16 bnx2x_ack_int(struct bnx2x *bp)
648{
649 barrier();
650 if (bp->common.int_block == INT_BLOCK_HC)
651 return bnx2x_hc_ack_int(bp);
652 else
653 return bnx2x_igu_ack_int(bp);
654}
387 655
388static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp) 656static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
389{ 657{
390 /* Tell compiler that consumer and producer can change */ 658 /* Tell compiler that consumer and producer can change */
391 barrier(); 659 barrier();
392 return (fp->tx_pkt_prod != fp->tx_pkt_cons); 660 return fp->tx_pkt_prod != fp->tx_pkt_cons;
393} 661}
394 662
395static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp) 663static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
@@ -424,6 +692,29 @@ static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
424 return hw_cons != fp->tx_pkt_cons; 692 return hw_cons != fp->tx_pkt_cons;
425} 693}
426 694
695static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
696{
697 u16 rx_cons_sb;
698
699 /* Tell compiler that status block fields can change */
700 barrier();
701 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
702 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
703 rx_cons_sb++;
704 return (fp->rx_comp_cons != rx_cons_sb);
705}
706
707/**
708 * disables tx from stack point of view
709 *
710 * @bp: driver handle
711 */
712static inline void bnx2x_tx_disable(struct bnx2x *bp)
713{
714 netif_tx_disable(bp->dev);
715 netif_carrier_off(bp->dev);
716}
717
427static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 718static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
428 struct bnx2x_fastpath *fp, u16 index) 719 struct bnx2x_fastpath *fp, u16 index)
429{ 720{
@@ -436,7 +727,7 @@ static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
436 return; 727 return;
437 728
438 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 729 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
439 SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE); 730 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
440 __free_pages(page, PAGES_PER_SGE_SHIFT); 731 __free_pages(page, PAGES_PER_SGE_SHIFT);
441 732
442 sw_buf->page = NULL; 733 sw_buf->page = NULL;
@@ -444,13 +735,67 @@ static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
444 sge->addr_lo = 0; 735 sge->addr_lo = 0;
445} 736}
446 737
447static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 738static inline void bnx2x_add_all_napi(struct bnx2x *bp)
448 struct bnx2x_fastpath *fp, int last)
449{ 739{
450 int i; 740 int i;
451 741
452 for (i = 0; i < last; i++) 742 /* Add NAPI objects */
453 bnx2x_free_rx_sge(bp, fp, i); 743 for_each_napi_queue(bp, i)
744 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
745 bnx2x_poll, BNX2X_NAPI_WEIGHT);
746}
747
748static inline void bnx2x_del_all_napi(struct bnx2x *bp)
749{
750 int i;
751
752 for_each_napi_queue(bp, i)
753 netif_napi_del(&bnx2x_fp(bp, i, napi));
754}
755
756static inline void bnx2x_disable_msi(struct bnx2x *bp)
757{
758 if (bp->flags & USING_MSIX_FLAG) {
759 pci_disable_msix(bp->pdev);
760 bp->flags &= ~USING_MSIX_FLAG;
761 } else if (bp->flags & USING_MSI_FLAG) {
762 pci_disable_msi(bp->pdev);
763 bp->flags &= ~USING_MSI_FLAG;
764 }
765}
766
767static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
768{
769 return num_queues ?
770 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
771 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
772}
773
774static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
775{
776 int i, j;
777
778 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
779 int idx = RX_SGE_CNT * i - 1;
780
781 for (j = 0; j < 2; j++) {
782 SGE_MASK_CLEAR_BIT(fp, idx);
783 idx--;
784 }
785 }
786}
787
788static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
789{
790 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
791 memset(fp->sge_mask, 0xff,
792 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
793
794 /* Clear the two last indices in the page to 1:
795 these are the indices that correspond to the "next" element,
796 hence will never be indicated and should be removed from
797 the calculations. */
798 bnx2x_clear_sge_mask_next_elems(fp);
454} 799}
455 800
456static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp, 801static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
@@ -479,6 +824,7 @@ static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
479 824
480 return 0; 825 return 0;
481} 826}
827
482static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp, 828static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
483 struct bnx2x_fastpath *fp, u16 index) 829 struct bnx2x_fastpath *fp, u16 index)
484{ 830{
@@ -487,14 +833,14 @@ static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
487 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; 833 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
488 dma_addr_t mapping; 834 dma_addr_t mapping;
489 835
490 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); 836 skb = netdev_alloc_skb(bp->dev, fp->rx_buf_size);
491 if (unlikely(skb == NULL)) 837 if (unlikely(skb == NULL))
492 return -ENOMEM; 838 return -ENOMEM;
493 839
494 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size, 840 mapping = dma_map_single(&bp->pdev->dev, skb->data, fp->rx_buf_size,
495 DMA_FROM_DEVICE); 841 DMA_FROM_DEVICE);
496 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 842 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
497 dev_kfree_skb(skb); 843 dev_kfree_skb_any(skb);
498 return -ENOMEM; 844 return -ENOMEM;
499 } 845 }
500 846
@@ -513,7 +859,7 @@ static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
513 * so there is no need to check for dma_mapping_error(). 859 * so there is no need to check for dma_mapping_error().
514 */ 860 */
515static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp, 861static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
516 struct sk_buff *skb, u16 cons, u16 prod) 862 u16 cons, u16 prod)
517{ 863{
518 struct bnx2x *bp = fp->bp; 864 struct bnx2x *bp = fp->bp;
519 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 865 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
@@ -531,32 +877,18 @@ static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
531 *prod_bd = *cons_bd; 877 *prod_bd = *cons_bd;
532} 878}
533 879
534static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 880static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
881 struct bnx2x_fastpath *fp, int last)
535{ 882{
536 int i, j; 883 int i;
537 884
538 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 885 if (fp->disable_tpa)
539 int idx = RX_SGE_CNT * i - 1; 886 return;
540 887
541 for (j = 0; j < 2; j++) { 888 for (i = 0; i < last; i++)
542 SGE_MASK_CLEAR_BIT(fp, idx); 889 bnx2x_free_rx_sge(bp, fp, i);
543 idx--;
544 }
545 }
546} 890}
547 891
548static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
549{
550 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
551 memset(fp->sge_mask, 0xff,
552 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
553
554 /* Clear the two last indices in the page to 1:
555 these are the indices that correspond to the "next" element,
556 hence will never be indicated and should be removed from
557 the calculations. */
558 bnx2x_clear_sge_mask_next_elems(fp);
559}
560static inline void bnx2x_free_tpa_pool(struct bnx2x *bp, 892static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
561 struct bnx2x_fastpath *fp, int last) 893 struct bnx2x_fastpath *fp, int last)
562{ 894{
@@ -574,79 +906,227 @@ static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
574 if (fp->tpa_state[i] == BNX2X_TPA_START) 906 if (fp->tpa_state[i] == BNX2X_TPA_START)
575 dma_unmap_single(&bp->pdev->dev, 907 dma_unmap_single(&bp->pdev->dev,
576 dma_unmap_addr(rx_buf, mapping), 908 dma_unmap_addr(rx_buf, mapping),
577 bp->rx_buf_size, DMA_FROM_DEVICE); 909 fp->rx_buf_size, DMA_FROM_DEVICE);
578 910
579 dev_kfree_skb(skb); 911 dev_kfree_skb(skb);
580 rx_buf->skb = NULL; 912 rx_buf->skb = NULL;
581 } 913 }
582} 914}
583 915
916static inline void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
917{
918 int i;
919
920 for (i = 1; i <= NUM_TX_RINGS; i++) {
921 struct eth_tx_next_bd *tx_next_bd =
922 &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
923
924 tx_next_bd->addr_hi =
925 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
926 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
927 tx_next_bd->addr_lo =
928 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
929 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
930 }
931
932 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
933 fp->tx_db.data.zero_fill1 = 0;
934 fp->tx_db.data.prod = 0;
935
936 fp->tx_pkt_prod = 0;
937 fp->tx_pkt_cons = 0;
938 fp->tx_bd_prod = 0;
939 fp->tx_bd_cons = 0;
940 fp->tx_pkt = 0;
941}
584 942
585static inline void bnx2x_init_tx_ring(struct bnx2x *bp) 943static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
586{ 944{
587 int i, j; 945 int i;
588 946
589 for_each_queue(bp, j) { 947 for_each_tx_queue(bp, i)
590 struct bnx2x_fastpath *fp = &bp->fp[j]; 948 bnx2x_init_tx_ring_one(&bp->fp[i]);
949}
591 950
592 for (i = 1; i <= NUM_TX_RINGS; i++) { 951static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
593 struct eth_tx_next_bd *tx_next_bd = 952{
594 &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 953 int i;
595 954
596 tx_next_bd->addr_hi = 955 for (i = 1; i <= NUM_RX_RINGS; i++) {
597 cpu_to_le32(U64_HI(fp->tx_desc_mapping + 956 struct eth_rx_bd *rx_bd;
598 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
599 tx_next_bd->addr_lo =
600 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
601 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
602 }
603 957
604 fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE; 958 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
605 fp->tx_db.data.zero_fill1 = 0; 959 rx_bd->addr_hi =
606 fp->tx_db.data.prod = 0; 960 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
961 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
962 rx_bd->addr_lo =
963 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
964 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
965 }
966}
967
968static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
969{
970 int i;
607 971
608 fp->tx_pkt_prod = 0; 972 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
609 fp->tx_pkt_cons = 0; 973 struct eth_rx_sge *sge;
610 fp->tx_bd_prod = 0; 974
611 fp->tx_bd_cons = 0; 975 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
612 fp->tx_cons_sb = BNX2X_TX_SB_INDEX; 976 sge->addr_hi =
613 fp->tx_pkt = 0; 977 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
978 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
979
980 sge->addr_lo =
981 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
982 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
614 } 983 }
615} 984}
616static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 985
986static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
617{ 987{
618 u16 rx_cons_sb; 988 int i;
989 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
990 struct eth_rx_cqe_next_page *nextpg;
991
992 nextpg = (struct eth_rx_cqe_next_page *)
993 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
994 nextpg->addr_hi =
995 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
996 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
997 nextpg->addr_lo =
998 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
999 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
1000 }
1001}
619 1002
620 /* Tell compiler that status block fields can change */ 1003/* Returns the number of actually allocated BDs */
621 barrier(); 1004static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
622 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 1005 int rx_ring_size)
623 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 1006{
624 rx_cons_sb++; 1007 struct bnx2x *bp = fp->bp;
625 return (fp->rx_comp_cons != rx_cons_sb); 1008 u16 ring_prod, cqe_ring_prod;
1009 int i;
1010
1011 fp->rx_comp_cons = 0;
1012 cqe_ring_prod = ring_prod = 0;
1013
1014 /* This routine is called only during fo init so
1015 * fp->eth_q_stats.rx_skb_alloc_failed = 0
1016 */
1017 for (i = 0; i < rx_ring_size; i++) {
1018 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
1019 fp->eth_q_stats.rx_skb_alloc_failed++;
1020 continue;
1021 }
1022 ring_prod = NEXT_RX_IDX(ring_prod);
1023 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
1024 WARN_ON(ring_prod <= (i - fp->eth_q_stats.rx_skb_alloc_failed));
1025 }
1026
1027 if (fp->eth_q_stats.rx_skb_alloc_failed)
1028 BNX2X_ERR("was only able to allocate "
1029 "%d rx skbs on queue[%d]\n",
1030 (i - fp->eth_q_stats.rx_skb_alloc_failed), fp->index);
1031
1032 fp->rx_bd_prod = ring_prod;
1033 /* Limit the CQE producer by the CQE ring size */
1034 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
1035 cqe_ring_prod);
1036 fp->rx_pkt = fp->rx_calls = 0;
1037
1038 return i - fp->eth_q_stats.rx_skb_alloc_failed;
1039}
1040
1041#ifdef BCM_CNIC
1042static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
1043{
1044 bnx2x_fcoe(bp, cl_id) = BNX2X_FCOE_ETH_CL_ID +
1045 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
1046 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
1047 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
1048 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
1049 bnx2x_fcoe(bp, bp) = bp;
1050 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
1051 bnx2x_fcoe(bp, index) = FCOE_IDX;
1052 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
1053 bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX;
1054 /* qZone id equals to FW (per path) client id */
1055 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fcoe(bp, cl_id) +
1056 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
1057 ETH_MAX_RX_CLIENTS_E1H);
1058 /* init shortcut */
1059 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = CHIP_IS_E2(bp) ?
1060 USTORM_RX_PRODS_E2_OFFSET(bnx2x_fcoe(bp, cl_qzone_id)) :
1061 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), bnx2x_fcoe_fp(bp)->cl_id);
1062
1063}
1064#endif
1065
1066static inline void __storm_memset_struct(struct bnx2x *bp,
1067 u32 addr, size_t size, u32 *data)
1068{
1069 int i;
1070 for (i = 0; i < size/4; i++)
1071 REG_WR(bp, addr + (i * 4), data[i]);
1072}
1073
1074static inline void storm_memset_mac_filters(struct bnx2x *bp,
1075 struct tstorm_eth_mac_filter_config *mac_filters,
1076 u16 abs_fid)
1077{
1078 size_t size = sizeof(struct tstorm_eth_mac_filter_config);
1079
1080 u32 addr = BAR_TSTRORM_INTMEM +
1081 TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid);
1082
1083 __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
1084}
1085
1086static inline void storm_memset_cmng(struct bnx2x *bp,
1087 struct cmng_struct_per_port *cmng,
1088 u8 port)
1089{
1090 size_t size =
1091 sizeof(struct rate_shaping_vars_per_port) +
1092 sizeof(struct fairness_vars_per_port) +
1093 sizeof(struct safc_struct_per_port) +
1094 sizeof(struct pfc_struct_per_port);
1095
1096 u32 addr = BAR_XSTRORM_INTMEM +
1097 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
1098
1099 __storm_memset_struct(bp, addr, size, (u32 *)cmng);
1100
1101 addr += size + 4 /* SKIP DCB+LLFC */;
1102 size = sizeof(struct cmng_struct_per_port) -
1103 size /* written */ - 4 /*skipped*/;
1104
1105 __storm_memset_struct(bp, addr, size,
1106 (u32 *)(cmng->traffic_type_to_priority_cos));
626} 1107}
627 1108
628/* HW Lock for shared dual port PHYs */ 1109/* HW Lock for shared dual port PHYs */
629void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1110void bnx2x_acquire_phy_lock(struct bnx2x *bp);
630void bnx2x_release_phy_lock(struct bnx2x *bp); 1111void bnx2x_release_phy_lock(struct bnx2x *bp);
631 1112
632void bnx2x_link_report(struct bnx2x *bp); 1113/**
633int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 1114 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
634int bnx2x_tx_int(struct bnx2x_fastpath *fp); 1115 *
635void bnx2x_init_rx_rings(struct bnx2x *bp); 1116 * @bp: driver handle
636netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 1117 * @mf_cfg: MF configuration
637 1118 *
638int bnx2x_change_mac_addr(struct net_device *dev, void *p); 1119 */
639void bnx2x_tx_timeout(struct net_device *dev); 1120static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
640void bnx2x_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp); 1121{
641void bnx2x_netif_start(struct bnx2x *bp); 1122 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
642void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 1123 FUNC_MF_CFG_MAX_BW_SHIFT;
643void bnx2x_free_irq(struct bnx2x *bp, bool disable_only); 1124 if (!max_cfg) {
644int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 1125 BNX2X_ERR("Illegal configuration detected for Max BW - "
645int bnx2x_resume(struct pci_dev *pdev); 1126 "using 100 instead\n");
646void bnx2x_free_skbs(struct bnx2x *bp); 1127 max_cfg = 100;
647int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 1128 }
648int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); 1129 return max_cfg;
649int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 1130}
650int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
651 1131
652#endif /* BNX2X_CMN_H */ 1132#endif /* BNX2X_CMN_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 14:46:48 -0400